| /linux/arch/arm/mach-lpc32xx/ |
| H A D | suspend.S | 63 @ Setup self-refresh with support for manual exit of
64 @ self-refresh mode
70 @ Wait for self-refresh acknowledge, clocks to the DRAM device
71 @ will automatically stop on start of self-refresh
76 bne 3b @ Branch until self-refresh mode starts
113 @ Re-enter run mode with self-refresh flag cleared, but no DRAM
114 @ update yet. DRAM is still in self-refresh
122 @ Clear self-refresh mode
129 @ Wait for EMC to clear self-refresh mode
133 bne 5b @ Branch until self-refresh has exited
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| H A D | pm.c | 38 * DRAM refresh
39 * DRAM clocking and refresh are slightly different for systems with DDR
44 * and exit DRAM self-refresh modes must not be executed in DRAM. A small
51 * Places DRAMs in self-refresh mode
126 * Setup SDRAM self-refresh clock to automatically disable o in lpc32xx_pm_init()
127 * start of self-refresh. This only needs to be done once. in lpc32xx_pm_init()
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| /linux/drivers/cpufreq/ |
| H A D | sa1110-cpufreq.c | 40 u_short refresh; /* refresh time for array (us) */ member
57 .refresh = 64000,
66 .refresh = 64000,
75 .refresh = 64000,
83 .refresh = 64000,
92 .refresh = 64000,
101 .refresh = 64000,
110 .refresh = 64000,
196 * Set the SDRAM refresh rate.
205 * Update the refresh period. We do this such that we always refresh
[all …]
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| /linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | rockchip,rk3399-dmc.yaml | 69 Configure the SR_IDLE value. Defines the self-refresh idle period in
70 which memories are placed into self-refresh mode if bus is idle for
79 Defines the memory self-refresh and controller clock gating idle period.
80 Memories are placed into self-refresh mode and memory controller clock
89 Defines the self-refresh power down idle period in which memories are
90 placed into self-refresh power down mode if bus is idle for
100 self-refresh mode. The controller, pi, PHY and DRAM clock will be gated
293 Configure the SR_IDLE value in nanoseconds. Defines the self-refresh idle
294 period in which memories are placed into self-refresh mode if bus is idle
300 Defines the memory self-refresh and controller clock gating idle period in nanoseconds.
[all …]
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| /linux/include/soc/at91/ |
| H A D | sama7-ddr.h | 55 #define UDDRC_STAT_SELFREF_TYPE_DIS (0x0 << 4) /* SDRAM is not in Self-refresh */
56 #define UDDRC_STAT_SELFREF_TYPE_PHY (0x1 << 4) /* SDRAM is in Self-refresh, which was caused by PH…
57 …FREF_TYPE_SW (0x2 << 4) /* SDRAM is in Self-refresh, which was not caused solely under Automatic S…
58 …T_SELFREF_TYPE_AUTO (0x3 << 4) /* SDRAM is in Self-refresh, which was caused by Automatic Self-ref…
59 #define UDDRC_STAT_SELFREF_TYPE_MSK (0x3 << 4) /* Self-refresh type mask */
63 #define UDDRC_STAT_OPMODE_SELF_REFRESH (0x3 << 0) /* Self-refresh */
67 #define UDDRC_PWRCTL_SELFREF_EN (1 << 0) /* Automatic self-refresh */
68 #define UDDRC_PWRCTL_SELFREF_SW (1 << 5) /* Software self-refresh */
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| H A D | at91sam9_sdramc.h | 26 #define AT91_SDRAMC_TR 0x04 /* SDRAM Controller Refresh Timer Register */
27 #define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */
54 #define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
62 #define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */
63 #define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
74 #define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */
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| H A D | at91sam9_ddrsdr.h | 21 #define AT91_DDRSDRC_RTR 0x04 /* Refresh Timer Register */
22 #define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */
59 #define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
63 #define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
64 #define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
81 #define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */
82 #define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
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| /linux/drivers/video/fbdev/core/ |
| H A D | fbcvt.c | 38 u32 refresh; member
230 cvt->xres, cvt->yres, cvt->refresh); in fb_cvt_print_name()
262 mode->refresh = cvt->f_refresh; in fb_cvt_convert_to_mode()
281 * @mode: pointer to fb_videomode; xres, yres, refresh and vmode must be
288 * @mode is filled with computed values. If interlaced, the refresh field
311 cvt.refresh = mode->refresh; in fb_find_mode_cvt()
312 cvt.f_refresh = cvt.refresh; in fb_find_mode_cvt()
315 if (!cvt.xres || !cvt.yres || !cvt.refresh || cvt.f_refresh > INT_MAX) { in fb_find_mode_cvt()
320 if (!(cvt.refresh == 50 || cvt.refresh == 60 || cvt.refresh == 70 || in fb_find_mode_cvt()
321 cvt.refresh == 85)) { in fb_find_mode_cvt()
[all …]
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| /linux/tools/perf/pmu-events/arch/arm64/thead/yitian710/sys/ |
| H A D | ali_drw.json | 171 "BriefDescription": "Rank0 enters self-refresh(SRE).",
178 "BriefDescription": "Rank1 enters self-refresh(SRE).",
185 "BriefDescription": "Rank2 enters self-refresh(SRE).",
192 "BriefDescription": "Rank3 enters self-refresh(SRE).",
227 "BriefDescription": "A cycle that Rank0 stays in self-refresh mode.",
234 "BriefDescription": "A cycle that Rank1 stays in self-refresh mode.",
241 "BriefDescription": "A cycle that Rank2 stays in self-refresh mode.",
248 "BriefDescription": "A cycle that Rank3 stays in self-refresh mode.",
255 "BriefDescription": "An auto-refresh(REF) command to DRAM.",
262 "BriefDescription": "A critical auto-refresh(REF) command to DRAM.",
[all …]
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| /linux/arch/arm/mach-pxa/ |
| H A D | sleep.S | 55 @ prepare SDRAM refresh settings
59 @ enable SDRAM self-refresh mode
96 @ prepare SDRAM refresh settings
100 @ enable SDRAM self-refresh mode
108 @ as possible to eliminate messing about with the refresh clock
160 @ external accesses after SDRAM is put in self-refresh mode
161 @ (see Errata 38 ...hangs when entering self-refresh mode)
166 @ put SDRAM into self-refresh
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| /linux/arch/arm/mach-socfpga/ |
| H A D | self-refresh.S | 44 * return value: lower 16 bits: loop count going into self refresh
45 * upper 16 bits: loop count exiting self refresh
53 /* Enable self refresh: set sdr.ctrlgrp.lowpwreq.selfrshreq = 1 */
89 /* Disable self-refresh: set sdr.ctrlgrp.lowpwreq.selfrshreq = 0 */
109 * Shift loop count for exiting self refresh into upper 16 bits.
110 * Leave loop count for requesting self refresh in lower 16 bits.
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| /linux/arch/sh/boards/mach-kfr2r09/ |
| H A D | sdram.S | 3 * KFR2R09 sdram self/auto-refresh setup code
15 /* code to enter and leave self-refresh. must be self-contained.
21 /* DBSC: put memory in self-refresh mode */
37 /* DBSC: put memory in auto-refresh mode */
55 /* DBSC: re-initialize and put in auto-refresh */
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| /linux/Documentation/fb/ |
| H A D | modedb.rst | 23 <xres>x<yres>[M][R][-<bpp>][@<refresh>][i][m][eDd]
24 <name>[-<bpp>][@<refresh>]
26 with <xres>, <yres>, <bpp> and <refresh> decimal numbers and <name> a string.
38 <bpp> and <refresh>, if specified) the timings will be calculated using
91 and coordinated set of standard formats, display refresh rates, and
102 pixelclock, the horizontal sync frequency, or the vertical refresh rate.
137 - acceptable refresh rates are 50, 60, 70 or 85 Hz only
138 - if reduced blanking, the refresh rate must be at 60Hz
162 video=<driver>:<xres>x<yres>[-<bpp>][@refresh]
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| H A D | uvesafb.rst | 38 or most optimal resolution/refresh rate for your setup will not work
43 - Adjusting the refresh rate is only possible with a VBE 3.0 compliant
45 compliant, while they simply ignore any refresh rate settings.
121 using this option implies that any refresh rate adjustments will
122 be ignored and the refresh rate will stay at your BIOS default
164 Use the default refresh rate (60 Hz) if set to 1.
179 Uvesafb will set a video mode with the default refresh rate and timings
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| /linux/drivers/cpuidle/ |
| H A D | cpuidle-zynq.c | 9 * The cpu idle uses wait-for-interrupt and RAM self refresh in order
12 * #2 wait-for-interrupt and RAM self refresh
28 /* Add code for DDR self refresh start */ in zynq_enter_idle()
44 .desc = "WFI and RAM Self Refresh",
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| /linux/arch/sh/boards/mach-ecovec24/ |
| H A D | sdram.S | 3 * Ecovec24 sdram self/auto-refresh setup code
15 /* code to enter and leave self-refresh. must be self-contained.
21 /* DBSC: put memory in self-refresh mode */
41 /* DBSC: put memory in auto-refresh mode */
55 /* DBSC: re-initialize and put in auto-refresh */
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| /linux/drivers/virt/coco/guest/ |
| H A D | tsm-mr.c | 25 * Given tm->refresh() is potentially expensive, tm_digest_read() caches MR
26 * values and calls tm->refresh() only when necessary. Only live MRs (i.e., with
27 * %TSM_MR_F_LIVE set) can trigger tm->refresh(), while others are assumed to
29 * been tm->write() calls since the last tm->refresh(). That is, tm->refresh()
65 * ctx->refresh() is necessary only for LIVE MRs, while others retain in tm_digest_read()
76 rc = ctx->tm->refresh(ctx->tm); in tm_digest_read()
151 if ((tm->mrs[i].mr_flags & TSM_MR_F_LIVE) && !tm->refresh) in tsm_mr_create_attribute_group()
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| /linux/arch/sh/boards/mach-migor/ |
| H A D | sdram.S | 3 * Migo-R sdram self/auto-refresh setup code
15 /* code to enter and leave self-refresh. must be self-contained.
21 /* SBSC: disable power down and put in self-refresh mode */
42 /* SBSC: set auto-refresh mode */
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| /linux/arch/sh/boards/mach-ap325rxa/ |
| H A D | sdram.S | 3 * AP325RXA sdram self/auto-refresh setup code
15 /* code to enter and leave self-refresh. must be self-contained.
21 /* SBSC: disable power down and put in self-refresh mode */
42 /* SBSC: set auto-refresh mode */
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| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-driver-hid-picolcd | 31 Description: Make it possible to adjust defio refresh rate.
33 Reading: returns list of available refresh rates (expressed in Hz),
34 the active refresh rate being enclosed in brackets ('[' and ']')
36 Writing: accepts new refresh rate expressed in integer Hz
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| /linux/arch/sh/boards/mach-se/7724/ |
| H A D | sdram.S | 3 * MS7724SE sdram self/auto-refresh setup code
15 /* code to enter and leave self-refresh. must be self-contained.
21 /* DBSC: put memory in self-refresh mode */
37 /* DBSC: put memory in auto-refresh mode */
72 /* DBSC: re-initialize and put in auto-refresh */
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| /linux/arch/sh/kernel/cpu/shmobile/ |
| H A D | pm.c | 28 * Sleep Self-Refresh mode is above plus RAM put in Self-Refresh
29 * Standby Self-Refresh mode is above plus stopped clocks
107 /* part 2: board specific code to enter self-refresh mode */ in sh_mobile_register_self_refresh()
113 /* part 3: board specific code to resume from self-refresh mode */ in sh_mobile_register_self_refresh()
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| /linux/drivers/gpu/drm/kmb/ |
| H A D | kmb_crtc.c | 192 int refresh; in kmb_crtc_mode_valid() local
206 refresh = drm_mode_vrefresh(mode); in kmb_crtc_mode_valid()
207 if (refresh < KMB_MIN_VREFRESH || refresh > KMB_MAX_VREFRESH) { in kmb_crtc_mode_valid()
208 drm_dbg(dev, "refresh = %d less than %d or greater than %d", in kmb_crtc_mode_valid()
209 refresh, KMB_MIN_VREFRESH, KMB_MAX_VREFRESH); in kmb_crtc_mode_valid()
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| /linux/arch/mips/alchemy/common/ |
| H A D | sleeper.S | 104 sw zero, 0x0020(a0) /* Auto Refresh */
130 sw zero, 0x08d0(a0) /* Self Refresh */
133 /* wait for sdram to enter self-refresh mode */
189 /* auto refresh */
200 /* issue the Self Refresh command */
206 /* wait for sdram to enter self-refresh mode */
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| /linux/drivers/fpga/ |
| H A D | machxo2-spi.c | 141 static const u8 refresh[] = LSC_REFRESH; in machxo2_cleanup() local
158 tx[1].tx_buf = &refresh; in machxo2_cleanup()
159 tx[1].len = sizeof(refresh); in machxo2_cleanup()
298 static const u8 refresh[] = LSC_REFRESH; in machxo2_write_complete() local
324 tx[1].tx_buf = &refresh; in machxo2_write_complete()
325 tx[1].len = sizeof(refresh); in machxo2_write_complete()
333 /* check refresh status */ in machxo2_write_complete()
351 dev_err(&mgr->dev, "Refresh failed.\n"); in machxo2_write_complete()
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