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/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dnvidia,tegra20-sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/nvidia,tegra20-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
18 mmc-controller.yaml and the properties for the Tegra SDHCI controller.
23 - enum:
24 - nvidia,tegra20-sdhci
25 - nvidia,tegra30-sdhci
[all …]
H A Dmarvell,xenon-sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/marvell,xenon-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 mmc-controller.yaml and the properties used by the Xenon implementation.
20 - Ulf Hansson <ulf.hansson@linaro.org>
25 - enum:
26 - marvell,armada-cp110-sdhci
27 - marvell,armada-ap806-sdhci
29 - items:
[all …]
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dnvidia,tegra194-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra194 XUSB pad controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The Tegra XUSB pad controller manages a set of I/O lanes (with differential
16 is controlled by a HW block referred to as a "pad" in the Tegra hardware
17 documentation. Each such "pad" may control either one or multiple lanes,
[all …]
H A Dnvidia,tegra186-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra186 XUSB pad controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The Tegra XUSB pad controller manages a set of I/O lanes (with differential
16 is controlled by a HW block referred to as a "pad" in the Tegra hardware
17 documentation. Each such "pad" may control either one or multiple lanes,
[all …]
H A Dnvidia,tegra124-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra124 XUSB pad controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The Tegra XUSB pad controller manages a set of I/O lanes (with differential
16 is controlled by a HW block referred to as a "pad" in the Tegra hardware
17 documentation. Each such "pad" may control either one or multiple lanes,
[all …]
H A Dnvidia,tegra210-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xus
[all...]
H A Dfsl,imx8-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Richard Zhu <hongxing.zhu@nxp.com>
13 "#phy-cells":
18 - fsl,imx8mm-pcie-phy
19 - fsl,imx8mp-pcie-phy
27 clock-names:
29 - const: ref
[all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/tegra/
H A Dnvidia,tegra20-pmc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra30-pmc
18 - nvidia,tegra114-pmc
19 - nvidia,tegra124-pmc
[all …]
H A Dnvidia,tegra186-pmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra186-pmc
17 - nvidia,tegra194-pmc
18 - nvidia,tegra234-pmc
19 - nvidia,tegra264-pmc
[all …]
/freebsd/sys/contrib/device-tree/Bindings/soc/tegra/
H A Dnvidia,tegra20-pmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra30-pmc
18 - nvidia,tegra114-pmc
19 - nvidia,tegra124-pmc
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Daltr,socfpga-stmmac.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/altr,socfpga-stmmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matthew Gerlach <matthew.gerlach@altera.com>
16 # TODO: Determine how to handle the Arria10 reset-name, stmmaceth-ocp, that
24 - altr,socfpga-stmmac
25 - altr,socfpga-stmmac-a10-s10
26 - altr,socfpga-stmmac-agilex5
29 - compatible
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Datmel,at91rm9200-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/atmel,at91rm9200-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manikandan Muralidharan <manikandan.m@microchip.com>
13 The AT91 Pinmux Controller, enables the IC to share one PAD to several
14 functional blocks. The sharing is done by multiplexing the PAD input/output
15 signals. For each PAD there are up to 8 muxing options (called periph modes).
16 Since different modules require different PAD settings (like pull up, keeper,
17 etc) the controller controls also the PAD settings parameters.
[all …]
H A Dthead,th1520-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/thead,th1520-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: T-Head TH1520 SoC pin controller
10 - Emil Renner Berthing <emil.renner.berthing@canonical.com>
13 Pinmux and pinconf controller in the T-Head TH1520 RISC-V SoC.
17 PADCTRL_AOSYS -> PAD Group 1
18 PADCTRL1_APSYS -> PAD Group 2
19 PADCTRL0_APSYS -> PAD Group 3
[all …]
H A Drockchip,pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
13 The Rockchip Pinmux Controller enables the IC to share one PAD
15 the PAD input/output signals. For each PAD there are several muxing
18 Please refer to pinctrl-bindings.txt in this directory for details of the
26 various pad settings such as pull-up, etc.
29 defined as gpio sub-nodes of the pinmux controller.
34 - rockchip,px30-pinctrl
[all …]
H A Dfsl,scu-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/fsl,scu-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: i.MX SCU Client Device Node - Pinctrl Based on SCU Message Protocol
10 - Dong Aisheng <aisheng.dong@nxp.com>
13 Client nodes are maintained as children of the relevant IMX-SCU device node.
15 (Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt)
18 - $ref: pinctrl.yaml#
23 - fsl,imx8qm-iomuxc
[all …]
H A Dfsl,imx7d-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/fsl,imx7d-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
13 Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
19 - enum:
20 - fsl,imx7d-iomuxc
21 - fsl,imx7d-iomuxc-lpsr
26 fsl,input-sel:
[all …]
H A Dfsl,imx93-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/fsl,imx93-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peng Fan <peng.fan@nxp.com>
13 Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
17 - $ref: pinctrl.yaml#
21 const: fsl,imx93-iomuxc
40 be found in <arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h>. The last
41 integer CONFIG is the pad setting value like pull-up on this pin. Please
[all …]
H A Dfsl,imx8mm-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/fsl,imx8mm-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Anson Huang <Anson.Huang@nxp.com>
13 Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
18 const: fsl,imx8mm-iomuxc
37 be found in <arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h>. The last
38 integer CONFIG is the pad setting value like pull-up on this pin. Please
40 $ref: /schemas/types.yaml#/definitions/uint32-matrix
[all …]
H A Dfsl,imx8mn-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/fsl,imx8mn-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Anson Huang <Anson.Huang@nxp.com>
13 Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
18 const: fsl,imx8mn-iomuxc
37 be found in <arch/arm64/boot/dts/freescale/imx8mn-pinfunc.h>. The last
38 integer CONFIG is the pad setting value like pull-up on this pin. Please
40 $ref: /schemas/types.yaml#/definitions/uint32-matrix
[all …]
H A Dfsl,imx8mp-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/fsl,imx8mp-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Anson Huang <Anson.Huang@nxp.com>
13 Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
18 const: fsl,imx8mp-iomuxc
37 be found in <arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h>. The last
38 integer CONFIG is the pad setting value like pull-up on this pin. Please
40 $ref: /schemas/types.yaml#/definitions/uint32-matrix
[all …]
H A Dfsl,imx8mq-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/fsl,imx8mq-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Anson Huang <Anson.Huang@nxp.com>
13 Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
18 const: fsl,imx8mq-iomuxc
37 be found in <arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h>. The last
38 integer CONFIG is the pad setting value like pull-up on this pin. Please
40 $ref: /schemas/types.yaml#/definitions/uint32-matrix
[all …]
/freebsd/sys/contrib/xen/io/
H A Dpvcalls.h2 * pvcalls.h -- Xen PV Calls Protocol
50 grant_ref_t ref[]; member
71 uint8_t pad[4]; member
78 grant_ref_t ref; member
80 uint8_t pad[4]; member
85 uint8_t pad[7]; member
95 uint8_t pad[4]; member
100 grant_ref_t ref; member
118 uint32_t pad; member
155 * c-file-style: "BSD"
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/
H A Darm,pl11x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liviu Dudau <Liviu.Dudau@arm.com>
11 - Andre Przywara <andre.przywara@arm.com>
24 - arm,pl110
25 - arm,pl111
27 - compatible
32 - enum:
33 - arm,pl110
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/tegra/
H A Dnvidia,tegra124-sor.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-so
[all...]
/freebsd/sys/contrib/device-tree/Bindings/firmware/
H A Dnxp,imx95-scmi-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/firmware/nxp,imx95-scmi-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Peng Fan <peng.fan@nxp.com>
14 - $ref: /schemas/pinctrl/pinctrl.yaml
31 be found in <arch/arm64/boot/dts/freescale/imx95-pinfunc.h>. The last
32 integer CONFIG is the pad setting value like pull-up on this pin.
34 $ref: /schemas/types.yaml#/definitions/uint32-matrix
37 - description: |
[all …]

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