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/linux/drivers/media/pci/bt8xx/
H A Dbtcx-risc.c4 btcx-risc.c
6 bt848/bt878/cx2388x risc code generator.
23 #include "btcx-risc.h"
37 /* allocate/free risc memory */
42 struct btcx_riscmem *risc) in btcx_riscmem_free() argument
44 if (NULL == risc->cpu) in btcx_riscmem_free()
49 memcnt, (unsigned long)risc->dma); in btcx_riscmem_free()
51 dma_free_coherent(&pci->dev, risc->size, risc->cpu, risc->dma); in btcx_riscmem_free()
52 memset(risc,0,sizeof(*risc)); in btcx_riscmem_free()
56 struct btcx_riscmem *risc, in btcx_riscmem_alloc() argument
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H A Dbttv-risc.c4 bttv-risc.c -- interfaces to other kernel modules
6 bttv risc code handling
32 /* risc code generators */
35 bttv_risc_packed(struct bttv *btv, struct btcx_riscmem *risc, in bttv_risc_packed() argument
46 /* estimate risc mem: worst case is one write per page border + in bttv_risc_packed()
54 if ((rc = btcx_riscmem_alloc(btv->c.pci,risc,instructions)) < 0) in bttv_risc_packed()
58 rp = risc->cpu; in bttv_risc_packed()
108 risc->jmp = rp; in bttv_risc_packed()
109 WARN_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size); in bttv_risc_packed()
114 bttv_risc_planar(struct bttv *btv, struct btcx_riscmem *risc, in bttv_risc_planar() argument
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/linux/Documentation/arch/riscv/
H A Dhwprobe.rst3 RISC-V Hardware Probing Interface
6 The RISC-V hardware probing interface is based around a single syscall, which
49 as defined by the RISC-V privileged architecture specification.
52 defined by the RISC-V privileged architecture specification.
55 defined by the RISC-V privileged architecture specification.
76 minimumNumber/maximumNumber, not minNum/maxNum") of the RISC-V ISA manual.
79 by version 2.2 of the RISC-V ISA manual.
82 version 1.0 of the RISC-V Vector extension manual.
128 defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
131 defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
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H A Dpatch-acceptance.rst8 The RISC-V instruction set architecture is developed in the open:
13 challenge for RISC-V Linux maintenance. Linux maintainers disapprove
16 principles to the RISC-V-related code that will be accepted for
22 RISC-V has a patchwork instance, where the status of patches can be checked:
26 If your patch does not appear in the default view, the RISC-V maintainers have
31 RISC-V `for-next` and `fixes` branches, depending on whether the patch has been
32 detected as a fix. Failing those, it will use the RISC-V `master` branch.
42 specifications from the RISC-V foundation this means "Frozen" or
47 Additionally, the RISC-V specification allows implementers to create
49 to go through any review or ratification process by the RISC-V
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H A Dboot.rst4 RISC-V Kernel Boot Requirements and Constraints
10 This document describes what the RISC-V kernel expects from bootloaders and
19 The RISC-V kernel expects the following of bootloaders and platform firmware:
24 The RISC-V kernel expects:
32 The RISC-V kernel expects:
39 The RISC-V kernel must not map any resident memory, or memory protected with
46 The RISC-V kernel expects to be placed at a PMD boundary (2MB aligned for rv64
53 The firmware can pass either a devicetree or ACPI tables to the RISC-V kernel.
71 support older firmwares without SBI HSM extension and M-mode RISC-V kernel.
75 booting the RISC-V kernel because it can support CPU hotplug and kexec.
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H A Dvm-layout.rst4 Virtual Memory Layout on RISC-V Linux
10 This document describes the virtual memory layout used by the RISC-V Linux
13 RISC-V Linux Kernel 32bit
16 RISC-V Linux Kernel SV32
21 RISC-V Linux Kernel 64bit
24 The RISC-V privileged architecture document states that the 64bit addresses
28 the RISC-V Linux Kernel resides.
30 RISC-V Linux Kernel SV39
67 RISC-V Linux Kernel SV48
103 RISC-V Linux Kernel SV57
/linux/drivers/media/pci/cx25821/
H A Dcx25821-core.c299 static int cx25821_risc_decode(u32 risc) in cx25821_risc_decode() argument
331 risc, instr[risc >> 28] ? instr[risc >> 28] : "INVALID"); in cx25821_risc_decode()
333 if (risc & (1 << (i + 12))) in cx25821_risc_decode()
336 pr_cont(" count=%d ]\n", risc & 0xfff); in cx25821_risc_decode()
337 return incr[risc >> 28] ? incr[risc >> 28] : 1; in cx25821_risc_decode()
419 unsigned int bpl, u32 risc) in cx25821_sram_channel_setup() argument
461 cx_write(ch->cmds_start + 0, risc); in cx25821_sram_channel_setup()
487 unsigned int bpl, u32 risc) in cx25821_sram_channel_setup_audio() argument
525 cx_write(ch->cmds_start + 0, risc); in cx25821_sram_channel_setup_audio()
555 "init risc lo", in cx25821_sram_channel_dump()
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H A Dcx25821-alsa.c53 struct cx25821_riscmem risc; member
225 /* Make sure RISC/FIFO are off before changing FIFO/RISC settings */ in _cx25821_start_audio_dma()
231 buf->risc.dma); in _cx25821_start_audio_dma()
263 /* Turn on audio downstream fifo and risc enable 0x101 */ in _cx25821_start_audio_dma()
325 /* risc op code error */ in cx25821_aud_irq()
327 pr_warn("WARNING %s/1: Audio risc op code error\n", dev->name); in cx25821_aud_irq()
398 struct cx25821_riscmem *risc = &chip->buf->risc; in dsp_buffer_free() local
405 dma_free_coherent(&chip->pci->dev, risc->size, risc->cpu, risc->dma); in dsp_buffer_free()
534 ret = cx25821_risc_databuffer_audio(chip->pci, &buf->risc, buf->sglist, in snd_cx25821_hw_params()
542 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC); in snd_cx25821_hw_params()
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/linux/drivers/media/pci/cx88/
H A Dcx88-core.c130 int cx88_risc_buffer(struct pci_dev *pci, struct cx88_riscmem *risc, in cx88_risc_buffer() argument
145 * estimate risc mem: worst case is one write per page border + in cx88_risc_buffer()
153 risc->size = instructions * 8; in cx88_risc_buffer()
154 risc->dma = 0; in cx88_risc_buffer()
155 risc->cpu = dma_alloc_coherent(&pci->dev, risc->size, &risc->dma, in cx88_risc_buffer()
157 if (!risc->cpu) in cx88_risc_buffer()
160 /* write risc instructions */ in cx88_risc_buffer()
161 rp = risc->cpu; in cx88_risc_buffer()
171 risc->jmp = rp; in cx88_risc_buffer()
172 WARN_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size); in cx88_risc_buffer()
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H A Dcx88-mpeg.c83 dev->ts_packet_size, buf->risc.dma); in cx8802_start_dma()
221 struct cx88_riscmem *risc = &buf->risc; in cx8802_buf_prepare() local
228 rc = cx88_risc_databuffer(dev->pci, risc, sgt->sgl, in cx8802_buf_prepare()
231 if (risc->cpu) in cx8802_buf_prepare()
232 dma_free_coherent(&dev->pci->dev, risc->size, in cx8802_buf_prepare()
233 risc->cpu, risc->dma); in cx8802_buf_prepare()
234 memset(risc, 0, sizeof(*risc)); in cx8802_buf_prepare()
248 buf->risc.cpu[1] = cpu_to_le32(buf->risc.dma + 8); in cx8802_buf_queue()
249 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_CNT_INC); in cx8802_buf_queue()
250 buf->risc.jmp[1] = cpu_to_le32(buf->risc.dma + 8); in cx8802_buf_queue()
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H A Dcx88-alsa.c46 struct cx88_riscmem risc; member
119 /* Make sure RISC/FIFO are off before changing FIFO/RISC settings */ in _cx88_start_audio_dma()
123 cx88_sram_channel_setup(chip->core, audio_ch, buf->bpl, buf->risc.dma); in _cx88_start_audio_dma()
149 /* Enables Risc Processor */ in _cx88_start_audio_dma()
151 /* audio downstream FIFO and RISC enable */ in _cx88_start_audio_dma()
219 /* risc op code error */ in cx8801_aud_irq()
221 pr_warn("Audio risc op code error\n"); in cx8801_aud_irq()
352 struct cx88_riscmem *risc = &chip->buf->risc; in dsp_buffer_free() local
359 if (risc->cpu) in dsp_buffer_free()
360 dma_free_coherent(&chip->pci->dev, risc->size, risc->cpu, in dsp_buffer_free()
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/linux/Documentation/translations/it_IT/arch/riscv/
H A Dpatch-acceptance.rst12 L'insieme di istruzioni RISC-V sono sviluppate in modo aperto: le
18 supporto RISC-V nel kernel Linux. I manutentori Linux non amano
22 relativo all'architettura RISC-V che verrà accettato per l'inclusione
28 RISC-V ha un'istanza di patchwork dov'è possibile controllare lo stato delle patch:
32 Se la vostra patch non appare nella vista predefinita, i manutentori di RISC-V
38 riferimento HEAD corrente dei rami `for-next` e `fixes` dei sorgenti RISC-V,
40 caso contrario, utilizzerà il ramo `master` di RISC-V. L'esatto commit a cui è
49 RISC-V li classifica come "Frozen" o "Retified". (Ovviamente, gli
53 In aggiunta, la specifica RISC-V permette agli implementatori di
55 attraverso il processo di revisione della fondazione RISC-V. Per
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/linux/Documentation/translations/zh_CN/arch/riscv/
H A Dboot.rst11 RISC-V内核启动要求和限制
24 RISC-V内核对引导加载程序和平台固件有以下要求:
29 RISC-V内核期望:
37 RISC-V内核期望:
44 RISC-V内核在直接映射中不能映射任何常驻内存或用PMPs保护的内存,
50 RISC-V内核期望被放置在PMD边界(对于rv64为2MB对齐,对于rv32为4MB对齐)。
83 使用UEFI启动时,RISC-V内核将只使用EFI内存映射来填充系统内存。
94 RISC-V内核。EFI stub使用以下方法之一获取引导hartid:
105 RISC-V内核的早期启动过程遵循以下约束:
139 的,并且与``setup_vm_final()``建立的映射一起使用,RISC-V内核使用
H A Dvm-layout.rst12 RISC-V Linux上的虚拟内存布局
20 32位 RISC-V Linux 内核
23 RISC-V Linux Kernel SV32
28 64位 RISC-V Linux 内核
31 RISC-V特权架构文档指出,64位地址 "必须使第63-48位值都等于第47位,否则将发生缺页异常。":这将虚
35 RISC-V Linux Kernel SV39
71 RISC-V Linux Kernel SV48
/linux/Documentation/devicetree/bindings/timer/
H A Driscv,timer.yaml7 title: RISC-V timer
13 RISC-V platforms always have a RISC-V timer device for the supervisor-mode
14 based on the time CSR defined by the RISC-V privileged specification. The
15 timer interrupts of this device are configured using the RISC-V SBI Time
16 extension or the RISC-V Sstc extension.
18 The clock frequency of RISC-V timer device is specified via the
/linux/drivers/media/pci/mantis/
H A Dmantis_dma.c43 /* MANTIS_BUF_SIZE / MANTIS_DMA_TR_UNITS must not exceed MANTIS_RISC_SIZE (4k RISC cmd buffer) */
44 #define MANTIS_RISC_SIZE PAGE_SIZE /* RISC program must fit here. */
62 "RISC=0x%lx cpu=0x%p size=%lx", in mantis_dma_exit()
101 "RISC program allocation failed"); in mantis_alloc_buffers()
108 "RISC=0x%lx cpu=0x%p size=%lx", in mantis_alloc_buffers()
128 /* Stop RISC Engine */ in mantis_dma_init()
144 dprintk(MANTIS_DEBUG, 1, "Mantis create RISC program"); in mantis_risc_program()
147 dprintk(MANTIS_DEBUG, 1, "risc len lines %u, bytes per line %u, bytes per DMA tr %u", in mantis_risc_program()
152 dprintk(MANTIS_DEBUG, 1, "RISC PROG line=[%d], step=[%d]", line, step); in mantis_risc_program()
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Driscv,cpu-intc.yaml7 title: RISC-V Hart-Level Interrupt Controller (HLIC)
10 RISC-V cores include Control Status Registers (CSRs) which are local to
11 each CPU core (HART in RISC-V terminology) and can be read or written by
16 The RISC-V supervisor ISA manual specifies three interrupt sources that are
25 All RISC-V systems that conform to the supervisor ISA specification are
50 The interrupt sources are defined by the RISC-V supervisor ISA manual,
/linux/drivers/media/pci/cx23885/
H A Dcx23885-alsa.c160 /* Make sure RISC/FIFO are off before changing FIFO/RISC settings */ in cx23885_start_audio_dma()
165 buf->risc.dma); in cx23885_start_audio_dma()
192 cx_set(DEV_CNTRL2, (1<<5)); /* Enables Risc Processor */ in cx23885_start_audio_dma()
194 RISC enable */ in cx23885_start_audio_dma()
236 /* risc op code error */ in cx23885_audio_irq()
238 pr_warn("%s/1: Audio risc op code error\n", in cx23885_audio_irq()
261 struct cx23885_riscmem *risc; in dsp_buffer_free() local
268 risc = &chip->buf->risc; in dsp_buffer_free()
269 dma_free_coherent(&chip->pci->dev, risc->size, risc->cpu, risc->dma); in dsp_buffer_free()
393 ret = cx23885_risc_databuffer(chip->pci, &buf->risc, buf->sglist, in snd_cx23885_hw_params()
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/linux/drivers/media/dvb-frontends/
H A Ddib9000.c93 } risc; member
239 if (state->platform.risc.fw_is_running && (reg < 1024)) in dib9000_read16_attr()
323 if (state->platform.risc.fw_is_running && (reg < 1024)) { in dib9000_write16_attr()
428 …state->platform.risc.memcmd = -1; /* if it was called directly reset it - to force a future setup-… in dib9000_risc_mem_setup_cmd()
433 struct dib9000_fe_memory_map *m = &state->platform.risc.fe_mm[cmd & 0x7f]; in dib9000_risc_mem_setup()
435 if (state->platform.risc.memcmd == cmd && /* same command */ in dib9000_risc_mem_setup()
439 state->platform.risc.memcmd = cmd; in dib9000_risc_mem_setup()
444 if (!state->platform.risc.fw_is_running) in dib9000_risc_mem_read()
447 if (mutex_lock_interruptible(&state->platform.risc.mem_lock) < 0) { in dib9000_risc_mem_read()
453 mutex_unlock(&state->platform.risc.mem_lock); in dib9000_risc_mem_read()
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/linux/drivers/cpuidle/
H A DKconfig.riscv3 # RISC-V CPU Idle drivers
7 bool "RISC-V SBI CPU idle Driver"
13 Select this option to enable RISC-V SBI firmware based CPU idle
14 driver for RISC-V systems. This drivers also supports hierarchical
/linux/Documentation/devicetree/bindings/iommu/
H A Driscv,iommu.yaml7 title: RISC-V IOMMU Architecture Implementation
13 The RISC-V IOMMU provides memory address translation and isolation for
17 It supports identical translation table format to the RISC-V address
24 For information on assigning RISC-V IOMMU to its peripheral devices,
62 Wired interrupt vectors available for RISC-V IOMMU to notify the
63 RISC-V HARTS. The cause to interrupt vector is software defined
/linux/drivers/scsi/
H A Dqlogicpti.h401 #define SBUS_CTRL_ERIRQ 0x0004 /* Enable RISC Processor Interrupts */
409 #define SBUS_STAT_RINT 0x0004 /* RISC Processor IRQ pending */
463 /* RISC processor status register */
466 #define RISC_PSR_RIRQ 0x2000 /* RISC irq status */
479 /* RISC processor memory timing register */
487 #define HCCTRL_RESET 0x1000 /* CMD: Reset RISC cpu */
488 #define HCCTRL_PAUSE 0x2000 /* CMD: Pause RISC cpu */
489 #define HCCTRL_REL 0x3000 /* CMD: Release paused RISC cpu */
490 #define HCCTRL_STEP 0x4000 /* CMD: Single step RISC cpu */
493 #define HCCTRL_CRIRQ 0x7000 /* CMD: Clear RISC cpu irq */
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/linux/Documentation/filesystems/
H A Dadfs.rst25 on a RISC OS Filecore filesystem, but will allow the data within files
45 the RISC OS file type will be added. Default 0.
95 RISC OS file type suffix
98 RISC OS file types are stored in bits 19..8 of the file load address.
100 To enable non-RISC OS systems to be used to store files without losing
104 naming convention is now also used by RISC OS emulators such as RPCEmu.
/linux/sound/parisc/
H A DKconfig2 # ALSA PA-RISC drivers
9 Support for GSC sound devices on PA-RISC architectures.
18 chip found in most GSC-based PA-RISC workstations. It's frequently
/linux/sound/pci/
H A Dbt87x.c50 #define REG_RISC_STRT_ADD 0x114 /* RISC program start address */
51 #define REG_RISC_COUNT 0x120 /* RISC program counter */
55 #define INT_RISCI (1 << 11) /* RISC instruction IRQ bit set */
60 #define INT_RIPERR (1 << 16) /* RISC instruction parity error */
65 #define INT_RISCS_SHIFT 28 /* RISC status bits */
98 /* RISC instruction opcodes */
105 /* RISC instruction bits */
215 __le32 *risc; in snd_bt87x_create_risc() local
222 risc = (__le32 *)chip->dma_risc.area; in snd_bt87x_create_risc()
224 *risc in snd_bt87x_create_risc()
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