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/linux/include/media/
H A Dcec-pin.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * cec-pin.h - low-level CEC pin control
15 * struct cec_pin_ops - low-level CEC pin operations
16 * @read: read the CEC pin. Returns > 0 if high, 0 if low, or an error
18 * @low: drive the CEC pin low.
19 * @high: stop driving the CEC pin. The pull-up will drive the pin
20 * high, unless someone else is driving the pin low.
21 * @enable_irq: optional, enable the interrupt to detect pin voltage changes.
26 * @read_hpd: optional. Read the HPD pin. Returns > 0 if high, 0 if low or
28 * @read_5v: optional. Read the 5V pin. Returns > 0 if high, 0 if low or
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dsprd,sc9860-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/sprd,sc9860-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Spreadtrum SC9860 Pin Controller
10 - Baolin Wang <baolin.wang@linux.alibaba.com>
13 The Spreadtrum pin controller are organized in 3 blocks (types).
18 pad driving level, system control select and so on ("domain pad
19 driving level": One pin can output 3.0v or 1.8v, depending on the
21 select 3.0v, then the pin can output 3.0v. "system control" is used
[all …]
H A Drenesas,rzn1-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzn1-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/N1 Pin Controller
10 - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
16 - const: renesas,r9a06g032-pinctrl # RZ/N1D
17 - const: renesas,rzn1-pinctrl # Generic RZ/N1
21 - description: GPIO Multiplexing Level1 Register Block
[all …]
H A Dmicrochip,pic32-pinctrl.txt1 * Microchip PIC32 Pin Controller
3 Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
4 ../interrupt-controller/interrupts.txt for generic information regarding
5 pin controller, GPIO, and interrupt bindings.
7 PIC32 'pin configuration node' is a node of a group of pins which can be
11 Required properties for pin controller node:
12 - compatible: "microchip,pic32mada-pinctrl"
13 - reg: Address range of the pinctrl registers.
14 - clocks: Clock specifier (see clock bindings for details)
16 Required properties for pin configuration sub-nodes:
[all …]
H A Dpinctrl-st.txt1 *ST pin controller.
3 Each multi-function pin is controlled, driven and routed through the
4 PIO multiplexing block. Each pin supports GPIO functionality (ALT0)
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
6 the pin to different hardware blocks.
8 When a pin is in GPIO mode, Output Enable (OE), Open Drain(OD), and
12 gpio driver to configure a pin.
14 GPIO bank can have one of the two possible types of interrupt-wirings.
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
[all …]
/linux/drivers/pinctrl/renesas/
H A Dpinctrl-rzn1.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014-2018 Renesas Electronics Europe Limited
9 #include <dt-bindings/pinctrl/rzn1-pinctrl.h>
19 #include <linux/pinctrl/pinconf-generic.h>
26 #include "../pinctrl-utils.h"
44 * logical to think of the hardware as three levels, with level 3 consisting of
47 * Level 1 functions go from 0 to 9, with level 1 function '15' (0xf) specifying
48 * that level 2 functions are used instead. Level 2 has a lot more options,
49 * going from 0 to 61. Level 3 allows selection of MDIO functions which can be
51 * level 2 functions that can select MDIO, and two MDIO channels so we have four
[all …]
/linux/include/linux/
H A Dmdio-bitbang.h1 /* SPDX-License-Identifier: GPL-2.0 */
14 /* Set the Management Data Clock high if level is one,
15 * low if level is zero.
17 void (*set_mdc)(struct mdiobb_ctrl *ctrl, int level);
19 /* Configure the Management Data I/O pin as an input if
24 /* Set the Management Data I/O pin high if value is one,
26 * when the MDIO pin is configured as an output.
30 /* Retrieve the state Management Data I/O pin. */
/linux/arch/riscv/kvm/
H A Dvm.c1 // SPDX-License-Identifier: GPL-2.0
63 return -ENXIO; in kvm_vm_ioctl_irq_line()
65 return kvm_riscv_aia_inject_irq(kvm, irql->irq, irql->level); in kvm_vm_ioctl_irq_line()
70 int level, bool line_status) in kvm_set_msi() argument
74 if (!level) in kvm_set_msi()
75 return -1; in kvm_set_msi()
77 msi.address_lo = e->msi.address_lo; in kvm_set_msi()
78 msi.address_hi = e->msi.address_hi; in kvm_set_msi()
79 msi.data = e->msi.data; in kvm_set_msi()
80 msi.flags = e->msi.flags; in kvm_set_msi()
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/linux/Documentation/driver-api/gpio/
H A Dintro.rst17 A "General Purpose Input/Output" (GPIO) is a flexible software-controlled
20 represents a bit connected to a particular pin, or "ball" on Ball Grid Array
23 passes such pin configuration data to drivers.
25 System-on-Chip (SOC) processors heavily rely on GPIOs. In some cases, every
26 non-dedicated pin can be configured as a GPIO; and most chips have at least
29 often have a few such pins to help with pin scarcity on SOCs; and there are
31 Most PC southbridges have a few dozen GPIO-capable pins (with only the BIOS
36 - Output values are writable (high=1, low=0). Some chips also have
38 value might be driven, supporting "wire-OR" and similar schemes for the
41 - Input values are likewise readable (1, 0). Some chips support readback
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/linux/arch/powerpc/platforms/52xx/
H A Dmpc52xx_pm.c1 // SPDX-License-Identifier: GPL-2.0
39 int mpc52xx_set_wakeup_gpio(u8 pin, u8 level) in mpc52xx_set_wakeup_gpio() argument
44 out_8(&gpiow->wkup_gpioe, in_8(&gpiow->wkup_gpioe) | (1 << pin)); in mpc52xx_set_wakeup_gpio()
46 out_8(&gpiow->wkup_ddr, in_8(&gpiow->wkup_ddr) & ~(1 << pin)); in mpc52xx_set_wakeup_gpio()
48 out_8(&gpiow->wkup_inten, in_8(&gpiow->wkup_inten) | (1 << pin)); in mpc52xx_set_wakeup_gpio()
49 /* low/high level creates wakeup interrupt */ in mpc52xx_set_wakeup_gpio()
50 tmp = in_be16(&gpiow->wkup_itype); in mpc52xx_set_wakeup_gpio()
51 tmp &= ~(0x3 << (pin * 2)); in mpc52xx_set_wakeup_gpio()
52 tmp |= (!level + 1) << (pin * 2); in mpc52xx_set_wakeup_gpio()
53 out_be16(&gpiow->wkup_itype, tmp); in mpc52xx_set_wakeup_gpio()
[all …]
/linux/Documentation/driver-api/media/
H A Dcec-core.rst1 .. SPDX-License-Identifier: GPL-2.0
15 ----------------
33 ---------------------
53 will be stored in adap->priv and can be used by the adapter ops.
95 Implementing the Low-Level CEC Adapter
96 --------------------------------------
98 The following low-level adapter operations have to be implemented in
103 .. code-block:: none
107 /* Low-level callbacks */
123 /* High-level callback */
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/linux/drivers/gpu/drm/loongson/
H A Dlsdc_i2c.c1 // SPDX-License-Identifier: GPL-2.0+
13 * __lsdc_gpio_i2c_set - set the state of a gpio pin indicated by mask
14 * @mask: gpio pin mask
19 struct lsdc_device *ldev = to_lsdc(li2c->ddev); in __lsdc_gpio_i2c_set()
23 spin_lock_irqsave(&ldev->reglock, flags); in __lsdc_gpio_i2c_set()
27 * Setting this pin as input directly, write 1 for input. in __lsdc_gpio_i2c_set()
28 * The external pull-up resistor will pull the level up in __lsdc_gpio_i2c_set()
30 val = readb(li2c->dir_reg); in __lsdc_gpio_i2c_set()
32 writeb(val, li2c->dir_reg); in __lsdc_gpio_i2c_set()
34 /* First set this pin as output, write 0 for output */ in __lsdc_gpio_i2c_set()
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Dcirrus,cs35l45.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ricardo Rivera-Matos <rriveram@opensource.cirrus.com>
11 - Richard Fitzgerald <rf@opensource.cirrus.com>
18 - $ref: dai-common.yaml#
23 - cirrus,cs35l45
31 '#sound-dai-cells':
34 reset-gpios:
37 vdd-a-supply:
[all …]
H A Dcs35l32.txt5 - compatible : "cirrus,cs35l32"
7 - reg : the I2C address of the device for I2C. Address is determined by the level
8 of the AD0 pin. Level 0 is 0x40 while Level 1 is 0x41.
10 - VA-supply, VP-supply : power supplies for the device,
15 - reset-gpios : a GPIO spec for the reset pin. If specified, it will be
18 - cirrus,boost-manager : Boost voltage control.
19 0 = Automatically managed. Boost-converter output voltage is the higher
21 1 = Automatically managed irrespective of audio, adapting for low-power
22 dissipation when LEDs are ON, and operating in Fixed-Boost Bypass Mode
27 - cirrus,sdout-datacfg : Data configuration for dual CS35L32 applications only.
[all …]
/linux/sound/soc/
H A Dsoc-dapm.c1 // SPDX-License-Identifier: GPL-2.0+
3 // soc-dapm.c -- ALSA SoC Dynamic Audio Power Management
12 // o Platform power domain - can support external components i.e. amps and
15 // o Jack insertion power event initiation - e.g. hp insertion will enable
66 #define DAPM_UPDATE_STAT(widget, val) widget->dapm->car
1051 snd_soc_dapm_force_bias_level(struct snd_soc_dapm_context * dapm,enum snd_soc_bias_level level) snd_soc_dapm_force_bias_level() argument
1078 snd_soc_dapm_init_bias_level(struct snd_soc_dapm_context * dapm,enum snd_soc_bias_level level) snd_soc_dapm_init_bias_level() argument
1094 snd_soc_dapm_set_bias_level(struct snd_soc_dapm_context * dapm,enum snd_soc_bias_level level) snd_soc_dapm_set_bias_level() argument
1408 int level = snd_power_get_state(widget->dapm->card->snd_card); dapm_suspend_check() local
2524 char *level; dapm_bias_read_file() local
2895 dapm_find_widget(struct snd_soc_dapm_context * dapm,const char * pin,bool search_other_contexts) dapm_find_widget() argument
2933 __dapm_set_pin(struct snd_soc_dapm_context * dapm,const char * pin,int status) __dapm_set_pin() argument
2965 dapm_set_pin(struct snd_soc_dapm_context * dapm,const char * pin,int status) dapm_set_pin() argument
3651 __snd_soc_dapm_get_pin_switch(struct snd_soc_dapm_context * dapm,const char * pin,struct snd_ctl_elem_value * ucontrol) __snd_soc_dapm_get_pin_switch() argument
3675 const char *pin = (const char *)kcontrol->private_value; snd_soc_dapm_get_pin_switch() local
3695 const char *pin = (const char *)kcontrol->private_value; snd_soc_dapm_get_component_pin_switch() local
3702 __dapm_put_pin_switch(struct snd_soc_dapm_context * dapm,const char * pin,struct snd_ctl_elem_value * ucontrol) __dapm_put_pin_switch() argument
3730 const char *pin = (const char *)kcontrol->private_value; snd_soc_dapm_put_pin_switch() local
3750 const char *pin = (const char *)kcontrol->private_value; snd_soc_dapm_put_component_pin_switch() local
4667 snd_soc_dapm_enable_pin_unlocked(struct snd_soc_dapm_context * dapm,const char * pin) snd_soc_dapm_enable_pin_unlocked() argument
4684 snd_soc_dapm_enable_pin(struct snd_soc_dapm_context * dapm,const char * pin) snd_soc_dapm_enable_pin() argument
4713 snd_soc_dapm_force_enable_pin_unlocked(struct snd_soc_dapm_context * dapm,const char * pin) snd_soc_dapm_force_enable_pin_unlocked() argument
4757 snd_soc_dapm_force_enable_pin(struct snd_soc_dapm_context * dapm,const char * pin) snd_soc_dapm_force_enable_pin() argument
4784 snd_soc_dapm_disable_pin_unlocked(struct snd_soc_dapm_context * dapm,const char * pin) snd_soc_dapm_disable_pin_unlocked() argument
4801 snd_soc_dapm_disable_pin(struct snd_soc_dapm_context * dapm,const char * pin) snd_soc_dapm_disable_pin() argument
4825 snd_soc_dapm_get_pin_status(struct snd_soc_dapm_context * dapm,const char * pin) snd_soc_dapm_get_pin_status() argument
4848 snd_soc_dapm_ignore_suspend(struct snd_soc_dapm_context * dapm,const char * pin) snd_soc_dapm_ignore_suspend() argument
[all...]
/linux/Documentation/devicetree/bindings/net/bluetooth/
H A Dmediatek,bluetooth.txt13 - compatible: Must be
14 "mediatek,mt7663u-bluetooth": for MT7663U device
15 "mediatek,mt7668u-bluetooth": for MT7668U device
16 - vcc-supply: Main voltage regulator
18 If the pin controller on the platform can support both pinmux and GPIO
21 - pinctrl-names: Should be "default", "runtime"
22 - pinctrl-0: Should contain UART RXD low when the device is powered up to
24 - pinctrl-1: Should contain UART mode pin ctrl
26 Else, the pin controller on the platform only can support pinmux control and
30 - boot-gpios: GPIO same to the pin as UART RXD and used to keep LOW when
[all …]
/linux/drivers/gpio/
H A Dgpio-imx-scu.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * to control the PIN resources on SCU domain.
16 #include <dt-bindings/firmware/imx/rsrc.h>
39 int level; in imx_scu_gpio_get() local
42 scoped_guard(mutex, &priv->lock) { in imx_scu_gpio_get()
43 /* to read PIN state via scu api */ in imx_scu_gpio_get()
44 err = imx_sc_misc_get_control(priv->handle, in imx_scu_gpio_get()
45 scu_rsrc_arr[offset], 0, &level); in imx_scu_gpio_get()
48 dev_err(priv->dev, "SCU get failed: %d\n", err); in imx_scu_gpio_get()
52 return level; in imx_scu_gpio_get()
[all …]
H A Dgpio-tangier.c1 // SPDX-License-Identifier: GPL-2.0-only
22 #include <linux/pinctrl/pinconf-generic.h>
30 #include "gpio-tangier.h"
33 #define GPLR 0x004 /* Pin level r/o */
34 #define GPDR 0x01c /* Pin direction */
35 #define GPSR 0x034 /* Pin set w/o */
36 #define GPCR 0x04c /* Pin clear w/o */
43 #define GLPR 0x318 /* Level input polarity */
46 * struct tng_gpio_context - Context to be saved during suspend-resume
47 * @level: Pin level
[all …]
/linux/arch/arm/plat-orion/
H A Dgpio.c2 * arch/arm/plat-orion/gpio.c
27 #include <plat/orion-gpio.h>
54 return ochip->base + GPIO_OUT_OFF; in GPIO_OUT()
59 return ochip->base + GPIO_IO_CONF_OFF; in GPIO_IO_CONF()
64 return ochip->base + GPIO_BLINK_EN_OFF; in GPIO_BLINK_EN()
69 return ochip->base + GPIO_IN_POL_OFF; in GPIO_IN_POL()
74 return ochip->base + GPIO_DATA_IN_OFF; in GPIO_DATA_IN()
79 return ochip->base + GPIO_EDGE_CAUSE_OFF; in GPIO_EDGE_CAUSE()
84 return ochip->base + ochip->mask_offset + GPIO_EDGE_MASK_OFF; in GPIO_EDGE_MASK()
89 return ochip->base + ochip->mask_offset + GPIO_LEVEL_MASK_OFF; in GPIO_LEVEL_MASK()
[all …]
/linux/drivers/pinctrl/intel/
H A DKconfig.tng1 # SPDX-License-Identifier: GPL-2.0-only
2 # Intel Tangier and compatible pin control drivers
12 This is a library driver for Intel Tangier pin controller and to
15 If built as a module its name will be pinctrl-tangier.
21 Intel Merrifield Family-Level Interface Shim (FLIS) driver provides
29 Intel Moorefield Family-Level Interface Shim (FLIS) driver provides
/linux/Documentation/devicetree/bindings/regulator/
H A Drichtek,rtmv20-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/richtek,rtmv20-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiYuan Huang <cy_huang@richtek.com>
15 (Enable/Fail), Enable pin to turn chip on, and Fail pin as fault indication.
27 wakeup-source: true
32 enable-gpios:
36 richtek,ld-pulse-delay-us:
38 load current pulse delay in microsecond after strobe pin pulse high.
[all …]
/linux/drivers/pinctrl/uniphier/
H A Dpinctrl-uniphier.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2015-2017 Socionext Inc.
21 - 1)
28 - 1)
35 - 1)
37 /* pull-up / pull-down register number */
42 - 1)
49 - 1)
52 #error "unable to pack pin attributes."
60 UNIPHIER_PIN_DRV_1BIT, /* 2 level control: 4/8 mA */
[all …]
/linux/include/dt-bindings/sound/
H A Dcs35l45.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * cs35l45.h -- CS35L45 ALSA SoC audio driver DT bindings header
12 * cirrus,asp-sdout-hiz-ctrl
14 * TX_HIZ_UNUSED: TX pin high-impedance during unused slots.
15 * TX_HIZ_DISABLED: TX pin high-impedance when all channels disabled.
21 * Optional GPIOX Sub-nodes:
22 * The cs35l45 node can have up to three "cirrus,gpio-ctrlX" ('X' = [1,2,3])
23 * sub-nodes for configuring the GPIO pins.
25 * - gpio-dir : GPIO pin direction. Valid only when 'gpio-ctrl'
30 * - gpio-lvl : GPIO level. Valid only when 'gpio-ctrl' is 1 and 'gpio-dir' is 0.
[all …]
/linux/Documentation/devicetree/bindings/iio/light/
H A Dvishay,vcnl4000.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Meerwald <pmeerw@pmeerw.net>
17 - $ref: ../common.yaml#
22 - enum:
23 - capella,cm36672p
24 - vishay,vcnl4000
25 - vishay,vcnl4010
26 - vishay,vcnl4020
[all …]
/linux/Documentation/devicetree/bindings/hwmon/pmbus/
H A Dinfineon,tda38640.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Naresh Solanki <naresh.solanki@9elements.com>
14 The Infineon TDA38640 is a 40A Single-voltage Synchronous Buck
17 …Datasheet: https://www.infineon.com/dgdl/Infineon-TDA38640-0000-DataSheet-v02_04-EN.pdf?fileId=8ac…
22 - infineon,tda38640
27 infineon,en-pin-fixed-level:
29 Indicates that the chip EN pin is at fixed level or left
30 unconnected(has internal pull-down).
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