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/linux/drivers/net/ethernet/mediatek/
H A Dmtk_ppe.c29 static void ppe_w32(struct mtk_ppe *ppe, u32 reg, u32 val) in ppe_w32() argument
31 writel(val, ppe->base + reg); in ppe_w32()
34 static u32 ppe_r32(struct mtk_ppe *ppe, u32 reg) in ppe_r32() argument
36 return readl(ppe->base + reg); in ppe_r32()
39 static u32 ppe_m32(struct mtk_ppe *ppe, u32 reg, u32 mask, u32 set) in ppe_m32() argument
43 val = ppe_r32(ppe, reg); in ppe_m32()
46 ppe_w32(ppe, reg, val); in ppe_m32()
51 static u32 ppe_set(struct mtk_ppe *ppe, u32 reg, u32 val) in ppe_set() argument
53 return ppe_m32(ppe, reg, 0, val); in ppe_set()
56 static u32 ppe_clear(struct mtk_ppe *ppe, u32 reg, u32 val) in ppe_clear() argument
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H A Dmtk_ppe.h349 void mtk_ppe_start(struct mtk_ppe *ppe);
350 int mtk_ppe_stop(struct mtk_ppe *ppe);
351 int mtk_ppe_prepare_reset(struct mtk_ppe *ppe);
353 void __mtk_ppe_check_skb(struct mtk_ppe *ppe, struct sk_buff *skb, u16 hash);
356 mtk_ppe_check_skb(struct mtk_ppe *ppe, struct sk_buff *skb, u16 hash) in mtk_ppe_check_skb() argument
360 if (!ppe) in mtk_ppe_check_skb()
367 diff = now - ppe->foe_check_time[hash]; in mtk_ppe_check_skb()
371 ppe->foe_check_time[hash] = now; in mtk_ppe_check_skb()
372 __mtk_ppe_check_skb(ppe, skb, hash); in mtk_ppe_check_skb()
399 int mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_flow_entry *entry);
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H A Dmtk_ppe_debugfs.c79 struct mtk_ppe *ppe = m->private; in mtk_ppe_debugfs_foe_show() local
83 struct mtk_foe_entry *entry = mtk_foe_get_entry(ppe, i); in mtk_ppe_debugfs_foe_show()
100 acct = mtk_foe_entry_get_mib(ppe, i, NULL); in mtk_ppe_debugfs_foe_show()
102 type = mtk_get_ib1_pkt_type(ppe->eth, entry->ib1); in mtk_ppe_debugfs_foe_show()
184 int mtk_ppe_debugfs_init(struct mtk_ppe *ppe, int index) in mtk_ppe_debugfs_init() argument
188 snprintf(ppe->dirname, sizeof(ppe->dirname), "ppe%d", index); in mtk_ppe_debugfs_init()
190 root = debugfs_create_dir(ppe->dirname, NULL); in mtk_ppe_debugfs_init()
191 debugfs_create_file("entries", S_IRUGO, root, ppe, &mtk_ppe_debugfs_foe_all_fops); in mtk_ppe_debugfs_init()
192 debugfs_create_file("bind", S_IRUGO, root, ppe, &mtk_ppe_debugfs_foe_bind_fops); in mtk_ppe_debugfs_init()
H A Dmtk_ppe_offload.c479 err = mtk_foe_entry_commit(eth->ppe[entry->ppe_index], entry); in mtk_flow_offload_replace()
491 mtk_foe_entry_clear(eth->ppe[entry->ppe_index], entry); in mtk_flow_offload_replace()
509 mtk_foe_entry_clear(eth->ppe[entry->ppe_index], entry); in mtk_flow_offload_destroy()
531 idle = mtk_foe_entry_idle_time(eth->ppe[entry->ppe_index], entry); in mtk_flow_offload_stats()
535 mtk_foe_entry_get_mib(eth->ppe[entry->ppe_index], entry->hash, in mtk_flow_offload_stats()
653 if (!eth->ppe[id] || !eth->ppe[id]->foe_table) in mtk_eth_offload_init()
/linux/drivers/net/ethernet/airoha/
H A Dairoha_ppe.c39 static u32 airoha_ppe_get_timestamp(struct airoha_ppe *ppe) in airoha_ppe_get_timestamp() argument
41 u16 timestamp = airoha_fe_rr(ppe->eth, REG_FE_FOE_TS); in airoha_ppe_get_timestamp()
46 static void airoha_ppe_hw_init(struct airoha_ppe *ppe) in airoha_ppe_hw_init() argument
49 struct airoha_eth *eth = ppe->eth; in airoha_ppe_hw_init()
59 ppe->foe_dma + sram_tb_size); in airoha_ppe_hw_init()
440 static u32 airoha_ppe_foe_get_flow_stats_index(struct airoha_ppe *ppe, u32 hash) in airoha_ppe_foe_get_flow_stats_index() argument
442 if (!airoha_ppe2_is_enabled(ppe->eth)) in airoha_ppe_foe_get_flow_stats_index()
449 static void airoha_ppe_foe_flow_stat_entry_reset(struct airoha_ppe *ppe, in airoha_ppe_foe_flow_stat_entry_reset() argument
454 memset(&ppe->foe_stats[index], 0, sizeof(*ppe->foe_stats)); in airoha_ppe_foe_flow_stat_entry_reset()
457 static void airoha_ppe_foe_flow_stats_reset(struct airoha_ppe *ppe, in airoha_ppe_foe_flow_stats_reset() argument
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H A Dairoha_eth.h466 struct hlist_node list; /* PPE L3 flow entry */
469 struct hlist_head l2_flows; /* PPE L2 subflows list */
474 struct hlist_node l2_subflow_node; /* PPE L2 subflow entry */
562 struct airoha_ppe *ppe; member
612 void airoha_ppe_check_skb(struct airoha_ppe *ppe, struct sk_buff *skb,
618 struct airoha_foe_entry *airoha_ppe_foe_get_entry(struct airoha_ppe *ppe,
620 void airoha_ppe_foe_entry_get_stats(struct airoha_ppe *ppe, u32 hash,
624 int airoha_ppe_debugfs_init(struct airoha_ppe *ppe);
626 static inline int airoha_ppe_debugfs_init(struct airoha_ppe *ppe) in airoha_ppe_debugfs_init() argument
/linux/Documentation/devicetree/bindings/net/
H A Dhisilicon-hip04-net.txt10 phandle, specifies a reference to the syscon ppe node
50 ppe: ppe@28c0000 {
51 compatible = "hisilicon,hip04-ppe", "syscon";
60 port-handle = <&ppe 31 0 31>;
68 port-handle = <&ppe 0 1 0>;
77 port-handle = <&ppe 8 2 8>;
H A Dhisilicon-hns-dsaf.txt20 The third region is the PPE register base and size.
23 - reg-names: may be ppe-base and(or) dsaf-base. It is used to find the
64 reg-names = "ppe-base", "dsaf-base";
H A Dairoha,en7581-npu.yaml15 Processor Engine (PPE) flow table.
/linux/block/partitions/
H A Daix.c50 struct ppe { struct
64 struct ppe ppe[1016]; argument
232 struct ppe *p = pvd->ppe + i; in aix_partition()
/linux/drivers/ata/
H A Dpata_sch.c34 PPE = (1 << 30), /* Prefetch/Post Enable */ enumerator
106 data &= ~(PM | PPE); in sch_set_piomode()
108 /* enable PPE for block device */ in sch_set_piomode()
110 data |= PPE; in sch_set_piomode()
H A Dpata_oldpiix.c92 control |= 4; /* PPE */ in oldpiix_set_piomode()
97 * Set PPE, IE and TIME as appropriate. in oldpiix_set_piomode()
141 * IORDY unconditionally along with TIME1. PPE has already in oldpiix_set_dmamode()
155 /* Intel specifies that the PPE functionality is for disk only */ in oldpiix_set_dmamode()
157 control |= 4; /* PPE enable */ in oldpiix_set_dmamode()
H A Dpata_mpiix.c43 PPE = (1 << 2), enumerator
91 /* Mask the IORDY/TIME/PPE for this device */ in mpiix_set_piomode()
93 control |= PPE; /* Enable prefetch/posting for disk */ in mpiix_set_piomode()
H A Dpata_efar.c112 control |= 4; /* PPE */ in efar_set_piomode()
118 /* Set PPE, IE, and TIME as appropriate */ in efar_set_piomode()
194 * IORDY unconditionally along with TIME1. PPE has already in efar_set_dmamode()
H A Dpata_it8213.c101 control |= 4; /* PPE */ in it8213_set_piomode()
105 /* Set PPE, IE, and TIME as appropriate */ in it8213_set_piomode()
189 * IORDY unconditionally along with TIME1. PPE has already in it8213_set_dmamode()
H A Dpata_rdc.c114 control |= 4; /* PPE enable */ in rdc_set_piomode()
138 /* Enable PPE, IE and TIME as appropriate */ in rdc_set_piomode()
229 * IORDY unconditionally along with TIME1. PPE has already in rdc_set_dmamode()
/linux/drivers/media/platform/nvidia/tegra-vde/
H A Dvde.h98 void __iomem *ppe; member
217 if (vde->ppe == base) in tegra_vde_reg_base_name()
218 return "PPE"; in tegra_vde_reg_base_name()
/linux/Documentation/devicetree/bindings/media/
H A Dnvidia,tegra-vde.yaml36 - const: ppe
106 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
/linux/drivers/net/wireless/ath/ath12k/
H A Drx_desc.h269 * as PPE may not support such packets.
275 * Global enable/disable bit for routing to PPE, used to disable
276 * PPE routing even if RXOLE CCE or flow search indicate 'Use_PPE'
279 * buffer management for WiFi-to-PPE routing.
282 * by a different subsystem, completely disabling WiFi-to-PPE
605 * Opaque service code between PPE and Wi-Fi
606 * This field gets passed on by REO to PPE in the EDMA descriptor
610 * This field gets passed on by REO to PPE in the EDMA descriptor
616 * This field gets passed on by REO to PPE in the EDMA descriptor
1122 * Opaque service code between PPE and Wi-Fi
[all …]
/linux/arch/powerpc/platforms/cell/spufs/
H A Dspu_restore.c182 * here by the PPE Sequence for SPU Context in restore_complete()
285 * 1. The EA for LSCSA is passed from PPE in the
288 * into LS, rather than pushed by PPE.
/linux/arch/mips/lantiq/
H A Dclk.c30 unsigned long io, unsigned long ppe) in clkdev_add_static() argument
35 cpu_clk_generic[3].rate = ppe; in clkdev_add_static()
H A Dclk.h73 unsigned long io, unsigned long ppe);
/linux/drivers/net/wireless/intel/iwlwifi/mvm/
H A Dmac80211.c2217 static u8 iwl_mvm_he_get_ppe_val(u8 *ppe, u8 ppe_pos_bit) in iwl_mvm_he_get_ppe_val() argument
2225 return (ppe[byte_num] >> bit_num) & in iwl_mvm_he_get_ppe_val()
2236 res = (ppe[byte_num + 1] & in iwl_mvm_he_get_ppe_val()
2239 res += (ppe[byte_num] >> bit_num) & (BIT(residue_bits) - 1); in iwl_mvm_he_get_ppe_val()
2246 u8 ru_index_bitmap, u8 *ppe, u8 ppe_pos_bit, in iwl_mvm_parse_ppe() argument
2274 * According to the 11be spec, if for a specific BW the PPE Thresholds in iwl_mvm_parse_ppe()
2276 * BW for which we had PPE Thresholds. In 11ax though, we don't have in iwl_mvm_parse_ppe()
2286 high_th = iwl_mvm_he_get_ppe_val(ppe, ppe_pos_bit); in iwl_mvm_parse_ppe()
2288 low_th = iwl_mvm_he_get_ppe_val(ppe, ppe_pos_bit); in iwl_mvm_parse_ppe()
2305 u8 *ppe = &link_sta->he_cap.ppe_thres[0]; in iwl_mvm_set_pkt_ext_from_he_ppe() local
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/linux/net/mac80211/tests/
H A Dutil.c102 * unset, as DCM, beam forming, RU and PPE
188 /* PPE threshold information is not supported */
/linux/Documentation/devicetree/bindings/mfd/
H A Dsyscon.yaml72 - hisilicon,hip04-ppe
178 - hisilicon,hip04-ppe

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