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/linux/drivers/net/pcs/
H A Dpcs-lynx.c3 * Lynx PCS MDIO helpers
8 #include <linux/pcs-lynx.h>
11 #define SGMII_CLOCK_PERIOD_NS 8 /* PCS is clocked at 125 MHz */
24 struct phylink_pcs pcs; member
35 #define phylink_pcs_to_lynx(pl_pcs) container_of((pl_pcs), struct lynx_pcs, pcs)
36 #define lynx_to_phylink_pcs(lynx) (&(lynx)->pcs)
38 static unsigned int lynx_pcs_inband_caps(struct phylink_pcs *pcs, in lynx_pcs_inband_caps() argument
60 static void lynx_pcs_get_state_usxgmii(struct mdio_device *pcs, in lynx_pcs_get_state_usxgmii() argument
63 struct mii_bus *bus = pcs->bus; in lynx_pcs_get_state_usxgmii()
64 int addr = pcs->addr; in lynx_pcs_get_state_usxgmii()
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H A Dpcs-mtk-lynxi.c13 #include <linux/pcs/pcs-mtk-lynxi.h>
74 * @dev: Pointer to device owning the PCS
77 * @pcs: Phylink PCS structure
84 struct phylink_pcs pcs; member
89 static struct mtk_pcs_lynxi *pcs_to_mtk_pcs_lynxi(struct phylink_pcs *pcs) in pcs_to_mtk_pcs_lynxi() argument
91 return container_of(pcs, struct mtk_pcs_lynxi, pcs); in pcs_to_mtk_pcs_lynxi()
94 static unsigned int mtk_pcs_lynxi_inband_caps(struct phylink_pcs *pcs, in mtk_pcs_lynxi_inband_caps() argument
108 static void mtk_pcs_lynxi_get_state(struct phylink_pcs *pcs, in mtk_pcs_lynxi_get_state() argument
112 struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs); in mtk_pcs_lynxi_get_state()
138 pcs_fwnode = fwnode_get_named_child_node(fwnode, "pcs"); in mtk_pcs_config_polarity()
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H A DMakefile2 # Makefile for Linux PCS drivers
4 pcs_xpcs-$(CONFIG_PCS_XPCS) := pcs-xpcs.o pcs-xpcs-plat.o \
5 pcs-xpcs-nxp.o pcs-xpcs-wx.o
8 obj-$(CONFIG_PCS_LYNX) += pcs-lynx.o
9 obj-$(CONFIG_PCS_MTK_LYNXI) += pcs-mtk-lynxi.o
10 obj-$(CONFIG_PCS_RZN1_MIIC) += pcs-rzn1-miic.o
H A Dpcs-xpcs.c11 #include <linux/pcs/pcs-xpcs.h>
17 #include "pcs-xpcs.h"
20 container_of((pl_pcs), struct dw_xpcs, pcs)
181 return &xpcs->pcs; in xpcs_to_phylink_pcs()
604 * PCS link will bounce. To avoid reporting link up too soon we include in xpcs_resolve_pma()
645 static int xpcs_validate(struct phylink_pcs *pcs, unsigned long *supported, in xpcs_validate() argument
653 xpcs = phylink_pcs_to_xpcs(pcs); in xpcs_validate()
670 static unsigned int xpcs_inband_caps(struct phylink_pcs *pcs, in xpcs_inband_caps() argument
673 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); in xpcs_inband_caps()
721 static void xpcs_pre_config(struct phylink_pcs *pcs, phy_interface_t interface) in xpcs_pre_config() argument
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H A Dpcs-rzn1-miic.c17 #include <linux/pcs-rzn1-miic.h>
23 #include <dt-bindings/net/pcs-rzn1-miic.h>
24 #include <dt-bindings/net/renesas,r9a09g077-pcs-miic.h>
255 * @pcs: PCS structure associated to the port
261 struct phylink_pcs pcs; member
266 static struct miic_port *phylink_pcs_to_miic_port(struct phylink_pcs *pcs) in phylink_pcs_to_miic_port() argument
268 return container_of(pcs, struct miic_port, pcs); in phylink_pcs_to_miic_port()
332 static int miic_config(struct phylink_pcs *pcs, unsigned int neg_mode, in miic_config() argument
336 struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs); in miic_config()
383 static void miic_link_up(struct phylink_pcs *pcs, unsigned int neg_mode, in miic_link_up() argument
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/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1046-post.dtsi27 pcs-handle = <&qsgmiib_pcs3>;
28 pcs-handle-names = "qsgmii";
42 pcs-handle = <&pcsphy4>, <&qsgmiib_pcs1>;
43 pcs-handle-names = "sgmii", "qsgmii";
48 pcs-handle = <&pcsphy5>, <&pcsphy5>;
49 pcs-handle-names = "sgmii", "qsgmii";
57 pcs-handle = <&pcsphy7>, <&qsgmiib_pcs2>, <&pcsphy7>;
58 pcs-handle-names = "sgmii", "qsgmii", "xfi";
62 qsgmiib_pcs1: ethernet-pcs@1 {
63 compatible = "fsl,lynx-pcs";
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H A Dfsl-ls1043-post.dtsi27 pcs-handle-names = "qsgmii";
32 pcs-handle = <&pcsphy1>, <&qsgmiib_pcs1>;
33 pcs-handle-names = "sgmii", "qsgmii";
44 pcs-handle = <&pcsphy4>, <&qsgmiib_pcs2>;
45 pcs-handle-names = "sgmii", "qsgmii";
50 pcs-handle = <&pcsphy5>, <&qsgmiib_pcs3>;
51 pcs-handle-names = "sgmii", "qsgmii";
58 qsgmiib_pcs1: ethernet-pcs@1 {
59 compatible = "fsl,lynx-pcs";
63 qsgmiib_pcs2: ethernet-pcs@2 {
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H A Dtqmls1088a-mbls10xxa-mc.dtsi17 pcs-handle = <&pcs1>;
21 pcs-handle = <&pcs2>;
25 pcs-handle = <&pcs3_0>;
29 pcs-handle = <&pcs3_1>;
33 pcs-handle = <&pcs3_2>;
37 pcs-handle = <&pcs3_3>;
41 pcs-handle = <&pcs7_0>;
45 pcs-handle = <&pcs7_1>;
49 pcs-handle = <&pcs7_2>;
53 pcs-handle = <&pcs7_3>;
H A Dfsl-ls1088a-rdb.dts23 pcs-handle = <&pcs2>;
30 pcs-handle = <&pcs3_0>;
37 pcs-handle = <&pcs3_1>;
44 pcs-handle = <&pcs3_2>;
51 pcs-handle = <&pcs3_3>;
58 pcs-handle = <&pcs7_0>;
65 pcs-handle = <&pcs7_1>;
72 pcs-handle = <&pcs7_2>;
79 pcs-handle = <&pcs7_3>;
/linux/drivers/net/dsa/b53/
H A Db53_serdes.c20 static inline struct b53_pcs *pcs_to_b53_pcs(struct phylink_pcs *pcs) in pcs_to_b53_pcs() argument
22 return container_of(pcs, struct b53_pcs, pcs); in pcs_to_b53_pcs()
68 static int b53_serdes_config(struct phylink_pcs *pcs, unsigned int neg_mode, in b53_serdes_config() argument
73 struct b53_device *dev = pcs_to_b53_pcs(pcs)->dev; in b53_serdes_config()
74 u8 lane = pcs_to_b53_pcs(pcs)->lane; in b53_serdes_config()
89 static void b53_serdes_an_restart(struct phylink_pcs *pcs) in b53_serdes_an_restart() argument
91 struct b53_device *dev = pcs_to_b53_pcs(pcs)->dev; in b53_serdes_an_restart()
92 u8 lane = pcs_to_b53_pcs(pcs)->lane; in b53_serdes_an_restart()
102 static void b53_serdes_get_state(struct phylink_pcs *pcs, unsigned int neg_mode, in b53_serdes_get_state() argument
105 struct b53_device *dev = pcs_to_b53_pcs(pcs)->dev; in b53_serdes_get_state()
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/linux/drivers/net/dsa/mv88e6xxx/
H A Dpcs-639x.c3 * Marvell 88E6352 family SERDES PCS support
130 static struct mv88e639x_pcs *sgmii_pcs_to_mv88e639x_pcs(struct phylink_pcs *pcs) in sgmii_pcs_to_mv88e639x_pcs() argument
132 return container_of(pcs, struct mv88e639x_pcs, sgmii_pcs); in sgmii_pcs_to_mv88e639x_pcs()
184 static int mv88e639x_sgmii_pcs_enable(struct phylink_pcs *pcs) in mv88e639x_sgmii_pcs_enable() argument
186 struct mv88e639x_pcs *mpcs = sgmii_pcs_to_mv88e639x_pcs(pcs); in mv88e639x_sgmii_pcs_enable()
194 static void mv88e639x_sgmii_pcs_disable(struct phylink_pcs *pcs) in mv88e639x_sgmii_pcs_disable() argument
196 struct mv88e639x_pcs *mpcs = sgmii_pcs_to_mv88e639x_pcs(pcs); in mv88e639x_sgmii_pcs_disable()
202 static void mv88e639x_sgmii_pcs_pre_config(struct phylink_pcs *pcs, in mv88e639x_sgmii_pcs_pre_config() argument
205 struct mv88e639x_pcs *mpcs = sgmii_pcs_to_mv88e639x_pcs(pcs); in mv88e639x_sgmii_pcs_pre_config()
241 static int mv88e639x_sgmii_pcs_post_config(struct phylink_pcs *pcs, in mv88e639x_sgmii_pcs_post_config() argument
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H A Dpcs-6185.c3 * Marvell 88E6185 family SERDES PCS support
24 static struct mv88e6185_pcs *pcs_to_mv88e6185_pcs(struct phylink_pcs *pcs) in pcs_to_mv88e6185_pcs() argument
26 return container_of(pcs, struct mv88e6185_pcs, phylink_pcs); in pcs_to_mv88e6185_pcs()
57 static void mv88e6185_pcs_get_state(struct phylink_pcs *pcs, in mv88e6185_pcs_get_state() argument
61 struct mv88e6185_pcs *mpcs = pcs_to_mv88e6185_pcs(pcs); in mv88e6185_pcs_get_state()
99 static int mv88e6185_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, in mv88e6185_pcs_config() argument
107 static void mv88e6185_pcs_an_restart(struct phylink_pcs *pcs) in mv88e6185_pcs_an_restart() argument
126 * have a PCS or not. in mv88e6185_pcs_init()
/linux/Documentation/networking/
H A Dsfp-phylink.rst219 should be used to configure the MAC when the MAC and PCS are not
249 10. Some Ethernet controllers work in pair with a PCS (Physical Coding Sublayer)
252 PCS whose operation is transparent, some other require dedicated PCS
254 provides a PCS abstraction through :c:type:`struct phylink_pcs <phylink_pcs>`.
256 Identify if your driver has one or more internal PCS blocks, and/or if
257 your controller can use an external PCS block that might be internally
260 If your controller doesn't have any internal PCS, you can go to step 11.
262 If your Ethernet controller contains one or several PCS blocks, create
263 one :c:type:`struct phylink_pcs <phylink_pcs>` instance per PCS block within
268 struct phylink_pcs pcs;
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/linux/Documentation/devicetree/bindings/net/
H A Dnvidia,tegra234-mgbe.yaml49 - const: eee-pcs
50 - const: rx-pcs-input
51 - const: rx-pcs-m
52 - const: rx-pcs
53 - const: tx-pcs
61 - const: pcs
137 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
138 "rx-pcs", "tx-pcs";
141 reset-names = "mac", "pcs";
H A Dfsl,fman-mdio.yaml41 Fman has internal MDIO for internal PCS(Physical
59 set when reading internal PCS registers. MDIO reads to
60 internal PCS registers may result in having the
64 PCS registers through MDIO. As a workaround, all internal
71 - For "fsl,fman-memac-mdio" compatible internal mdio bus, the PHY is PCS PHY.
72 The PCS PHY address should correspond to the value of the appropriate
/linux/Documentation/devicetree/bindings/net/pcs/
H A Dfsl,lynx-pcs.yaml4 $id: http://devicetree.org/schemas/net/pcs/fsl,lynx-pcs.yaml#
7 title: NXP Lynx PCS
13 NXP Lynx 10G and 28G SerDes have Ethernet PCS devices which can be used as
19 const: fsl,lynx-pcs
36 qsgmii_pcs1: ethernet-pcs@1 {
37 compatible = "fsl,lynx-pcs";
H A Dsnps,dw-xpcs.yaml4 $id: http://devicetree.org/schemas/net/pcs/snps,dw-xpcs.yaml#
7 title: Synopsys DesignWare Ethernet PCS
16 controlled by means of the IEEE std. Clause 45 registers set. The PCS can be
21 The PCS CSRs can be accessible either over the Ethernet MDIO bus or directly
83 PCS/PMA layer can be clocked by an internal reference clock source
111 ethernet-pcs@1f05d000 {
128 ethernet-pcs@0 {
/linux/drivers/clocksource/
H A Dtimer-pistachio.c70 struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs); in pistachio_clocksource_read_cycles() local
80 raw_spin_lock_irqsave(&pcs->lock, flags); in pistachio_clocksource_read_cycles()
81 overflow = gpt_readl(pcs->base, TIMER_CURRENT_OVERFLOW_VALUE, 0); in pistachio_clocksource_read_cycles()
82 counter = gpt_readl(pcs->base, TIMER_CURRENT_VALUE, 0); in pistachio_clocksource_read_cycles()
83 raw_spin_unlock_irqrestore(&pcs->lock, flags); in pistachio_clocksource_read_cycles()
96 struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs); in pistachio_clksrc_set_mode() local
99 val = gpt_readl(pcs->base, TIMER_CFG, timeridx); in pistachio_clksrc_set_mode()
105 gpt_writel(pcs->base, val, TIMER_CFG, timeridx); in pistachio_clksrc_set_mode()
110 struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs); in pistachio_clksrc_enable() local
114 gpt_writel(pcs->base, RELOAD_VALUE, TIMER_RELOAD_VALUE, timeridx); in pistachio_clksrc_enable()
/linux/drivers/net/dsa/sja1105/
H A Dsja1105_mdio.c4 #include <linux/pcs/pcs-xpcs.h>
383 bus->name = "SJA1105 PCS MDIO bus"; in sja1105_mdiobus_pcs_register()
384 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-pcs", in sja1105_mdiobus_pcs_register()
403 struct phylink_pcs *pcs; in sja1105_mdiobus_pcs_register() local
412 pcs = xpcs_create_pcs_mdiodev(bus, port); in sja1105_mdiobus_pcs_register()
413 if (IS_ERR(pcs)) { in sja1105_mdiobus_pcs_register()
414 rc = PTR_ERR(pcs); in sja1105_mdiobus_pcs_register()
418 priv->pcs[port] = pcs; in sja1105_mdiobus_pcs_register()
427 if (priv->pcs[port]) { in sja1105_mdiobus_pcs_register()
428 xpcs_destroy_pcs(priv->pcs[port]); in sja1105_mdiobus_pcs_register()
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/linux/drivers/net/dsa/lantiq/
H A Dmxl-gsw1xx.c35 struct phylink_pcs pcs; member
129 static unsigned int gsw1xx_pcs_inband_caps(struct phylink_pcs *pcs, in gsw1xx_pcs_inband_caps() argument
135 static struct gsw1xx_priv *pcs_to_gsw1xx(struct phylink_pcs *pcs) in pcs_to_gsw1xx() argument
137 return container_of(pcs, struct gsw1xx_priv, pcs); in pcs_to_gsw1xx()
140 static int gsw1xx_pcs_enable(struct phylink_pcs *pcs) in gsw1xx_pcs_enable() argument
142 struct gsw1xx_priv *priv = pcs_to_gsw1xx(pcs); in gsw1xx_pcs_enable()
149 static void gsw1xx_pcs_disable(struct phylink_pcs *pcs) in gsw1xx_pcs_disable() argument
151 struct gsw1xx_priv *priv = pcs_to_gsw1xx(pcs); in gsw1xx_pcs_disable()
162 static void gsw1xx_pcs_get_state(struct phylink_pcs *pcs, in gsw1xx_pcs_get_state() argument
166 struct gsw1xx_priv *priv = pcs_to_gsw1xx(pcs); in gsw1xx_pcs_get_state()
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/linux/tools/testing/selftests/bpf/
H A Djit_disasm_helpers.c30 __u32 pcs[MAX_LOCAL_LABELS]; member
47 * - if print_phase is true and ref_value is in labels->pcs, in lookup_symbol()
50 * in labels->pcs; in lookup_symbol()
54 if (labels->pcs[i] == ref_value) in lookup_symbol()
58 labels->pcs[labels->cnt++] = ref_value; in lookup_symbol()
133 qsort(labels.pcs, labels.cnt, sizeof(*labels.pcs), cmp_u32); in disasm_one_func()
153 label_pc = bsearch(&pc, labels.pcs, labels.cnt, sizeof(*labels.pcs), cmp_u32); in disasm_one_func()
157 label = labels.names[label_pc - labels.pcs]; in disasm_one_func()
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/linux/drivers/platform/x86/siemens/
H A DKconfig24 batteries of several Industrial PCs from Siemens.
35 This option enables CMOS battery monitoring for Simatic Industrial PCs
47 This option enables CMOS battery monitoring for Simatic Industrial PCs
60 This option enables CMOS battery monitoring for Simatic Industrial PCs
/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-usb-legacy.c24 #include "phy-qcom-qmp-pcs-misc-v3.h"
25 #include "phy-qcom-qmp-pcs-usb-v4.h"
26 #include "phy-qcom-qmp-pcs-usb-v5.h"
72 /* PCS registers */
483 u16 pcs; member
493 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
518 /* Offset from PCS to PCS_USB region */
528 void __iomem *pcs; member
757 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ in qmp_usb_legacy_init_dp_com()
770 void __iomem *pcs = qmp->pcs; in qmp_usb_legacy_init() local
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/linux/arch/mips/cavium-octeon/executive/
H A Dcvmx-helper-sgmii.c65 * Write PCS*_LINK*_TIMER_COUNT_REG[COUNT] with the in __cvmx_helper_sgmii_hardware_init_one_time()
88 * 1000BASE-X mode, tx_Config_Reg<D15:D0> is PCS*_AN*_ADV_REG. in __cvmx_helper_sgmii_hardware_init_one_time()
90 * PCS*_SGM*_AN_ADV_REG. In SGMII MAC mode, in __cvmx_helper_sgmii_hardware_init_one_time()
142 * Take PCS through a reset sequence. in __cvmx_helper_sgmii_hardware_init_link()
143 * PCS*_MR*_CONTROL_REG[PWR_DN] should be cleared to zero. in __cvmx_helper_sgmii_hardware_init_link()
144 * Write PCS*_MR*_CONTROL_REG[RESET]=1 (while not changing the in __cvmx_helper_sgmii_hardware_init_link()
145 * value of the other PCS*_MR*_CONTROL_REG bits). Read in __cvmx_helper_sgmii_hardware_init_link()
146 * PCS*_MR*_CONTROL_REG[RESET] until it changes value to in __cvmx_helper_sgmii_hardware_init_link()
166 * Write PCS*_MR*_CONTROL_REG[RST_AN]=1 to ensure a fresh in __cvmx_helper_sgmii_hardware_init_link()
176 * Wait for PCS*_MR*_STATUS_REG[AN_CPT] to be set, indicating in __cvmx_helper_sgmii_hardware_init_link()
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/linux/drivers/hwmon/peci/
H A Dcputemp.c90 u32 pcs; in update_temp_target() local
96 ret = peci_pcs_read(priv->peci_dev, PECI_PCS_TEMP_TARGET, 0, &pcs); in update_temp_target()
101 FIELD_GET(TEMP_TARGET_REF_TEMP_MASK, pcs) * MILLIDEGREE_PER_DEGREE; in update_temp_target()
103 tcontrol_margin = FIELD_GET(TEMP_TARGET_FAN_TEMP_MASK, pcs); in update_temp_target()
107 tthrottle_offset = FIELD_GET(TEMP_TARGET_TJ_OFFSET_MASK, pcs) * MILLIDEGREE_PER_DEGREE; in update_temp_target()
206 u32 pcs; in get_dts() local
212 ret = peci_pcs_read(priv->peci_dev, PECI_PCS_THERMAL_MARGIN, 0, &pcs); in get_dts()
216 thermal_margin = FIELD_GET(DTS_MARGIN_MASK, pcs); in get_dts()
239 u32 pcs; in get_core_temp() local
245 ret = peci_pcs_read(priv->peci_dev, PECI_PCS_MODULE_TEMP, core_index, &pcs); in get_core_temp()
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