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/linux/Documentation/devicetree/bindings/gpu/
H A Dsamsung-scaler.yaml57 - description: mscl clock
60 - const: mscl
91 clock-names = "mscl";
/linux/Documentation/devicetree/bindings/clock/
H A Dsamsung,exynos5433-clock.yaml27 # IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS domains and bus
56 - samsung,exynos5433-cmu-mscl
366 const: samsung,exynos5433-cmu-mscl
H A Dsamsung,exynos7-clock.yaml35 - samsung,exynos7-clock-mscl
/linux/Documentation/devicetree/bindings/interconnect/
H A Dsamsung,exynos-bus.yaml137 |--- MSCL
148 |--- MSCL
/linux/include/dt-bindings/clock/
H A Dexynos7-clk.h161 /* MSCL */
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5420.dtsi120 bus_mscl: bus-mscl {
880 clock-names = "mscl";
890 clock-names = "mscl";
900 clock-names = "mscl";
/linux/drivers/devfreq/event/
H A Dexynos-ppmu.c85 PPMU_EVENT(mscl),
/linux/drivers/gpu/drm/exynos/
H A Dexynos_drm_scaler.c695 .clk_name = {"mscl"},
/linux/arch/arm64/boot/dts/exynos/
H A Dexynos5433.dtsi562 compatible = "samsung,exynos5433-cmu-mscl";
690 label = "MSCL";
/linux/drivers/clk/samsung/
H A Dclk-exynos5420.c1294 /* MSCL Block */
1311 { GATE_IP_MSCL, 0xffffffff, 0xffffffff }, /* MSCL gates */
H A Dclk-exynos7.c1226 CLK_OF_DECLARE(exynos7_clk_mscl, "samsung,exynos7-clock-mscl",
H A Dclk-exynos5433.c5542 .compatible = "samsung,exynos5433-cmu-mscl",