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Searched full:lvl1 (Results 1 – 9 of 9) sorted by relevance

/linux/Documentation/devicetree/bindings/thermal/
H A Dqcom,pm8775-mbg-tm.yaml17 for both hot and cold, LVL1 and LVL2 thresholds, which makes it different
20 it is a hot/cold and LVL1/LVL2 violation.
/linux/drivers/infiniband/hw/irdma/
H A Dpble.c414 struct irdma_pble_info *lvl1 = &palloc->level1; in get_lvl1_pble() local
416 ret_code = irdma_prm_get_pbles(&pble_rsrc->pinfo, &lvl1->chunkinfo, in get_lvl1_pble()
417 palloc->total_cnt << 3, &lvl1->addr, in get_lvl1_pble()
423 lvl1->idx = fpm_to_idx(pble_rsrc, fpm_addr); in get_lvl1_pble()
424 lvl1->cnt = palloc->total_cnt; in get_lvl1_pble()
/linux/sound/soc/codecs/
H A Dmax98373.c264 SOC_SINGLE("BDE LVL1 Thresh", MAX98373_R2097_BDE_L1_THRESH, 0, 0xFF, 0),
275 SOC_SINGLE_TLV("BDE LVL1 Clip Thresh Volume", MAX98373_R20A9_BDE_L1_CFG_2,
283 SOC_SINGLE_TLV("BDE LVL1 Clip Reduction Volume", MAX98373_R20AA_BDE_L1_CFG_3,
291 SOC_SINGLE_TLV("BDE LVL1 Limiter Thresh Volume", MAX98373_R20A8_BDE_L1_CFG_1,
/linux/drivers/thermal/qcom/
H A DKconfig36 events. Current support handles a single LVL1 upper (hot) trip.
H A Dqcom-spmi-mbg-tm.c192 dev_dbg(chip->dev, "Lvl1 upper threshold not violated, ignoring interrupt\n"); in mbg_tm_isr()
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/
H A Dgsp.c1619 nvkm_gsp_mem_dtor(&rx3->lvl1); in nvkm_gsp_radix3_dtor()
1670 ret = nvkm_gsp_mem_ctor(gsp, GSP_PAGE_SIZE, &rx3->lvl1); in nvkm_gsp_radix3_sg()
1682 *pte = rx3->lvl1.addr; in nvkm_gsp_radix3_sg()
1685 pte = rx3->lvl1.data; in nvkm_gsp_radix3_sg()
1708 nvkm_gsp_mem_dtor(&rx3->lvl1); in nvkm_gsp_radix3_sg()
/linux/drivers/gpu/drm/nouveau/include/nvkm/subdev/
H A Dgsp.h25 struct nvkm_gsp_mem lvl1; member
/linux/drivers/iommu/
H A Dio-pgtable-arm-v7s.c48 * MediaTek extend 2 bits to reach 34bits, 14 bits at lvl1 and 8 bits at lvl2.
/linux/drivers/irqchip/
H A Dirq-gic-v3-its.c2511 * which is 'psz'. For computing lvl1 table size, in its_parse_indirect_baser()
2513 * which is reported by ITS hardware times lvl1 table in its_parse_indirect_baser()
2885 /* Flush Lvl1 entry to PoC if hw doesn't support coherency */ in allocate_vpe_l2_table()
3395 /* Flush Lvl1 entry to PoC if hw doesn't support coherency */ in its_alloc_table_entry()