Home
last modified time | relevance | path

Searched full:ipi (Results 1 – 25 of 203) sorted by relevance

123456789

/linux/arch/mips/kvm/
H A Dloongson_ipi.c3 * Loongson-3 Virtual IPI interrupt support.
53 static int loongson_vipi_read(struct loongson_kvm_ipi *ipi, in loongson_vipi_read() argument
61 struct ipi_state *s = &(ipi->ipistate[id]); in loongson_vipi_read()
98 static int loongson_vipi_write(struct loongson_kvm_ipi *ipi, in loongson_vipi_write() argument
106 struct kvm *kvm = ipi->kvm; in loongson_vipi_write()
108 struct ipi_state *s = &(ipi->ipistate[id]); in loongson_vipi_write()
157 struct loongson_kvm_ipi *ipi; in kvm_ipi_read() local
161 ipi = ipi_device->ipi; in kvm_ipi_read()
163 spin_lock_irqsave(&ipi->lock, flags); in kvm_ipi_read()
164 loongson_vipi_read(ipi, addr, len, val); in kvm_ipi_read()
[all …]
/linux/kernel/irq/
H A Dipi.c6 * This file contains driver APIs to the IPI subsystem.
9 #define pr_fmt(fmt) "genirq/ipi: " fmt
15 * irq_reserve_ipi() - Setup an IPI to destination cpumask
16 * @domain: IPI domain
17 * @dest: cpumask of CPUs which can receive the IPI
19 * Allocate a virq that can be used to send IPI to any CPU in dest mask.
31 pr_warn("Reservation on a non IPI domain\n"); in irq_reserve_ipi()
59 * The IPI requires a separate HW irq on each CPU. We require in irq_reserve_ipi()
62 * several IPI ranges. in irq_reserve_ipi()
80 pr_warn("Can't reserve IPI, failed to alloc descs\n"); in irq_reserve_ipi()
[all …]
H A Dipi-mux.c3 * Multiplex several virtual IPIs over a single HW IPI.
9 #define pr_fmt(fmt) "ipi-mux: " fmt
49 /* If a pending IPI was unmasked, raise a parent IPI immediately. */ in ipi_mux_unmask()
81 * The flag writes must complete before the physical IPI is in ipi_mux_send_mask()
92 .name = "IPI Mux",
146 * parent IPI.
149 * @mux_send: callback to trigger parent IPI for a particular CPU
170 fwnode = irq_domain_alloc_named_fwnode("IPI-Mux"); in ipi_mux_create()
172 pr_err("unable to create IPI Mux fwnode\n"); in ipi_mux_create()
180 pr_err("unable to add IPI Mux domain\n"); in ipi_mux_create()
[all …]
/linux/Documentation/virt/kvm/
H A Dvcpu-requests.rst49 order to perform some KVM maintenance. To do so, an IPI is sent, forcing
55 1) Send an IPI. This forces a guest mode exit.
70 as well as to avoid sending unnecessary IPIs (see "IPI Reduction"), and
71 even to ensure IPI acknowledgements are waited upon (see "Waiting for
160 then the caller will wait for each VCPU to acknowledge its IPI before
162 If, for example, the VCPU is sleeping, so no IPI is necessary, then
192 kick will send an IPI to force an exit from guest mode when necessary.
197 enter guest mode. This means that an optimized implementation (see "IPI
198 Reduction") must be certain when it's safe to not send the IPI. One
208 !kvm_request_pending() on its last check and then not receiving an IPI for
[all …]
/linux/arch/hexagon/kernel/
H A Dsmp.c38 static inline void __handle_ipi(unsigned long *ops, struct ipi_data *ipi, in __handle_ipi() argument
69 /* Used for IPI call from other CPU's to unmask int */
77 * This is based on Alpha's IPI stuff.
85 struct ipi_data *ipi = &per_cpu(ipi_data, cpu); in handle_ipi() local
88 while ((ops = xchg(&ipi->bits, 0)) != 0) in handle_ipi()
89 __handle_ipi(&ops, ipi, cpu); in handle_ipi()
102 struct ipi_data *ipi = &per_cpu(ipi_data, cpu); in send_ipi() local
104 set_bit(msg, &ipi->bits); in send_ipi()
208 /* Also need to register the interrupts for IPI */ in smp_prepare_cpus()
/linux/arch/riscv/kernel/
H A Dsbi-ipi.c3 * Multiplex several IPIs over a single HW IPI.
70 * Don't disable IPI when CPU goes offline because in sbi_ipi_init()
72 * via generic IPI-Mux in sbi_ipi_init()
75 "irqchip/sbi-ipi:starting", in sbi_ipi_init()
79 pr_info("providing IPIs using SBI IPI extension\n"); in sbi_ipi_init()
/linux/arch/arc/kernel/
H A Dsmp.c244 * figure out what msg was sent. For those which don't (ARC has dedicated IPI
270 * Call the platform specific IPI kick function, but avoid if possible: in ipi_send_msg_one()
273 * IPI corresponding to that msg. This is true, even if it is already in in ipi_send_msg_one()
274 * IPI handler, because !@old means it has not yet dequeued the msg(s) in ipi_send_msg_one()
315 * ipi_cpu_stop - handle IPI from smp_send_stop()
348 * Has hooks for platform specific IPI
355 pr_debug("IPI [%ld] received on cpu %d\n", in do_IPI()
362 * "dequeue" the msg corresponding to this IPI (and possibly other in do_IPI()
373 pr_info("IPI with bogus msg %ld in %ld\n", msg, copy); in do_IPI()
381 * API called by platform code to hookup arch-common ISR to their IPI IRQ
[all …]
/linux/arch/riscv/include/asm/
H A Dsmp.h28 /* print IPI stats */
42 /* Enable IPI for CPU hotplug */
45 /* Disable IPI for CPU hotplug */
48 /* Check if IPI interrupt numbers are available */
51 /* Set the IPI interrupt numbers for arch (called by irqchip drivers) */
/linux/drivers/irqchip/
H A Dirq-riscv-imsic-early.c69 /* Create IMSIC IPI multiplexing */ in imsic_ipi_domain_init()
202 /* Initialize IPI domain */ in imsic_early_probe()
205 pr_err("%pfwP: Failed to initialize IPI domain\n", fwnode); in imsic_early_probe()
216 * because this affects IPI and the masking/unmasking of in imsic_early_probe()
217 * virtual IPIs is done via generic IPI-Mux in imsic_early_probe()
298 * Even if imsic_platform_acpi_probe() fails, the IPI part of IMSIC can in imsic_early_acpi_init()
300 * DT where IPI works but MSI probe fails for some reason. in imsic_early_acpi_init()
H A Dirq-armada-370-xp.c139 /* IPI and MSI interrupt definitions for IPI platforms */
146 /* MSI interrupt definitions for non-IPI platforms */
159 * @ipi_domain: IPI domain
194 * We distinguish IPI availability in the IC by the IC not having a in mpic_is_ipi_available()
367 /* Unmask low 16 MSI irqs on non-IPI platforms */ in mpic_msi_init()
433 * other CPUs before issuing the IPI. in mpic_ipi_send_mask()
449 .name = "IPI",
543 /* Unmask IPI interrupt */ in mpic_smp_cpu_init()
723 /* IPI Handling */ in mpic_handle_irq()
859 * it is used to distinguish between IPI and non-IPI platforms. in mpic_of_init()
[all …]
/linux/Documentation/admin-guide/hw-vuln/
H A Dcore-scheduling.rst112 Once a task has been selected for all the siblings in the core, an IPI is sent to
113 siblings for whom a new task was selected. Siblings on receiving the IPI will
130 When the highest priority task is selected to run, a reschedule-IPI is sent to
142 (victim) to enter idle mode. This is because the sending of the IPI would bring
145 which may not be worth protecting. It is also possible that the IPI is received
171 IPI processing delays
173 Core scheduling selects only trusted tasks to run together. IPI is used to notify
175 receiving of the IPI on some arch (on x86, this has not been observed). This may
177 IPI. Even though cache is flushed on entry to user mode, victim tasks on siblings
/linux/arch/powerpc/sysdev/xics/
H A Dicp-opal.c26 /* Clear any pending IPI */ in icp_opal_teardown_cpu()
33 * We take the ipi irq but and never return so we need to EOI the IPI, in icp_opal_flush_ipi()
92 * Here be dragons. The caller has asked to allow only IPI's and not in icp_opal_set_cpu_priority()
159 /* Clear pending IPI */ in icp_opal_flush_interrupt()
H A Dicp-hv.c65 /* Make sure all previous accesses are ordered before IPI sending */ in icp_hv_set_qirr()
87 /* Clear any pending IPI */ in icp_hv_teardown_cpu()
93 /* We take the ipi irq but and never return so we in icp_hv_flush_ipi()
94 * need to EOI the IPI, but want to leave our priority 0 in icp_hv_flush_ipi()
H A Dxics-common.c126 unsigned int ipi; in xics_request_ipi() local
128 ipi = irq_create_mapping(xics_host, XICS_IPI); in xics_request_ipi()
129 BUG_ON(!ipi); in xics_request_ipi()
134 BUG_ON(request_irq(ipi, icp_ops->ipi_action, in xics_request_ipi()
135 IRQF_NO_DEBUG | IRQF_PERCPU | IRQF_NO_THREAD, "IPI", NULL)); in xics_request_ipi()
155 * not going to return from the IPI in xics_teardown_cpu()
257 * interrupts, the expectation is that we'll only get woken up by an IPI in xics_migrate_irqs_away()
525 /* Patch up IPI chip EOI */ in xics_init()
/linux/tools/testing/selftests/kvm/x86/
H A Dxapic_ipi_test.c9 * Test that when the APIC is in xAPIC mode, a vCPU can send an IPI to wake
15 * has reentered HLT before sending the next IPI. While the vCPUs are running,
41 * Vector for IPI from sender vCPU to halting vCPU.
48 * Incremented in the IPI handler. Provides evidence to the sender that the IPI
116 * Runs on halter vCPU when IPI arrives. Write an arbitrary non-zero value to
159 * Send IPI to halter vCPU. in sender_guest_code()
160 * First IPI can be sent unconditionally because halter vCPU in sender_guest_code()
169 * 1. Received the IPI in sender_guest_code()
346 "IPI, HLT and wake count have not increased " in do_migrations()
454 "IPI sender vCPU thread started. Letting vCPUs run for %d seconds.\n", in main()
/linux/tools/perf/pmu-events/arch/riscv/
H A Driscv-sbi-firmware.json39 "PublicDescription": "Sent IPI to other HART event",
42 "BriefDescription": "Sent IPI to other HART event"
45 "PublicDescription": "Received IPI from other HART event",
48 "BriefDescription": "Received IPI from other HART event"
/linux/Documentation/virt/kvm/loongarch/
H A Dhypercalls.rst88 PV IPI on LoongArch includes both PV IPI multicast sending and PV IPI receiving,
89 and SWI is used for PV IPI inject since there is no VM-exits accessing SWI registers.
/linux/Documentation/features/sched/membarrier-sync-core/
H A Darch-support.txt11 # when returning from IPI handler, and when returning to user-space.
31 # x86-32 uses IRET as return from interrupt, which takes care of the IPI.
35 # x86-64 uses IRET as return from interrupt, which takes care of the IPI.
/linux/arch/powerpc/kvm/
H A Dbook3s_hv_builtin.c200 * to memory vs. the IPI/message.
227 /* Else poke the target with an IPI */ in kvmhv_rm_send_ipi()
243 /* Order setting of exit map vs. msgsnd/IPI */ in kvmhv_interrupt_vcore()
332 * If we have an interrupt that's not an IPI, check if we have a
378 * -1 if there was a guest wakeup IPI (which has now been cleared)
413 /* see if a host IPI is pending */ in kvmppc_read_one_intr()
449 * If it is an IPI, clear the MFRR and EOI it. in kvmppc_read_one_intr()
470 * We need to re-check host IPI now in case it got set in the in kvmppc_read_one_intr()
477 * we need to resend that IPI, bummer in kvmppc_read_one_intr()
490 /* OK, it's an IPI for us */ in kvmppc_read_one_intr()
/linux/arch/arm/include/asm/
H A Dsmp.h23 * generate IPI list text
28 * Called from C code, this handles an IPI.
38 * Register IPI interrupts with the arch SMP code
/linux/scripts/gdb/linux/
H A Dinterrupts.py134 for ipi in range(nr_ipi):
135 text += "%*s%u: " % (prec - 1, "IPI", ipi)
136 desc = ipi_desc[ipi].cast(irq_desc_type.get_type().pointer())
141 text += "%s" % (ipi_types[ipi].string())
/linux/include/soc/arc/
H A Dmcip.h3 * ARConnect IP Support (Multi core enabler: Cross core IPI, RTC ...)
66 msg:1, sem:1, ipi:1, slv:1, member
70 slv:1, ipi:1, sem:1, msg:1,
/linux/Documentation/translations/zh_TW/arch/loongarch/
H A Dirq-chip-model.rst26 在這種模型裏面，IPI（Inter-Processor Interrupt）和CPU本地時鐘中斷直接發送到CPUINTC，
31 | IPI | --> | CPUINTC | <-- | Timer |
62 在這種模型裏面，IPI（Inter-Processor Interrupt）和CPU本地時鐘中斷直接發送到CPUINTC，
67 | IPI | --> | CPUINTC | <-- | Timer |
/linux/arch/x86/kernel/cpu/
H A Dumwait.c46 * and issue the IPI before the old value had been written. The IPI would
47 * interrupt, write the new value and after return from IPI the previous
51 * value or the IPI is updating this CPU to the new control value after
/linux/arch/sh/kernel/cpu/sh2/
H A Dsmp-j2.c48 np = of_find_compatible_node(NULL, NULL, "jcore,ipi-controller"); in j2_prepare_cpus()
66 "ipi", (void *)j2_ipi_interrupt_handler) != 0) in j2_prepare_cpus()
114 /* There is only one IPI interrupt shared by all messages, so in j2_send_ipi()

123456789