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/freebsd/crypto/openssl/crypto/poly1305/asm/
H A Dpoly1305-mips.pl2 # Copyright 2016-2020 The OpenSSL Project Authors. All Rights Reserved.
24 # R1x000 5.64/+120% (big-endian)
25 # Octeon II 3.80/+280% (little-endian)
41 # - never ever touch $tp, "thread pointer", former $gp [o32 can be
43 # - copy return value to $t0, former $v0 [or to $a0 if you're adapting
45 # - on O32 populate $a4-$a7 with 'lw $aN,4*N($sp)' if necessary;
71 ($in0,$in1,$tmp0,$tmp1,$tmp2,$tmp3,$tmp4) = ($a4,$a5,$a6,$a7,$at,$t0,$t1);
102 ld $in0,0($inp)
103 ld $in1,8($inp)
105 ldl $in0,0+MSB($inp)
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H A Dpoly1305-sparcv9.pl2 # Copyright 2016-2021 The OpenSSL Project Authors. All Rights Reserved.
31 # (*) Comparison to compiler-generated code is really problematic,
34 # improvement on T4 for gcc-4.6. Well, in T4 case it's a bit
37 # (**) Pre-III performance should be even worse; floating-point
38 # performance for UltraSPARC I-IV on the other hand is reported
39 # to be 4.25 for hand-coded assembly, but they are just too old
41 # (***) Multi-process benchmark saturates at ~12.5x single-process
42 # result on 8-core processor, or ~21GBps per 2.85GHz socket.
80 save %sp,-STACK_FRAME-16,%sp
109 ldxa [$inp+%g0]0x88,$h0 ! load little-endian key
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H A Dpoly1305-ppcfp.pl2 # Copyright 2016-2020 The OpenSSL Project Authors. All Rights Reserved.
22 # and improvement coefficients relative to gcc-generated code.
56 ( $xlate="${dir}ppc-xlate.pl" and -f $xlate ) or
57 ( $xlate="${dir}../../perlasm/ppc-xlate.pl" and -f $xlate) or
58 die "can't locate ppc-xlate.pl";
69 my ($in0,$in1,$in2,$in3,$i1,$i2,$i3) = map("r$_",(7..12,6));
88 $STU $sp,-$LOCALS($sp) # minimal frame
110 beq- Lno_key
120 li $in1,4
123 $LWXLE $in0,0,$inp # load key
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/freebsd/crypto/openssl/crypto/aes/asm/
H A Daesp8-ppc.pl2 # Copyright 2014-2024 The OpenSSL Project Authors. All Rights Reserved.
19 # The module is endian-agnostic in sense that it supports both big-
20 # and little-endian cases. Data alignment in parallelizable modes is
25 # is aligned programmatically, which in turn guarantees exception-
33 # Add XTS subroutine, 9x on little- and 12x improvement on big-endian
37 # Current large-block performance in cycles per byte processed with
38 # 128-bit key (less is better).
40 # CBC en-/decrypt CTR XTS
72 ( $xlate="${dir}ppc-xlate.pl" and -f $xlate ) or
73 ( $xlate="${dir}../../perlasm/ppc-xlate.pl" and -f $xlate) or
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H A Daesv8-armx.pl2 # Copyright 2014-2023 The OpenSSL Project Authors. All Rights Reserved.
18 # module is endian-agnostic in sense that it supports both big- and
19 # little-endian cases. As does it support both 32- and 64-bit modes
24 # instruction latencies and issue rates. On Cortex-A53, an in-order
25 # execution core, this costs up to 10-15%, which is partially
26 # compensated by implementing dedicated code path for 128-bit
27 # CBC encrypt case. On Cortex-A57 parallelizable mode performance
32 # Key to performance of parallelize-able modes is round instruction
42 # Performance in cycles per byte processed with 128-bit key:
46 # Cortex-A53 1.32 1.17/1.29(**) 1.36/1.46
[all …]
H A Daesfx-sparcv9.pl2 # Copyright 2016-2021 The OpenSSL Project Authors. All Rights Reserved.
20 # required key setup and single-block procedures.
24 # Add "teaser" CBC and CTR mode-specific subroutines. "Teaser" means
27 # get processing one byte in 4.1 cycles with 128-bit key on SPARC64 X.
33 # instructions and improve single-block and short-input performance
62 add %o7, .Linp_align-1b, %o7
139 .size aes_fx_encrypt,.-aes_fx_encrypt
152 add %o7, .Linp_align-1b, %o7
229 .size aes_fx_decrypt,.-aes_fx_decrypt
239 mov -1, $inc
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H A Daes-ia64.S1 // Copyright 2004-2016 The OpenSSL Project Authors. All Rights Reserved.
16 // Then it uses 'zxt' which is an I-type, but can be replaced with
17 // 'and' which in turn can be assigned to M-port [there're double as
18 // much M-ports as there're I-ports on Itanium 2]. By sacrificing few
22 // generated code by over factor of 2 (two), GCC 3.4 - by 70% and
23 // HP C - by 40%. Measured best-case scenario, i.e. aligned
24 // big-endian input, ECB timing on Itanium 2 is (18 + 13*rounds)
27 // Version 1.2 mitigates the hazard of cache-timing attacks by
28 // a) compressing S-boxes from 8KB to 2KB+256B, b) scheduling
29 // references to S-boxes for L2 cache latency, c) prefetching T[ed]4
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H A Daesni-x86_64.pl2 # Copyright 2009-2020 The OpenSSL Project Authors. All Rights Reserved.
17 # This module implements support for Intel AES-NI extension. In
19 # drop-in replacement for crypto/aes/asm/aes-x86_64.pl [see below for
25 # non-parallelizable modes such as CBC encrypt is 3.75 cycles per byte
26 # processed with 128-bit key. And given their throughput asymptotic
30 # different modes and block sized. Pairs of numbers are for en-/
33 # 16-byte 64-byte 256-byte 1-KB 8-KB
42 # that otherwise used 'openssl speed -evp aes-128-??? -engine aesni
43 # [-decrypt]' will exhibit 10-15% worse results for smaller blocks.
51 # Looking at the results for 8-KB buffer.
[all …]
H A Daesni-x86.pl2 # Copyright 2009-2022 The OpenSSL Project Authors. All Rights Reserved.
17 # This module implements support for Intel AES-NI extension. In
19 # drop-in replacement for crypto/aes/asm/aes-586.pl [see below for
24 # To start with see corresponding paragraph in aesni-x86_64.pl...
27 # The simplified table below represents 32-bit performance relative
28 # to 64-bit one in every given point. Ratios vary for different
31 # 16-byte 64-byte 256-byte 1-KB 8-KB
32 # 53-67% 67-84% 91-94% 95-98% 97-99.5%
35 # because function call overhead is higher in 32-bit mode. Largest
36 # 8-KB block performance is virtually same: 32-bit code is less than
[all …]
/freebsd/crypto/openssl/crypto/modes/asm/
H A Dghashp8-ppc.pl2 # Copyright 2014-2020 The OpenSSL Project Authors. All Rights Reserved.
24 # version is ~2.1x slower than hardware-assisted AES-128-CTR, ~12x
25 # faster than "4-bit" integer-only compiler-generated 64-bit code.
32 # aggregated reduction - by 170% or 2.7x (resulting in 0.55 cpb).
59 $FRAME=6*$SIZE_T+13*16; # 13*16 is for v20-v31 offload
62 ( $xlate="${dir}ppc-xlate.pl" and -f $xlate ) or
63 ( $xlate="${dir}../../perlasm/ppc-xlate.pl" and -f $xlate) or
64 die "can't locate ppc-xlate.pl";
73 my ($Xl1,$Xm1,$Xh1,$IN1,$H2,$H2h,$H2l)=map("v$_",(13..19));
84 li r0,-4096
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H A Dghash-ia64.pl2 # Copyright 2010-2020 The OpenSSL Project Authors. All Rights Reserved.
19 # The module implements "4-bit" GCM GHASH function and underlying
20 # single multiplication operation in GF(2^128). "4-bit" means that it
21 # uses 256 bytes per-key table [+128 bytes shared table]. Streamed
24 # code. To anchor to something else sha1-ia64.pl module processes one
35 # But occasionally you prove yourself wrong:-) I figured out a way to
46 for (@ARGV) { $ADDP="add" if (/[\+DD|\-mlp]64/); }
48 for (@ARGV) { $big_endian=1 if (/\-DB_ENDIAN/);
49 $big_endian=0 if (/\-DL_ENDIAN/); }
58 # in scalable manner;-) Naturally assuming data in L1 cache...
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/freebsd/crypto/openssl/crypto/des/asm/
H A Ddes_enc.m41 ! Copyright 2000-2018 The OpenSSL Project Authors. All Rights Reserved.
8 ! To expand the m4 macros: m4 -B 8192 des_enc.m4 > des_enc.S
15 ! Assemble through gcc: gcc -c -mcpu=ultrasparc -o des_enc.o des_enc.S
17 ! Assemble through cc: cc -c -xarch=v8plusa -o des_enc.o des_enc.S
21 ! 32-bit build:
22 ! 23% faster than cc-5.2 -xarch=v8plus -xO5
23 ! 115% faster than gcc-3.2.1 -m32 -mcpu=ultrasparc -O5
24 ! 64-bit build:
25 ! 50% faster than cc-5.2 -xarch=v9 -xO5
26 ! 100% faster than gcc-3.2.1 -m64 -mcpu=ultrasparc -O5
[all …]
/freebsd/crypto/openssl/ms/
H A Dcmp.pl2 # Copyright 1995-2016 The OpenSSL Project Authors. All Rights Reserved.
11 open(IN0,"<$ARGV[0]") || die "unable to open $ARGV[0]\n";
12 open(IN1,"<$ARGV[1]") || die "unable to open $ARGV[1]\n";
13 binmode IN0;
14 binmode IN1;
20 $n1=sysread(IN0,$b1,4096);
21 $n2=sysread(IN1,$b2,4096);
34 close(IN0);
35 close(IN1);
/freebsd/sys/contrib/device-tree/Bindings/hwmon/
H A Dadc128d818.txt2 --------------------------------------------------------
6 - Mode 0: 7 single-ended voltage readings (IN0-IN6),
8 - Mode 1: 8 single-ended voltage readings (IN0-IN7),
10 - Mode 2: 4 pseudo-differential voltage readings
11 (IN0-IN1, IN3-IN2, IN4-IN5, IN7-IN6),
13 - Mode 3: 4 single-ended voltage readings (IN0-IN3),
14 2 pseudo-differential voltage readings
15 (IN4-IN5, IN7-IN6),
24 - compatible: must be set to "ti,adc128d818"
25 - reg: I2C address of the device
[all …]
H A Dti,adc128d818.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Javier Carrasco <javier.carrasco.cruz@gmail.com>
14 The ADC128D818 is a 12-Bit, 8-Channel Analog to Digital Converter (ADC)
31 Mode 0 - 7 single-ended voltage readings (IN0-IN6), 1 temperature
33 Mode 1 - 8 single-ended voltage readings (IN0-IN7), no temperature.
34 Mode 2 - 4 pseudo-differential voltage readings
35 (IN0-IN1, IN3-IN2, IN4-IN5, IN7-IN6), 1 temperature reading (internal).
36 Mode 3 - 4 single-ended voltage readings (IN0-IN3), 2 pseudo-differential
[all …]
H A Dadt7475.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jean Delvare <jdelvare@suse.com>
23 https://www.onsemi.com/pub/Collateral/ADT7473-D.PDF
24 https://www.onsemi.com/pub/Collateral/ADT7475-D.PDF
25 https://www.onsemi.com/pub/Collateral/ADT7476-D.PDF
26 https://www.onsemi.com/pub/Collateral/ADT7490-D.PDF
34 - adi,adt7473
35 - adi,adt7475
[all …]
/freebsd/crypto/openssl/crypto/poly1305/
H A Dpoly1305_ieee754.c2 * Copyright 2016-2018 The OpenSSL Project Authors. All Rights Reserved.
11 * This module is meant to be used as template for non-x87 floating-
12 * point assembly modules. The template itself is x86_64-specific
14 * have to recognize platform-specific parts, UxTOy and inline asm,
17 * Huh? x86_64-specific code as template for non-x87? Note seven, which
18 * is not a typo, but reference to 80-bit precision. This module on the
19 * other hand relies on 64-bit precision operations, which are default
21 * large-block performance in cycles per processed byte for *this* code
23 * gcc-4.8 icc-15.0 clang-3.4(*)
50 # error "this is gcc-specific template"
[all …]
/freebsd/sys/contrib/device-tree/Bindings/iio/afe/
H A Dcurrent-sense-shunt.txt4 When an io-channel measures the voltage over a current sense shunt,
10 - compatible : "current-sense-shunt"
11 - io-channels : Channel node of a voltage io-channel.
12 - shunt-resistor-micro-ohms : The shunt resistance in microohms.
19 compatible = "current-sense-shunt";
20 io-channels = <&tiadc 0>;
23 shunt-resistor-micro-ohms = <3300000>;
30 #io-channel-cells = <1>;
32 #address-cells = <1>;
33 #size-cells = <0>;
[all …]
H A Dcurrent-sense-shunt.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/afe/current-sense-shunt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Rosin <peda@axentia.se>
13 When an io-channel measures the voltage over a current sense shunt,
20 const: current-sense-shunt
22 io-channels:
25 Channel node of a voltage io-channel.
27 "#io-channel-cells":
[all …]
/freebsd/contrib/ncurses/ncurses/tinfo/
H A Dcaptoinfo.c2 * Copyright 2018-2020,2021 Thomas E. Dickey *
3 * Copyright 1998-2016,2017 Free Software Foundation, Inc. *
31 * Author: Zeyd M. Ben-Halim <zmbenhal@netcom.com> 1992,1995 *
33 * and: Thomas E. Dickey 1996-on *
41 * cap-to-info --- conversion between termcap and terminfo formats
53 * This code recognizes all the standard 4.4BSD %-escapes:
64 * %n exclusive-or all parameters with 0140 (Datamedia 2500)
66 * %D Reverse coding (value - 2*(value%16)), no output (Delta Data).
74 * %a[+*-/=][cp]x GNU arithmetic.
80 * %-x subtract parameter FROM char x and output it as a char
[all …]
/freebsd/sys/contrib/device-tree/Bindings/iio/adc/
H A Dadi,ad4695.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <Michael.Hennerich@analog.com>
11 - Nuno Sá <nuno.sa@analog.com>
14 A family of similar multi-channel analog to digital converters with SPI bus.
21 $ref: /schemas/spi/spi-peripheral-props.yaml#
26 - adi,ad4695
27 - adi,ad4696
28 - adi,ad4697
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dsilabs,si5341.txt6 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
8 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
10 https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
21 chip at boot, in case you have a (pre-)programmed device. If the PLL is not
33 - compatible: shall be one of the following:
34 "silabs,si5340" - Si5340 A/B/C/D
35 "silabs,si5341" - Si5341 A/B/C/D
36 "silabs,si5342" - Si5342 A/B/C/D
37 "silabs,si5344" - Si5344 A/B/C/D
38 "silabs,si5345" - Si5345 A/B/C/D
[all …]
/freebsd/sys/dev/sound/pci/
H A Demu10kx-pcm.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
5 * Copyright (c) 2003-2007 Yuriy Tsibizov <yuriy.tsibizov@gfk.ru>
173 /* no mixer device for ac97 */ /* in0 AC97 */
174 [SOUND_MIXER_DIGITAL1] = {1, 1, 1}, /* in1 CD SPDIF */
177 [SOUND_MIXER_LINE2] = {1, 1, 4}, /* in4 Line-In2 */
178 [SOUND_MIXER_DIGITAL3] = {1, 1, 5}, /* in5 on-card SPDIF */
187 [SOUND_MIXER_VOLUME] = {1, 0, (-1)},
188 [SOUND_MIXER_PCM] = {1, 0, (-1)},
190 /* no mixer device */ /* in0 AC97 */
[all …]
/freebsd/crypto/openssl/crypto/bn/asm/
H A Dia64-mont.pl2 # Copyright 2010-2020 The OpenSSL Project Authors. All Rights Reserved.
19 # "Teaser" Montgomery multiplication module for IA-64. There are
22 # - modulo-scheduling outer loop would eliminate quite a number of
25 # - shorter vector support [with input vectors being fetched only
27 # - 2x unroll with help of n0[1] would make the code scalable on
28 # "wider" IA-64, "wider" than Itanium 2 that is, which is not of
31 # - dedicated squaring procedure(?);
35 # Shorter vector support is implemented by zero-padding ap and np
36 # vectors up to 8 elements, or 512 bits. This means that 256-bit
37 # inputs will be processed only 2 times faster than 512-bit inputs,
[all …]
/freebsd/crypto/openssl/crypto/sha/asm/
H A Dsha1-ia64.pl2 # Copyright 2004-2016 The OpenSSL Project Authors. All Rights Reserved.
19 # to perform rotations by maintaining copy of 32-bit value in upper
20 # bits of 64-bit register. Just follow mux2 and shrp instructions...
21 # Performance under big-endian OS such as HP-UX is 179MBps*1GHz, which
28 .ident \"sha1-ia64.s, version 1.3\"
29 .ident \"IA-64 ISA artwork by Andy Polyakov <appro\@fy.chalmers.se>\"
37 for (@ARGV) { $ADDP="add" if (/[\+DD|\-mlp]64/); }
239 ctx=r32; // in0
240 inp=r33; // in1
267 { .mmi; ld4 $h4=[ctx],-16
[all …]

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