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/linux/drivers/gpu/drm/vc4/
H A Dvc4_hvs.c7 * DOC: VC4 HVS module.
9 * The Hardware Video Scaler (HVS) is the piece of hardware that does
16 * There is a single global HVS, with multiple output FIFOs that can
18 * the HVS, while the vc4_crtc.c code actually drives HVS setup for
204 void vc4_hvs_dump_state(struct vc4_hvs *hvs) in vc4_hvs_dump_state() argument
206 struct drm_device *drm = &hvs->vc4->base; in vc4_hvs_dump_state()
207 struct drm_printer p = drm_info_printer(&hvs->pdev->dev); in vc4_hvs_dump_state()
213 drm_print_regset32(&p, &hvs->regset); in vc4_hvs_dump_state()
215 DRM_INFO("HVS ctx:\n"); in vc4_hvs_dump_state()
219 readl((u32 __iomem *)hvs->dlist + i + 0), in vc4_hvs_dump_state()
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H A Dvc4_plane.c9 * Each DRM plane is a layer of pixels being scanned out by the HVS.
11 * At atomic modeset check time, we compute the HVS display element
15 * into the region of the HVS that it has allocated for us.
35 u32 hvs; /* HVS_FORMAT_* */ member
42 .hvs = HVS_PIXEL_FORMAT_RGBA8888,
48 .hvs = HVS_PIXEL_FORMAT_RGBA8888,
54 .hvs = HVS_PIXEL_FORMAT_RGBA8888,
60 .hvs = HVS_PIXEL_FORMAT_RGBA8888,
66 .hvs = HVS_PIXEL_FORMAT_RGB565,
72 .hvs = HVS_PIXEL_FORMAT_RGB565,
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H A Dvc4_kms.c137 struct vc4_hvs *hvs = vc4->hvs; in vc4_ctm_commit() local
213 struct vc4_hvs *hvs = vc4->hvs; in vc4_hvs_pv_muxing_commit() local
256 struct vc4_hvs *hvs = vc4->hvs; in vc5_hvs_pv_muxing_commit() local
332 struct vc4_hvs *hvs = vc4->hvs; in vc6_hvs_pv_muxing_commit() local
381 struct vc4_hvs *hvs = vc4->hvs; in vc4_atomic_commit_tail() local
406 vc4_hvs_mask_underrun(hvs, vc4_crtc_state->assigned_channel); in vc4_atomic_commit_tail()
433 500000000, hvs->max_core_rate); in vc4_atomic_commit_tail()
441 WARN_ON(clk_set_min_rate(hvs->core_clk, core_rate)); in vc4_atomic_commit_tail()
442 WARN_ON(clk_set_min_rate(hvs->disp_clk, core_rate)); in vc4_atomic_commit_tail()
484 hvs->max_core_rate, in vc4_atomic_commit_tail()
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H A Dvc4_crtc.c12 * the HVS at that timing, and feeds it to the encoder.
16 * responsible for writing the display list for the HVS channel that
85 struct vc4_hvs *hvs = vc4->hvs; in vc4_crtc_get_cob_allocation() local
114 struct vc4_hvs *hvs = vc4->hvs; in vc4_crtc_get_scanout_position() local
132 * pixelvalve by the HVS, and also the scaler status. in vc4_crtc_get_scanout_position()
145 /* Vertical position of hvs composed scanline. */ in vc4_crtc_get_scanout_position()
158 if (vc4_hvs_get_fifo_frame_count(hvs, channel) % 2) in vc4_crtc_get_scanout_position()
163 /* This is the offset we need for translating hvs -> pv scanout pos. */ in vc4_crtc_get_scanout_position()
169 /* HVS more than fifo_lines into frame for compositing? */ in vc4_crtc_get_scanout_position()
173 * from HVS. The actual PV scanout can not trail behind more in vc4_crtc_get_scanout_position()
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H A Dvc4_drv.h99 struct vc4_hvs *hvs; member
213 * demanding in term of memory or HVS bandwidth which is hard to guess
330 /* Pointer back to the HVS structure */
331 struct vc4_hvs *hvs; member
353 /* Memory manager for the LBM memory used by HVS scaling. */
470 /* Load of this plane on the HVS block. The load is expressed in HVS
534 /* Bitmask of channels (FIFOs) of the HVS that the output can source from */
537 /* Which output of the HVS this pixelvalve sources from. */
605 * set in the HVS for that CRTC. Protected by @irq_lock, and
612 * @current_hvs_channel: HVS channel currently assigned to the
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H A Dvc4_regs.h24 WARN_ON(!FIELD_FIT(hvs->vc4->gen == VC4_GEN_6_C ? \
27 FIELD_PREP(hvs->vc4->gen == VC4_GEN_6_C ? \
32 #define VC6_GET_FIELD(word, field) FIELD_GET(hvs->vc4->gen == VC4_GEN_6_C ? \
241 /* Global register for clock gating the HVS */
419 /* Last pixel in the COB (display FIFO memory) allocated to this HVS
425 /* First pixel in the COB (display FIFO memory) allocated to this HVS
520 /* Slave addresses for DMAing from HVS composition output to other
565 #define SCALER6_DISPX_CTRL0(x) ((hvs->vc4->gen == VC4_GEN_6_C) ? \
576 #define SCALER6_DISPX_CTRL1(x) ((hvs->vc4->gen == VC4_GEN_6_C) ? \
583 #define SCALER6_DISPX_BGND(x) ((hvs->vc4->gen == VC4_GEN_6_C) ? \
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H A Dvc4_drv.c278 { .compatible = "brcm,bcm2711-hvs" },
279 { .compatible = "brcm,bcm2712-hvs" },
280 { .compatible = "brcm,bcm2835-hvs" },
427 * but after the HVS to set the possible_crtc field properly
428 * - The HDMI driver needs to be bound after the HVS so that we can
429 * lookup the HVS maximum core clock rate and figure out if we
H A Dvc4_txp.c50 /* Pre-rotation width/height of the image. Must match HVS config.
133 /* Request odd field from HVS. */
H A Dvc4_hdmi.c475 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20) { in vc4_hdmi_connector_get_modes()
1682 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20 && clock > HDMI_14_MAX_TMDS_CLK) in vc4_hdmi_connector_clock_valid()
1686 if (!vc4->hvs->vc5_hdmi_enable_4096by2160 && in vc4_hdmi_connector_clock_valid()
/linux/Documentation/devicetree/bindings/display/
H A Dbrcm,bcm2835-hvs.yaml4 $id: http://devicetree.org/schemas/display/brcm,bcm2835-hvs.yaml#
15 - brcm,bcm2711-hvs
16 - brcm,bcm2712-hvs
17 - brcm,bcm2835-hvs
41 - brcm,bcm2711-hvs
42 - brcm,bcm2712-hvs
50 hvs@7e400000 {
51 compatible = "brcm,bcm2835-hvs";
H A Dbrcm,bcm2835-vc4.yaml14 with HDMI output and the HVS (Hardware Video Scaler) for compositing
/linux/Documentation/gpu/
H A Dvc4.rst21 HVS section in Display Hardware Handling
25 :doc: VC4 HVS module.
27 HVS planes
73 * The HVS to PixelValve dynamic FIFO assignment, for the BCM2835-7
/linux/drivers/gpu/drm/vc4/tests/
H A Dvc4_mock.c178 vc4->hvs = __vc4_hvs_alloc(vc4, NULL, NULL); in __mock_device()
179 KUNIT_ASSERT_NOT_ERR_OR_NULL(test, vc4->hvs); in __mock_device()
H A Dvc4_test_pv_muxing.c849 * This test makes sure that we never change the FIFO of an active HVS
/linux/tools/testing/selftests/net/
H A Dtest_vxlan_under_vrf.sh7 # two for the HVs, two for the VMs.
91 # Check connectivity between HVs by pinging hv-2 from hv-1
H A Dtest_vxlan_vnifiltering.sh7 # six namespaces: two for the HVs, four for the VMs. Each VM is
/linux/arch/arm64/boot/dts/broadcom/
H A Dbcm2712.dtsi459 hvs: hvs@107c580000 { label
460 compatible = "brcm,bcm2712-hvs";
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm2711-rpi.dtsi71 &hvs {
H A Dbcm283x.dtsi431 hvs@7e400000 {
432 compatible = "brcm,bcm2835-hvs";
H A Dbcm2711.dtsi292 hvs: hvs@7e400000 { label
293 compatible = "brcm,bcm2711-hvs";
/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_vfpf.h29 /* Common definitions for all HVs */
/linux/drivers/media/i2c/
H A Dimx274.c230 {0x3018, 0xA2}, /* output XVS, HVS */
271 {0x3018, 0xA2}, /* output XVS, HVS */
311 {0x3018, 0xA2}, /* output XVS, HVS */
351 {0x3018, 0xA2}, /* output XVS, HVS */
/linux/arch/x86/kernel/
H A Dirq.c160 seq_printf(p, "%*s: ", prec, "HVS"); in arch_show_interrupts()
/linux/include/uapi/drm/
H A Ddrm_fourcc.h1052 * HVS, it is only valid for H.264 (NV12/21) and RGBA modes.