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/linux/drivers/gpu/drm/amd/amdgpu/
H A Dhdp_v4_0.c27 #include "hdp/hdp_4_0_offset.h"
28 #include "hdp/hdp_4_0_sh_mask.h"
48 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1); in hdp_v4_0_invalidate_hdp()
49 RREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE); in hdp_v4_0_invalidate_hdp()
52 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); in hdp_v4_0_invalidate_hdp()
67 /* HDP SRAM errors are uncorrectable ones (i.e. fatal errors) */ in hdp_v4_0_query_ras_error_count()
68 err_data->ue_count += RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT); in hdp_v4_0_query_ras_error_count()
77 WREG32_SOC15(HDP, 0, mmHDP_EDC_CNT, 0); in hdp_v4_0_reset_ras_error_count()
79 /*read back hdp ras counter to reset it to 0 */ in hdp_v4_0_reset_ras_error_count()
80 RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT); in hdp_v4_0_reset_ras_error_count()
[all …]
H A Dhdp_v5_0.c26 #include "hdp/hdp_5_0_0_offset.h"
27 #include "hdp/hdp_5_0_0_sh_mask.h"
34 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1); in hdp_v5_0_invalidate_hdp()
35 RREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE); in hdp_v5_0_invalidate_hdp()
38 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); in hdp_v5_0_invalidate_hdp()
53 hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); in hdp_v5_0_update_mem_power_gating()
54 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); in hdp_v5_0_update_mem_power_gating()
62 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v5_0_update_mem_power_gating()
64 /* HDP 5.0 doesn't support dynamic power mode switch, in hdp_v5_0_update_mem_power_gating()
82 WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); in hdp_v5_0_update_mem_power_gating()
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H A Dhdp_v6_0.c26 #include "hdp/hdp_6_0_0_offset.h"
27 #include "hdp/hdp_6_0_0_sh_mask.h"
45 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1); in hdp_v6_0_update_clock_gating()
47 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL); in hdp_v6_0_update_clock_gating()
48 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); in hdp_v6_0_update_clock_gating()
55 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1, hdp_clk_cntl); in hdp_v6_0_update_clock_gating()
57 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v6_0_update_clock_gating()
76 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); in hdp_v6_0_update_clock_gating()
112 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); in hdp_v6_0_update_clock_gating()
120 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1, hdp_clk_cntl); in hdp_v6_0_update_clock_gating()
[all …]
H A Dhdp_v5_2.c26 #include "hdp/hdp_5_2_1_offset.h"
27 #include "hdp/hdp_5_2_1_sh_mask.h"
65 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL); in hdp_v5_2_update_mem_power_gating()
66 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); in hdp_v5_2_update_mem_power_gating()
73 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v5_2_update_mem_power_gating()
92 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); in hdp_v5_2_update_mem_power_gating()
127 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); in hdp_v5_2_update_mem_power_gating()
136 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v5_2_update_mem_power_gating()
147 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL); in hdp_v5_2_update_medium_grain_clock_gating()
167 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v5_2_update_medium_grain_clock_gating()
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H A Dhdp_v7_0.c26 #include "hdp/hdp_7_0_0_offset.h"
27 #include "hdp/hdp_7_0_0_sh_mask.h"
41 hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0,regHDP_CLK_CNTL); in hdp_v7_0_update_clock_gating()
42 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); in hdp_v7_0_update_clock_gating()
48 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v7_0_update_clock_gating()
67 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); in hdp_v7_0_update_clock_gating()
103 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); in hdp_v7_0_update_clock_gating()
110 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v7_0_update_clock_gating()
119 tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); in hdp_v7_0_get_clockgating_state()
H A Dmmhub_v2_0.c44 [14][0] = "HDP",
58 [14][1] = "HDP",
75 [14][0] = "HDP",
91 [14][1] = "HDP",
103 [14][0] = "HDP",
115 [14][1] = "HDP",
H A Dsoc24.c445 /* remap HDP registers to a hole in mmio space, in soc24_common_hw_init()
538 adev->hdp.funcs->update_clock_gating(adev, in soc24_common_set_clockgating_state()
571 adev->hdp.funcs->get_clock_gating_state(adev, flags); in soc24_common_get_clockgating_state()
H A Dsoc21.c972 /* remap HDP registers to a hole in mmio space, in soc21_common_hw_init()
1069 adev->hdp.funcs->update_clock_gating(adev, in soc21_common_set_clockgating_state()
1102 adev->hdp.funcs->get_clock_gating_state(adev, flags); in soc21_common_get_clockgating_state()
H A Dmmhub_v2_3.c41 [27][0] = "HDP",
52 [27][1] = "HDP",
H A Dsdma_v4_4_2.c393 int mem_space, int hdp, in sdma_v4_4_2_wait_reg_mem() argument
399 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) | in sdma_v4_4_2_wait_reg_mem()
418 * sdma_v4_4_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
422 * Emit an hdp flush packet on the requested DMA ring.
2141 3 + /* hdp invalidate */
2173 3 + /* hdp invalidate */
H A Dgmc_v11_0.c240 /* flush hdp cache */ in gmc_v11_0_flush_gpu_tlb()
919 /* Flush HDP after it is initialized */ in gmc_v11_0_gart_enable()
H A Dsdma_v7_0.c35 #include "hdp/hdp_6_0_0_offset.h"
321 * sdma_v7_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
325 * Emit an hdp flush packet on the requested DMA ring.
H A Dsdma_v6_0.c36 #include "hdp/hdp_6_0_0_offset.h"
319 * sdma_v6_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
323 * Emit an hdp flush packet on the requested DMA ring.
/linux/drivers/pinctrl/stm32/
H A DKconfig62 tristate "STMicroelectronics STM32 Hardware Debug Port (HDP) pin control"
73 It permits the observation of up to 16 signals per HDP line.
H A DMakefile14 obj-$(CONFIG_PINCTRL_STM32_HDP) += pinctrl-stm32-hdp.o
/linux/drivers/net/wireless/quantenna/qtnfmac/pcie/
H A Dpearl_pcie_regs.h7 /* Pearl PCIe HDP registers */
96 /* PCIe HDP interrupt status definition */
/linux/drivers/gpu/drm/radeon/
H A Dcik_sdma.c161 * cik_sdma_hdp_flush_ring_emit - emit an hdp flush on the DMA ring
166 * Emit an hdp flush packet on the requested DMA ring.
212 /* flush HDP */ in cik_sdma_fence_ring_emit()
983 /* flush HDP */ in cik_dma_vm_flush()
H A Devergreen_dma.c52 /* flush HDP */ in evergreen_dma_fence_ring_emit()
H A Dradeon_ib.c112 * @hdp_flush: Whether or not to perform an HDP cache flush
H A Dsi_dma.c198 /* flush hdp cache */ in si_dma_vm_flush()
H A Dni_dma.c455 /* flush hdp cache */ in cayman_dma_vm_flush()
H A Dni.c978 /* Initialize HDP */ in cayman_gpu_init()
1241 /* flush hdp cache */ in cayman_pcie_gart_tlb_flush()
2644 block = "HDP"; in cayman_vm_decode_fault()
2669 /* flush hdp cache */ in cayman_vm_flush()
/linux/include/dt-bindings/clock/
H A Dstm32mp13-clks.h72 #define HDP 44 macro
H A Dstm32mp1-clks.h68 #define HDP 55 macro
/linux/drivers/clk/stm32/
H A Dclk-stm32mp13.c747 static struct clk_stm32_gate hdp = { variable
749 .hw.init = CLK_HW_INIT("hdp", "pclk3", &clk_stm32_gate_ops, 0),
1362 STM32_GATE_CFG(HDP, hdp, SECF_NONE),

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