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/linux/include/linux/
H A Dsysfb.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
7 * Copyright (c) 2012-2013 David Herrmann <dh.herrmann@gmail.com>
20 M_I17, /* 17-Inch iMac */
21 M_I20, /* 20-Inch iMac */
22 M_I20_SR, /* 20-Inch iMac (Santa Rosa) */
23 M_I24, /* 24-Inc
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/linux/drivers/net/dsa/sja1105/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
11 This is the driver for the NXP SJA1105 (5-port) and SJA1110 (10-port)
15 - SJA1105E (Gen. 1, No TT-Ethernet)
16 - SJA1105T (Gen. 1, TT-Ethernet)
17 - SJA1105P (Gen. 2, No SGMII, No TT-Ethernet)
18 - SJA1105Q (Gen. 2, No SGMII, TT-Ethernet)
19 - SJA1105R (Gen. 2, SGMII, No TT-Ethernet)
20 - SJA1105S (Gen. 2, SGMII, TT-Ethernet)
21 - SJA1110A (Gen. 3, SGMII, TT-Ethernet, 100base-TX PHY, 10 ports)
22 - SJA1110B (Gen. 3, SGMII, TT-Ethernet, 100base-TX PHY, 9 ports)
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/linux/sound/hda/codecs/
H A Danalog.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (c) 2005-2007 Takashi Iwai <tiwai@suse.de>
31 struct hda_gen_spec gen; member
53 ((spec)->beep_amp = HDA_COMPOSE_AMP_VAL(nid, 1, idx, dir)) /* mono */
61 struct ad198x_spec *spec = codec->spec; in create_beep_ctls()
64 if (!spec->beep_am in create_beep_ctls()
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H A Dvia.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * (C) 2006-2009 VIA Technology, Inc.
8 * (C) 2006-2008 Takashi Iwai <tiwai@suse.de>
13 /* 2006-03-03 Lydia Wang Create the basic patch to support VT1708 codec */
14 /* 2006-03-14 Lydia Wang Modify hard code for some pin widget nid */
15 /* 2006-08-02 Lydia Wang Add support to VT1709 codec */
16 /* 2006-09-08 Lydia Wang Fix internal loopback recording source select bug */
17 /* 2007-09-12 Lydia Wang Add EAPD enable during driver initialization */
18 /* 2007-09-17 Lydia Wang Add VT1708B codec support */
19 /* 2007-11-14 Lydia Wang Add VT1708A codec HP and CD pin connect config */
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/linux/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_du_drv.c1 // SPDX-License-Identifier: GPL-2.0+
3 * R-Car Display Unit DRM driver
5 * Copyright (C) 2013-2015 Renesas Electronics Corporation
11 #include <linux/dma-mapping.h>
32 /* -----------------------------------------------------------------------------
37 .gen = 2,
61 .gen = 2,
84 .gen = 2,
112 .gen = 3,
143 .gen = 3,
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H A Drcar_du_group.c1 // SPDX-License-Identifier: GPL-2.0+
3 * R-Car Display Unit Channels Pair
5 * Copyright (C) 2013-2015 Renesas Electronics Corporation
11 * The R8A7779 DU is split in per-CRTC resources (scan-out engine, blending
12 * unit, timings generator, ...) and device-global resources (start/stop
19 * modeled as a single device with three CRTCs, two sets of "semi-global"
20 * resources, and a few device-global resources.
23 * counterpart in the DU documentation, that models those semi-global resources.
35 return rcar_du_read(rgrp->dev, rgrp->mmio_offset + reg); in rcar_du_group_read()
40 rcar_du_write(rgrp->dev, rgrp->mmio_offset + reg, data); in rcar_du_group_write()
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/linux/drivers/gpu/drm/vc4/
H A Dvc4_hvs.c1 // SPDX-License-Identifier: GPL-2.0-only
31 #include <soc/bcm2835/raspberrypi-firmware.h>
206 struct drm_device *drm = &hvs->vc4->base; in vc4_hvs_dump_state()
207 struct drm_printer p = drm_info_printer(&hvs->pdev->dev); in vc4_hvs_dump_state()
213 drm_print_regset32(&p, &hvs->regset); in vc4_hvs_dump_state()
219 readl((u32 __iomem *)hvs->dlist + i + 0), in vc4_hvs_dump_state()
220 readl((u32 __iomem *)hvs->dlist + i + 1), in vc4_hvs_dump_state()
221 readl((u32 __iomem *)hvs->dlist + i + 2), in vc4_hvs_dump_state()
222 readl((u32 __iomem *)hvs->dlist + i + 3)); in vc4_hvs_dump_state()
230 struct drm_debugfs_entry *entry = m->private; in vc4_hvs_debugfs_underrun()
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H A Dvc4_kms.c1 // SPDX-License-Identifier: GPL-2.0-only
49 struct drm_device *dev = state->dev; in vc4_get_ctm_state()
54 ret = drm_modeset_lock(&vc4->ctm_state_lock, state->acquire_ctx); in vc4_get_ctm_state()
70 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL); in vc4_ctm_duplicate_state()
74 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); in vc4_ctm_duplicate_state()
76 return &state->base; in vc4_ctm_duplicate_state()
96 drm_atomic_private_obj_fini(&vc4->ctm_manager); in vc4_ctm_obj_fini()
103 drm_modeset_lock_init(&vc4->ctm_state_lock); in vc4_ctm_obj_init()
107 return -ENOMEM; in vc4_ctm_obj_init()
109 drm_atomic_private_obj_init(&vc4->base, &vc4->ctm_manager, &ctm_state->base, in vc4_ctm_obj_init()
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H A Dvc4_drv.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-2015 Broadcom
11 * OpenGL ES 2.0-compatible 3D engine called V3D, and a highly
15 * The 3D engine also has an interface for submitting arbitrary
16 * compute shader-style jobs using the same shader processor as is
27 #include <linux/dma-mapping.h>
41 #include <soc/bcm2835/raspberrypi-firmware.h>
68 int min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8); in vc4_dumb_fixup_args()
70 if (args->pitch < min_pitch) in vc4_dumb_fixup_args()
71 args->pitch = min_pitch; in vc4_dumb_fixup_args()
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/linux/drivers/rapidio/switches/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 tristate "IDT CPS-xx SRIO switches support"
8 Includes support for IDT CPS-16/12/10/8 serial RapidIO switches.
11 tristate "IDT CPS Gen.2 SRIO switch support"
14 Includes support for ITD CPS Gen.2 serial RapidIO switches.
17 tristate "IDT RXS Gen.3 SRIO switch support"
20 Includes support for ITD RXS Gen.3 serial RapidIO switches.
/linux/tools/bpf/bpftool/Documentation/
H A Dbpftool-gen.rst1 .. SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 bpftool-gen
6 --
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/linux/sound/hda/codecs/cirrus/
H A Dcs421x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Cirrus Logic CS421x HD-audio codec
19 struct hda_gen_spec gen; member
45 /* Vendor-specific processing widget */
57 * 1 = digital immediate, analog zero-cross
58 * 2 = digtail & analog soft-ramp
59 * 3 = digital soft-ramp, analog zero-cross
61 #define CS_COEF_ADC_SZC_MASK (3 << 0)
62 #define CS_COEF_ADC_MIC_SZC_MODE (3 << 0) /* SZC setup for mic */
63 #define CS_COEF_ADC_LI_SZC_MODE (3 << 0) /* SZC setup for line-in */
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H A Dcs420x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Cirrus Logic CS420x HD-audio codec
21 struct hda_gen_spec gen; member
52 /* Vendor-specific processing widget */
65 * 1 = digital immediate, analog zero-cross
66 * 2 = digtail & analog soft-ramp
67 * 3 = digital soft-ramp, analog zero-cross
69 #define CS_COEF_ADC_SZC_MASK (3 << 0)
70 #define CS_COEF_ADC_MIC_SZC_MODE (3 << 0) /* SZC setup for mic */
71 #define CS_COEF_ADC_LI_SZC_MODE (3 << 0) /* SZC setup for line-in */
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/linux/drivers/net/vmxnet3/
H A Dvmxnet3_defs.h4 * Copyright (C) 2008-2024, VMware, Inc. All Rights Reserved.
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
23 * Maintained by: pv-drivers@vmware.com
73 #define VMXNET3_REG_ALIGN 8 /* All registers are 8-byte aligned. */
133 * Little Endian layout of bitfields -
135 * Byte 1 : oco gen 13.len.8
137 * Byte 3 : 13...msscof...6
139 * Big Endian layout of bitfields -
142 * Byte 2 : oco gen 13.len.8
143 * Byte 3 : 7.....len.....0
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/linux/drivers/net/ethernet/chelsio/cxgb3/
H A Dsge.c2 * Copyright (c) 2005-2008 Chelsio, Inc. All rights reserved.
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
38 #include <linux/dma-mapping.h>
137 * This structure lives at skb->head and must be allocated by callers.
148 * desc = 1 + (flits - 2) / (WR_FLITS - 1).
157 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
162 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
180 * refill_rspq - replenish an SGE response queue
193 V_RSPQ(q->cntxt_id) | V_CREDITS(credits)); in refill_rspq()
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/linux/drivers/gpu/drm/ast/
H A Dast_drv.h14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
59 /* 1st gen */
62 /* 2nd gen */
66 /* 3rd gen */
67 AST2200 = __AST_CHIP(3, 0),
68 AST2150 = __AST_CHIP(3, 1),
69 /* 4th gen */
73 /* 5th gen */
77 /* 6th gen */
81 /* 7th gen */
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/linux/drivers/phy/st/
H A Dphy-miphy28lp.c1 // SPDX-License-Identifier: GPL-2.0-only
25 #include <dt-bindings/phy/phy.h>
44 #define DIS_LINK_RST BIT(3)
119 #define EQ_BOOST_GAIN BIT(3)
148 #define EN_DIGIT_SIGNAL_CHECK BIT(3)
171 * 0: 30MHz crystal clk - 1: 100MHz ext clk routed through MiPHY1
173 * 1: 30MHz crystal clk - 0: 100MHz ext clk routed through MiPHY1
176 #define MIPHY_OSC_FORCE_EXT BIT(3)
191 #define MIPHY_SATA_BANK_NB 3
233 static char *PHY_TYPE_name[] = { "sata-up", "pcie-up", "", "usb3-up" };
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/linux/sound/hda/codecs/realtek/
H A Drealtek.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 // Realtek HD-audio codec support code
49 if (val != -1) in alc_read_coefex_idx()
66 struct alc_spec *spec = codec->spec;
68 if (!spec->coef0) in __alc_update_coefex_idx()
69 spec->coef in __alc_update_coefex_idx()
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/linux/arch/x86/lib/
H A Dretpoline.S1 /* SPDX-License-Identifier: GPL-2.0 */
9 #include <asm/asm-offsets.h>
10 #include <asm/nospec-branch.h>
63 #define GEN(reg) THUNK reg macro
64 #include <asm/GEN-for-each-reg.h>
65 #undef GEN
70 #define GEN(reg) __EXPORT_THUNK(__x86_indirect_thunk_ ## reg) macro
71 #include <asm/GEN-for-each-reg.h>
72 #undef GEN
93 #define GEN(reg) CALL_THUNK reg macro
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/linux/drivers/base/firmware_loader/builtin/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-y += main.o
4 # Create $(fwdir) from $(CONFIG_EXTRA_FIRMWARE_DIR) -- if it doesn't have a
7 fwdir := $(addprefix $(srctree)/,$(filter-out /%,$(fwdir)))$(filter /%,$(fwdir))
9 firmware := $(addsuffix .gen.o, $(CONFIG_EXTRA_FIRMWARE))
10 obj-y += $(firmware)
12 FWNAME = $(patsubst $(obj)/%.gen.S,%,$@)
13 FWSTR = $(subst $(comma),_,$(subst /,_,$(subst .,_,$(subst -,_,$(FWNAME)))))
15 ASM_ALIGN = $(if $(CONFIG_64BIT),3,2)
33 echo " $(ASM_WORD) _fw_end - _fw_$(FWSTR)_bin"
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/linux/sound/mips/
H A Dhal2.h1 /* SPDX-License-Identifier: GPL-2.0-only */
8 * Copyright (c) 2001, 2002, 2003 Ladislav Michl <ladis@linux-mips.org>
26 #define H2_REV_MINOR_CHIP_M 0x000F /* RO: bits 3:0, minor chip revision */
42 /* 3=Unix Timer */
49 /* 3=AES Out */
56 /* 1=Bresenham Clock Gen 1 */
57 /* 2=Bresenham Clock Gen 2 */
58 /* 3=Bresenham Clock Gen 3 */
120 #define H2I_AESTX_C_CLKID_SHIFT 3 /* Bresenham Clock Gen 1-3 */
122 #define H2I_AESTX_C_DATAT_SHIFT 8 /* 1=mono 2=stereo (3=quad) */
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/linux/drivers/usb/host/
H A Dpci-quirks.c1 // SPDX-License-Identifier: GPL-2.0
4 * Some of it includes work-arounds for PCI hardware and BIOS quirks.
5 * It may need to run early during booting -- before USB would normally
6 * initialize -- to ensure that Linux doesn't use any legacy modes.
22 #include "pci-quirks.h"
23 #include "xhci-ext-caps.h"
43 #define OHCI_HCFS (3 << 6) /* hc functional state */
45 #define OHCI_OCR (1 << 3) /* ownership change request */
129 enum amd_chipset_gen gen; member
146 * amd_chipset_sb_type_init - initialize amd chipset southbridge type
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/linux/drivers/phy/marvell/
H A Dphy-armada38x-comphy.c1 // SPDX-License-Identifier: GPL-2.0
17 #define MAX_A38X_PORTS 3
28 #define COMPHY_STAT1_PLL_RDY_TX BIT(3)
56 { 3, 0, 0 },
60 { 0, 3, 0 },
61 { 0, 0, 3 },
66 struct a38x_comphy *priv = lane->priv; in a38x_set_conf()
69 if (priv->conf) { in a38x_set_conf()
70 conf = readl_relaxed(priv->conf); in a38x_set_conf()
72 conf |= BIT(lane->port); in a38x_set_conf()
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/linux/Documentation/devicetree/bindings/phy/
H A Dnvidia,tegra194-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
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/linux/arch/x86/events/intel/
H A Duncore_snb.c1 // SPDX-License-Identifier: GPL-2.0
162 #define SNB_UNC_GLOBAL_CTL_CORE_ALL ((1 << 4) - 1)
181 #define NHM_UNC_GLOBAL_CTL_EN_PC_ALL ((1ULL << 8) - 1)
190 #define SKL_UNC_GLOBAL_CTL_CORE_ALL ((1 << 5) - 1)
248 DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7");
249 DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15");
250 DEFINE_UNCORE_FORMAT_ATTR(chmask, chmask, "config:8-11");
253 DEFINE_UNCORE_FORMAT_ATTR(cmask5, cmask, "config:24-28");
254 DEFINE_UNCORE_FORMAT_ATTR(cmask8, cmask, "config:24-31");
255 DEFINE_UNCORE_FORMAT_ATTR(threshold, threshold, "config:24-29");
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