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/linux/drivers/usb/dwc3/
H A Dcore.c51 * @dwc: pointer to our context structure
53 static int dwc3_get_dr_mode(struct dwc3 *dwc) in dwc3_get_dr_mode() argument
56 struct device *dev = dwc->dev; in dwc3_get_dr_mode()
59 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) in dwc3_get_dr_mode()
60 dwc->dr_mode = USB_DR_MODE_OTG; in dwc3_get_dr_mode()
62 mode = dwc->dr_mode; in dwc3_get_dr_mode()
63 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); in dwc3_get_dr_mode()
93 if (mode == USB_DR_MODE_OTG && !dwc->edev && in dwc3_get_dr_mode()
95 !device_property_read_bool(dwc->dev, "usb-role-switch")) && in dwc3_get_dr_mode()
100 if (mode != dwc->dr_mode) { in dwc3_get_dr_mode()
[all …]
H A Dgadget.c35 * @dwc: pointer to our context structure
41 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) in dwc3_gadget_set_test_mode() argument
45 reg = dwc3_readl(dwc, DWC3_DCTL); in dwc3_gadget_set_test_mode()
60 dwc3_gadget_dctl_write_safe(dwc, reg); in dwc3_gadget_set_test_mode()
67 * @dwc: pointer to our context structure
72 int dwc3_gadget_get_link_state(struct dwc3 *dwc) in dwc3_gadget_get_link_state() argument
76 reg = dwc3_readl(dwc, DWC3_DSTS); in dwc3_gadget_get_link_state()
83 * @dwc: pointer to our context structure
89 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) in dwc3_gadget_set_link_state() argument
100 reg = dwc3_readl(dwc, DWC3_DSTS); in dwc3_gadget_set_link_state()
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H A Ddebugfs.c283 struct dwc3 *dwc = s->private; in dwc3_host_lsp() local
289 dbc_enabled = !!(dwc->hwparams.hwparams1 & DWC3_GHWPARAMS1_ENDBC); in dwc3_host_lsp()
291 sel = dwc->dbg_lsp_select; in dwc3_host_lsp()
299 dwc3_writel(dwc, DWC3_GDBGLSPMUX, reg); in dwc3_host_lsp()
300 val = dwc3_readl(dwc, DWC3_GDBGLSP); in dwc3_host_lsp()
305 dwc3_writel(dwc, DWC3_GDBGLSPMUX, reg); in dwc3_host_lsp()
306 val = dwc3_readl(dwc, DWC3_GDBGLSP); in dwc3_host_lsp()
313 struct dwc3 *dwc = s->private; in dwc3_gadget_lsp() local
319 dwc3_writel(dwc, DWC3_GDBGLSPMUX, reg); in dwc3_gadget_lsp()
320 reg = dwc3_readl(dwc, DWC3_GDBGLSP); in dwc3_gadget_lsp()
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H A Dhost.c27 * @dwc: Pointer to our controller context structure
29 static void dwc3_power_off_all_roothub_ports(struct dwc3 *dwc) in dwc3_power_off_all_roothub_ports() argument
39 if (dwc->xhci_resources[0].start) { in dwc3_power_off_all_roothub_ports()
40 if (dwc->xhci_resources[0].flags & IORESOURCE_MEM_NONPOSTED) in dwc3_power_off_all_roothub_ports()
41 xhci_regs = ioremap_np(dwc->xhci_resources[0].start, DWC3_XHCI_REGS_END); in dwc3_power_off_all_roothub_ports()
43 xhci_regs = ioremap(dwc->xhci_resources[0].start, DWC3_XHCI_REGS_END); in dwc3_power_off_all_roothub_ports()
45 dev_err(dwc->dev, "Failed to ioremap xhci_regs\n"); in dwc3_power_off_all_roothub_ports()
62 dev_err(dwc->dev, "xhci base reg invalid\n"); in dwc3_power_off_all_roothub_ports()
69 struct dwc3 *dwc; in dwc3_xhci_plat_start() local
75 dwc = dev_get_drvdata(pdev->dev.parent); in dwc3_xhci_plat_start()
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H A Dglue.h26 * @dwc: Reference to dwc3 context structure
35 struct dwc3 *dwc; member
58 * @dwc: Pointer to DWC3 controller context
64 void dwc3_core_remove(struct dwc3 *dwc);
72 int dwc3_runtime_suspend(struct dwc3 *dwc);
73 int dwc3_runtime_resume(struct dwc3 *dwc);
74 int dwc3_runtime_idle(struct dwc3 *dwc);
75 int dwc3_pm_suspend(struct dwc3 *dwc);
76 int dwc3_pm_resume(struct dwc3 *dwc);
77 void dwc3_pm_complete(struct dwc3 *dwc);
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H A Ddwc3-pci.c226 static int dwc3_pci_quirks(struct dwc3_pci *dwc, in dwc3_pci_quirks() argument
229 struct pci_dev *pdev = dwc->pci; in dwc3_pci_quirks()
235 guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid); in dwc3_pci_quirks()
236 dwc->has_dsm_for_pm = true; in dwc3_pci_quirks()
290 dwc->dwc3->id = PLATFORM_DEVID_NONE; in dwc3_pci_quirks()
311 return device_add_software_node(&dwc->dwc3->dev, swnode); in dwc3_pci_quirks()
317 struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work); in dwc3_pci_resume_work() local
318 struct platform_device *dwc3 = dwc->dwc3; in dwc3_pci_resume_work()
333 struct dwc3_pci *dwc; in dwc3_pci_probe() local
346 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); in dwc3_pci_probe()
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H A Ddwc3-haps.c43 struct dwc3_haps *dwc; in dwc3_haps_probe() local
56 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); in dwc3_haps_probe()
57 if (!dwc) in dwc3_haps_probe()
60 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); in dwc3_haps_probe()
61 if (!dwc->dwc3) in dwc3_haps_probe()
75 ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res)); in dwc3_haps_probe()
81 dwc->pci = pci; in dwc3_haps_probe()
82 dwc->dwc3->dev.parent = dev; in dwc3_haps_probe()
84 ret = device_add_software_node(&dwc->dwc3->dev, &dwc3_haps_swnode); in dwc3_haps_probe()
88 ret = platform_device_add(dwc->dwc3); in dwc3_haps_probe()
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H A Ddwc3-qcom.c74 struct dwc3 dwc; member
90 #define to_dwc3_qcom(d) container_of((d), struct dwc3_qcom, dwc)
186 max_speed = usb_get_maximum_speed(qcom->dwc.dev); in dwc3_qcom_interconnect_init()
229 return qcom->dwc.xhci; in dwc3_qcom_is_host()
236 struct dwc3 *dwc = &qcom->dwc; in dwc3_qcom_read_usb2_speed() local
241 hcd = platform_get_drvdata(dwc->xhci); in dwc3_qcom_read_usb2_speed()
406 struct dwc3 *dwc = &qcom->dwc; in qcom_dwc3_resume_irq() local
417 pm_runtime_resume(&dwc->xhci->dev); in qcom_dwc3_resume_irq()
561 static void dwc3_qcom_set_role_notifier(struct dwc3 *dwc, enum usb_role next_role) in dwc3_qcom_set_role_notifier() argument
563 struct dwc3_qcom *qcom = to_dwc3_qcom(dwc); in dwc3_qcom_set_role_notifier()
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H A Dcore.h692 * @dwc: pointer to DWC controller
706 struct dwc3 *dwc; member
729 * @dwc: pointer to DWC controller
754 struct dwc3 *dwc; member
881 * @ctrl: DWC-F
1000 void (*pre_set_role)(struct dwc3 *dwc, enum usb_role role);
1001 void (*pre_run_stop)(struct dwc3 *dwc, bool is_on);
1584 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode, bool ignore_susphy);
1585 void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
1589 (dwc->ip == _ip##_IP)
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H A Ddwc3-apple.c80 * @dwc: Core DWC3 structure
90 struct dwc3 dwc; member
104 #define to_dwc3_apple(d) container_of((d), struct dwc3_apple, dwc)
167 guard(spinlock_irqsave)(&appledwc->dwc.lock); in dwc3_apple_set_ptrcap()
168 dwc3_set_prtcap(&appledwc->dwc, mode, false); in dwc3_apple_set_ptrcap()
179 appledwc->dwc.dev = appledwc->dev; in dwc3_apple_core_probe()
180 probe_data.dwc = &appledwc->dwc; in dwc3_apple_core_probe()
207 ret = dwc3_core_init(&appledwc->dwc); in dwc3_apple_core_init()
236 phy_set_mode(appledwc->dwc.usb2_generic_phy[0], PHY_MODE_USB_HOST); in dwc3_apple_init()
239 phy_set_mode(appledwc->dwc.usb2_generic_phy[0], PHY_MODE_USB_DEVICE); in dwc3_apple_init()
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H A Ddwc3-generic-plat.c25 struct dwc3 dwc; member
36 #define to_dwc3_generic(d) container_of((d), struct dwc3_generic, dwc)
117 dwc3g->dwc.dev = dev; in dwc3_generic_probe()
118 probe_data.dwc = &dwc3g->dwc; in dwc3_generic_probe()
146 struct dwc3 *dwc = platform_get_drvdata(pdev); in dwc3_generic_remove() local
148 dwc3_core_remove(dwc); in dwc3_generic_remove()
153 struct dwc3 *dwc = dev_get_drvdata(dev); in dwc3_generic_suspend() local
154 struct dwc3_generic *dwc3g = to_dwc3_generic(dwc); in dwc3_generic_suspend()
157 ret = dwc3_pm_suspend(dwc); in dwc3_generic_suspend()
168 struct dwc3 *dwc = dev_get_drvdata(dev); in dwc3_generic_resume() local
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/linux/drivers/dma/dw/
H A Dcore.c49 static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc) in dwc_first_active() argument
51 return to_dw_desc(dwc->active_list.next); in dwc_first_active()
57 struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan); in dwc_tx_submit() local
61 spin_lock_irqsave(&dwc->lock, flags); in dwc_tx_submit()
70 list_add_tail(&desc->desc_node, &dwc->queue); in dwc_tx_submit()
71 spin_unlock_irqrestore(&dwc->lock, flags); in dwc_tx_submit()
78 static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc) in dwc_desc_get() argument
80 struct dw_dma *dw = to_dw_dma(dwc->chan.device); in dwc_desc_get()
88 dwc->descs_allocated++; in dwc_desc_get()
90 dma_async_tx_descriptor_init(&desc->txd, &dwc->chan); in dwc_desc_get()
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H A Ddw.c14 static void dw_dma_initialize_chan(struct dw_dma_chan *dwc) in dw_dma_initialize_chan() argument
16 struct dw_dma *dw = to_dw_dma(dwc->chan.device); in dw_dma_initialize_chan()
17 u32 cfghi = is_slave_direction(dwc->direction) ? 0 : DWC_CFGH_FIFO_MODE; in dw_dma_initialize_chan()
18 u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority); in dw_dma_initialize_chan()
19 bool hs_polarity = dwc->dws.hs_polarity; in dw_dma_initialize_chan()
21 cfghi |= DWC_CFGH_DST_PER(dwc->dws.dst_id); in dw_dma_initialize_chan()
22 cfghi |= DWC_CFGH_SRC_PER(dwc->dws.src_id); in dw_dma_initialize_chan()
28 channel_writel(dwc, CFG_LO, cfglo); in dw_dma_initialize_chan()
29 channel_writel(dwc, CFG_HI, cfghi); in dw_dma_initialize_chan()
32 static void dw_dma_suspend_chan(struct dw_dma_chan *dwc, bool drain) in dw_dma_suspend_chan() argument
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H A Didma32.c36 static unsigned int idma32_get_slave_devfn(struct dw_dma_chan *dwc) in idma32_get_slave_devfn() argument
38 struct device *slave = dwc->chan.slave; in idma32_get_slave_devfn()
46 static void idma32_initialize_chan_xbar(struct dw_dma_chan *dwc) in idma32_initialize_chan_xbar() argument
48 struct dw_dma *dw = to_dw_dma(dwc->chan.device); in idma32_initialize_chan_xbar()
58 value |= dwc->chan.chan_id; in idma32_initialize_chan_xbar()
63 value = readl(misc + DMA_CTL_CH(dwc->chan.chan_id)); in idma32_initialize_chan_xbar()
69 switch (dwc->direction) { in idma32_initialize_chan_xbar()
88 writel(value, misc + DMA_CTL_CH(dwc->chan.chan_id)); in idma32_initialize_chan_xbar()
91 value = readl(misc + DMA_XBAR_SEL(dwc->chan.chan_id)); in idma32_initialize_chan_xbar()
95 value |= idma32_get_slave_devfn(dwc); in idma32_initialize_chan_xbar()
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H A Dregs.h298 __dwc_regs(struct dw_dma_chan *dwc) in __dwc_regs() argument
300 return dwc->ch_regs; in __dwc_regs()
303 #define channel_readl(dwc, name) \ argument
304 readl(&(__dwc_regs(dwc)->name))
305 #define channel_writel(dwc, name, val) \ argument
306 writel((val), &(__dwc_regs(dwc)->name))
326 void (*initialize_chan)(struct dw_dma_chan *dwc);
327 void (*suspend_chan)(struct dw_dma_chan *dwc, bool drain);
328 void (*resume_chan)(struct dw_dma_chan *dwc, bool drain);
329 u32 (*prepare_ctllo)(struct dw_dma_chan *dwc);
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/linux/drivers/pwm/
H A Dpwm-dwc-core.c22 #include "pwm-dwc.h"
24 static void __dwc_pwm_set_enable(struct dwc_pwm *dwc, int pwm, int enabled) in __dwc_pwm_set_enable() argument
28 reg = dwc_pwm_readl(dwc, DWC_TIM_CTRL(pwm)); in __dwc_pwm_set_enable()
35 dwc_pwm_writel(dwc, reg, DWC_TIM_CTRL(pwm)); in __dwc_pwm_set_enable()
38 static int __dwc_pwm_configure_timer(struct dwc_pwm *dwc, in __dwc_pwm_configure_timer() argument
52 tmp = DIV_ROUND_CLOSEST_ULL(state->duty_cycle, dwc->clk_ns); in __dwc_pwm_configure_timer()
58 dwc->clk_ns); in __dwc_pwm_configure_timer()
70 __dwc_pwm_set_enable(dwc, pwm->hwpwm, false); in __dwc_pwm_configure_timer()
78 dwc_pwm_writel(dwc, low, DWC_TIM_LD_CNT(pwm->hwpwm)); in __dwc_pwm_configure_timer()
79 dwc_pwm_writel(dwc, high, DWC_TIM_LD_CNT2(pwm->hwpwm)); in __dwc_pwm_configure_timer()
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H A Dpwm-dwc.h64 static inline u32 dwc_pwm_readl(struct dwc_pwm *dwc, u32 offset) in dwc_pwm_readl() argument
66 return readl(dwc->base + offset); in dwc_pwm_readl()
69 static inline void dwc_pwm_writel(struct dwc_pwm *dwc, u32 value, u32 offset) in dwc_pwm_writel() argument
71 writel(value, dwc->base + offset); in dwc_pwm_writel()
/linux/drivers/net/ethernet/synopsys/
H A DMakefile6 obj-$(CONFIG_DWC_XLGMAC) += dwc-xlgmac.o
7 dwc-xlgmac-objs := dwc-xlgmac-net.o dwc-xlgmac-desc.o \
8 dwc-xlgmac-hw.o dwc-xlgmac-common.o \
9 dwc-xlgmac-ethtool.o
11 dwc-xlgmac-$(CONFIG_DWC_XLGMAC_PCI) += dwc-xlgmac-pci.o
/linux/Documentation/devicetree/bindings/ata/
H A Dsnps,dwc-ahci.yaml4 $id: http://devicetree.org/schemas/ata/snps,dwc-ahci.yaml#
7 title: Synopsys DWC AHCI SATA controller
13 This document defines device tree bindings for the generic Synopsys DWC
20 - snps,dwc-ahci
26 - $ref: snps,dwc-ahci-common.yaml#
32 const: snps,dwc-ahci
42 $ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port
59 compatible = "snps,dwc-ahci";
H A Dsnps,dwc-ahci-common.yaml4 $id: http://devicetree.org/schemas/ata/snps,dwc-ahci-common.yaml#
7 title: Synopsys DWC AHCI SATA controller properties
13 This document defines device tree schema for the generic Synopsys DWC
30 Basic DWC AHCI SATA clock sources like application AXI/AHB BIU clock,
61 normally supported by the DWC AHCI SATA controller.
83 $ref: '#/$defs/dwc-ahci-port'
88 dwc-ahci-port:
H A Deswin,eic7700-ahci.yaml14 AHCI SATA controller embedded into the EIC7700 SoC is based on the DWC AHCI
25 - $ref: snps,dwc-ahci-common.yaml#
31 - const: snps,dwc-ahci
68 compatible = "eswin,eic7700-ahci", "snps,dwc-ahci";
/linux/drivers/ufs/host/
H A DMakefile3 obj-$(CONFIG_SCSI_UFS_DWC_TC_PCI) += tc-dwc-g210-pci.o ufshcd-dwc.o tc-dwc-g210.o
4 obj-$(CONFIG_SCSI_UFS_DWC_TC_PLATFORM) += tc-dwc-g210-pltfrm.o ufshcd-dwc.o tc-dwc-g210.o
16 obj-$(CONFIG_SCSI_UFS_AMD_VERSAL2) += ufs-amd-versal2.o ufshcd-dwc.o
H A Dtc-dwc-g210-pltfrm.c18 #include "ufshcd-dwc.h"
19 #include "tc-dwc-g210.h"
22 * UFS DWC specific variant operations
25 .name = "tc-dwc-g210-pltfm",
31 .name = "tc-dwc-g210-pltfm",
91 .name = "tc-dwc-g210-pltfm",
99 MODULE_ALIAS("platform:tc-dwc-g210-pltfm");
/linux/Documentation/devicetree/bindings/net/
H A Dsnps,dwc-qos-ethernet.txt1 * Synopsys DWC Ethernet QoS IP version 4.10 driver (GMAC)
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
72 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10":
78 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10":
83 - "snps,dwc-qos-ethernet-4.10" (deprecated):
97 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10":
99 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10":
[all …]
/linux/Documentation/devicetree/bindings/ufs/
H A Dsnps,tc-dwc-g210.yaml4 $id: http://devicetree.org/schemas/ufs/snps,tc-dwc-g210.yaml#
18 - snps,dwc-ufshcd-1.40a
31 - const: snps,dwc-ufshcd-1.40a
47 "snps,dwc-ufshcd-1.40a",

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