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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dnvidia,tegra124-dfll.txt1 NVIDIA Tegra124 DFLL FCPU clocksource
6 The DFLL IP block on Tegra is a root clocksource designed for clocking
14 - "nvidia,tegra124-dfll": for Tegra124
15 - "nvidia,tegra210-dfll": for Tegra210
17 - registers for the DFLL control logic.
21 - interrupts: Should contain the DFLL block interrupt.
25 - soc: Clock source for the DFLL control logic.
31 - dvco: Reset control for the DFLL DVCO.
34 - vdd-cpu-supply: Regulator for the CPU voltage rail that the DFLL
39 - nvidia,sample-rate: Sample rate of the DFLL control loop.
[all …]
/freebsd/sys/contrib/device-tree/Bindings/cpufreq/
H A Dnvidia,tegra124-cpufreq.txt14 - dfll: Fast DFLL clocksource that also automatically scales CPU voltage.
34 <&dfll>;
35 clock-names = "cpu_g", "pll_x", "pll_p", "dfll";
/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_cpufreq.c373 rv = clk_get_by_ofw_name(parent_dev, 0, "dfll", &sc->clk_dfll); in get_fdt_resources()
378 device_printf(sc->dev, "Cannot get 'dfll' clock\n"); in get_fdt_resources()
/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra124.dtsi981 dfll: clock@70110000 { label
982 compatible = "nvidia,tegra124-dfll";
983 reg = <0 0x70110000 0 0x100>, /* DFLL control */
1239 <&dfll>;
1240 clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
H A Dtegra124-nyan.dtsi531 /* CPU DFLL clock */
H A Dtegra124-jetson-tk1.dts1836 /* CPU DFLL clock */
H A Dtegra124-apalis.dtsi1946 /* CPU DFLL clock */
H A Dtegra124-apalis-v1.2.dtsi1954 /* CPU DFLL clock */
/freebsd/sys/arm/nvidia/tegra124/
H A Dtegra124_cpufreq.c456 rv = clk_get_by_ofw_name(parent_dev, 0, "dfll", &sc->clk_dfll); in get_fdt_resources()
460 device_printf(sc->dev, "Cannot get 'dfll' clock\n"); in get_fdt_resources()
H A Dtegra124_clk_pll.c139 DFLLCPU: DFLL clock source for the fast CPU cluster
/freebsd/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra210.dtsi1372 dfll: clock@70110000 { label
1373 compatible = "nvidia,tegra210-dfll";
1374 reg = <0 0x70110000 0 0x100>, /* DFLL control */
1385 reset-names = "dvco", "dfll";
1974 <&dfll>;
1975 clock-names = "cpu_g", "pll_x", "pll_p", "dfll";