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/linux/arch/m68k/ifpsp060/
H A Dpfpsp.sa1 dc.l $60ff0000,$17400000,$60ff0000,$15f40000
2 dc.l $60ff0000,$02b60000,$60ff0000,$04700000
3 dc.l $60ff0000,$1b100000,$60ff0000,$19aa0000
4 dc.l $60ff0000,$1b5a0000,$60ff0000,$062e0000
5 dc.l $60ff0000,$102c0000,$51fc51fc,$51fc51fc
6 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
7 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
8 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
9 dc.l $2f00203a,$ff2c487b,$0930ffff,$fef8202f
10 dc.l $00044e74,$00042f00,$203afef2,$487b0930
[all …]
H A Dfplsp.sa1 dc.l $60ff0000,$238e0000,$60ff0000,$24200000
2 dc.l $60ff0000,$24b60000,$60ff0000,$11060000
3 dc.l $60ff0000,$11980000,$60ff0000,$122e0000
4 dc.l $60ff0000,$0f160000,$60ff0000,$0fa80000
5 dc.l $60ff0000,$103e0000,$60ff0000,$12ae0000
6 dc.l $60ff0000,$13400000,$60ff0000,$13d60000
7 dc.l $60ff0000,$05ae0000,$60ff0000,$06400000
8 dc.l $60ff0000,$06d60000,$60ff0000,$213e0000
9 dc.l $60ff0000,$21d00000,$60ff0000,$22660000
10 dc.l $60ff0000,$16160000,$60ff0000,$16a80000
[all …]
H A Ditest.sa1 dc.l $60ff0000,$005c5465,$7374696e,$67203638
2 dc.l $30363020,$49535020,$73746172,$7465643a
3 dc.l $0a007061,$73736564,$0a002066,$61696c65
4 dc.l $640a0000,$4a80660e,$487affe8,$61ff0000
5 dc.l $4f9a588f,$4e752f01,$61ff0000,$4fa4588f
6 dc.l $487affd8,$61ff0000,$4f82588f,$4e754e56
7 dc.l $ff6048e7,$3f3c487a,$ff9e61ff,$00004f6c
8 dc.l $588f42ae,$ff78487b,$01700000,$00ea61ff
9 dc.l $00004f58,$588f61ff,$000000f0,$61ffffff
10 dc.l $ffa642ae,$ff78487b,$01700000,$0af661ff
[all …]
H A Dftest.sa1 dc.l $60ff0000,$00d40000,$60ff0000,$016c0000
2 dc.l $60ff0000,$01a80000,$54657374,$696e6720
3 dc.l $36383036,$30204650,$53502073,$74617274
4 dc.l $65643a0a,$00546573,$74696e67,$20363830
5 dc.l $36302046,$50535020,$756e696d,$706c656d
6 dc.l $656e7465,$6420696e,$73747275,$6374696f
7 dc.l $6e207374,$61727465,$643a0a00,$54657374
8 dc.l $696e6720,$36383036,$30204650,$53502065
9 dc.l $78636570,$74696f6e,$20656e61,$626c6564
10 dc.l $20737461,$72746564,$3a0a0070,$61737365
[all …]
H A Dilsp.sa1 dc.l $60ff0000,$01fe0000,$60ff0000,$02080000
2 dc.l $60ff0000,$04900000,$60ff0000,$04080000
3 dc.l $60ff0000,$051e0000,$60ff0000,$053c0000
4 dc.l $60ff0000,$055a0000,$60ff0000,$05740000
5 dc.l $60ff0000,$05940000,$60ff0000,$05b40000
6 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
7 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
8 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
9 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
10 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_hwseq.h31 void dcn20_log_color_state(struct dc *dc,
38 struct dc *dc,
41 struct dc *dc,
43 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);
44 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);
45 bool dcn20_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
47 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
49 void dcn20_program_output_csc(struct dc *dc,
57 void dcn20_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);
59 struct dc *dc,
[all …]
H A Ddcn20_hwseq.c74 void dcn20_log_color_state(struct dc *dc, in dcn20_log_color_state() argument
77 struct dc_context *dc_ctx = dc->ctx; in dcn20_log_color_state()
78 struct resource_pool *pool = dc->res_pool; in dcn20_log_color_state()
150 dc->caps.color.dpp.input_lut_shared, in dcn20_log_color_state()
151 dc->caps.color.dpp.icsc, in dcn20_log_color_state()
152 dc->caps.color.dpp.dgam_ram, in dcn20_log_color_state()
153 dc->caps.color.dpp.dgam_rom_caps.srgb, in dcn20_log_color_state()
154 dc->caps.color.dpp.dgam_rom_caps.bt2020, in dcn20_log_color_state()
155 dc->caps.color.dpp.dgam_rom_caps.gamma2_2, in dcn20_log_color_state()
156 dc->caps.color.dpp.dgam_rom_caps.pq, in dcn20_log_color_state()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc.c29 #include "dc.h"
92 dc->ctx
95 dc->ctx->logger
102 * DC is the OS-agnostic component of the amdgpu DC driver.
104 * DC maintains and validates a set of structs representing the state of the
107 * Main DC HW structs:
109 * struct dc - The central struct. One per driver. Created on driver load,
113 * Used as a backpointer by most other structs in dc.
126 * Main dc state structs:
129 * these structs in dc->current_state representing the currently programmed state.
[all …]
H A Ddc_vm_helper.c27 #include "dc.h"
37 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config) in dc_setup_system_context() argument
42 if (dc->hwss.init_sys_ctx) { in dc_setup_system_context()
43 num_vmids = dc->hwss.init_sys_ctx(dc->hwseq, dc, pa_config); in dc_setup_system_context()
48 memcpy(&dc->vm_pa_config, pa_config, sizeof(struct dc_phy_addr_space_config)); in dc_setup_system_context()
49 dc->vm_pa_config.valid = true; in dc_setup_system_context()
50 dc->dml2_options.gpuvm_enable = true; in dc_setup_system_context()
51 dc_z10_save_init(dc); in dc_setup_system_context()
57 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid) in dc_setup_vm_context() argument
59 dc->hwss.init_vm_ctx(dc->hwseq, dc, va_config, vmid); in dc_setup_vm_context()
[all …]
/linux/drivers/tty/
H A Dnozomi.c315 struct nozomi *dc; member
463 static void nozomi_setup_memory(struct nozomi *dc) in nozomi_setup_memory() argument
465 void __iomem *offset = dc->base_addr + dc->config_table.dl_start; in nozomi_setup_memory()
472 dc->port[PORT_MDM].dl_addr[CH_A] = offset; in nozomi_setup_memory()
473 dc->port[PORT_MDM].dl_addr[CH_B] = in nozomi_setup_memory()
474 (offset += dc->config_table.dl_mdm_len1); in nozomi_setup_memory()
475 dc->port[PORT_MDM].dl_size[CH_A] = in nozomi_setup_memory()
476 dc->config_table.dl_mdm_len1 - buff_offset; in nozomi_setup_memory()
477 dc->port[PORT_MDM].dl_size[CH_B] = in nozomi_setup_memory()
478 dc->config_table.dl_mdm_len2 - buff_offset; in nozomi_setup_memory()
[all …]
/linux/drivers/md/
H A Ddm-delay.c59 struct delay_c *dc = timer_container_of(dc, t, delay_timer); in handle_delayed_timer() local
61 queue_work(dc->kdelayd_wq, &dc->flush_expired_bios); in handle_delayed_timer()
64 static void queue_timeout(struct delay_c *dc, unsigned long expires) in queue_timeout() argument
66 timer_reduce(&dc->delay_timer, expires); in queue_timeout()
69 static inline bool delay_is_fast(struct delay_c *dc) in delay_is_fast() argument
71 return !!dc->worker; in delay_is_fast()
86 static void flush_delayed_bios(struct delay_c *dc, bool flush_all) in flush_delayed_bios() argument
95 mutex_lock(&dc->process_bios_lock); in flush_delayed_bios()
96 spin_lock(&dc->delayed_bios_lock); in flush_delayed_bios()
97 list_replace_init(&dc->delayed_bios, &local_list); in flush_delayed_bios()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/
H A Dhw_sequencer_private.h76 void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
77 void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
78 void (*init_pipes)(struct dc *dc, struct dc_state *context);
79 void (*reset_hw_ctx_wrap)(struct dc *dc, struct dc_state *context);
80 void (*plane_atomic_disconnect)(struct dc *dc,
83 void (*update_mpcc)(struct dc *dc, struct pipe_ctx *pipe_ctx);
84 bool (*set_input_transfer_func)(struct dc *dc,
87 bool (*set_output_transfer_func)(struct dc *dc,
90 void (*power_down)(struct dc *dc);
93 bool (*enable_display_power_gating)(struct dc *dc,
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
H A Ddcn32_hwseq.h31 struct dc;
44 bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable);
46 void dcn32_cab_for_ss_control(struct dc *dc, bool enable);
48 void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context);
53 bool dcn32_set_input_transfer_func(struct dc *dc,
60 bool dcn32_set_output_transfer_func(struct dc *dc,
64 void dcn32_init_hw(struct dc *dc);
66 void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context);
68 void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context);
70 void dcn32_update_force_pstate(struct dc *dc, struct dc_state *context);
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn31/
H A Ddcn31_hwseq.c63 dc->ctx->logger
70 static void enable_memory_low_power(struct dc *dc) in enable_memory_low_power() argument
72 struct dce_hwseq *hws = dc->hwseq; in enable_memory_low_power()
75 if (dc->debug.enable_mem_low_power.bits.dmcu) { in enable_memory_low_power()
77 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) { in enable_memory_low_power()
83 if (dc->debug.enable_mem_low_power.bits.optc) { in enable_memory_low_power()
88 if (dc->debug.enable_mem_low_power.bits.vga) { in enable_memory_low_power()
93 if (dc->debug.enable_mem_low_power.bits.mpc && in enable_memory_low_power()
94 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode) in enable_memory_low_power()
95 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc); in enable_memory_low_power()
[all …]
/linux/drivers/md/bcache/
H A Dwriteback.c30 static uint64_t __calc_target_rate(struct cached_dev *dc) in __calc_target_rate() argument
32 struct cache_set *c = dc->disk.c; in __calc_target_rate()
48 div64_u64(bdev_nr_sectors(dc->bdev) << WRITEBACK_SHARE_SHIFT, in __calc_target_rate()
52 div_u64(cache_sectors * dc->writeback_percent, 100); in __calc_target_rate()
61 static void __update_writeback_rate(struct cached_dev *dc) in __update_writeback_rate() argument
83 int64_t target = __calc_target_rate(dc); in __update_writeback_rate()
84 int64_t dirty = bcache_dev_sectors_dirty(&dc->disk); in __update_writeback_rate()
87 div_s64(error, dc->writeback_rate_p_term_inverse); in __update_writeback_rate()
101 struct cache_set *c = dc->disk.c; in __update_writeback_rate()
105 if (dc->writeback_consider_fragment && in __update_writeback_rate()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
H A Ddcn35_hwseq.c76 static void enable_memory_low_power(struct dc *dc)
78 struct dce_hwseq *hws = dc->hwseq;
81 if (dc->debug.enable_mem_low_power.bits.dmcu) {
83 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) {
89 if (dc->debug.enable_mem_low_power.bits.optc) {
94 if (dc->debug.enable_mem_low_power.bits.vga) {
99 if (dc->debug.enable_mem_low_power.bits.mpc &&
100 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode)
101 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc);
103 …if (dc->debug.enable_mem_low_power.bits.vpg && dc->res_pool->stream_enc[0]->vpg->funcs->vpg_powerd…
[all …]
H A Ddcn35_hwseq.h32 struct dc;
34 void dcn35_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
48 void dcn35_init_hw(struct dc *dc);
54 void dcn35_power_down_on_boot(struct dc *dc);
56 bool dcn35_apply_idle_power_optimizations(struct dc *dc, bool enable);
58 void dcn35_z10_restore(const struct dc *dc);
60 void dcn35_init_pipes(struct dc *dc, struct dc_state *context);
61 void dcn35_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx);
62 void dcn35_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx,
64 void dcn35_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
H A Ddcn30_hwseq.c65 dc->ctx->logger
72 void dcn30_log_color_state(struct dc *dc, in dcn30_log_color_state() argument
75 struct dc_context *dc_ctx = dc->ctx; in dcn30_log_color_state()
76 struct resource_pool *pool = dc->res_pool; in dcn30_log_color_state()
157 dc->caps.color.dpp.input_lut_shared, in dcn30_log_color_state()
158 dc->caps.color.dpp.icsc, in dcn30_log_color_state()
159 dc->caps.color.dpp.dgam_ram, in dcn30_log_color_state()
160 dc->caps.color.dpp.dgam_rom_caps.srgb, in dcn30_log_color_state()
161 dc->caps.color.dpp.dgam_rom_caps.bt2020, in dcn30_log_color_state()
162 dc->caps.color.dpp.dgam_rom_caps.gamma2_2, in dcn30_log_color_state()
[all …]
/linux/drivers/scsi/esas2r/
H A Desas2r_disc.c291 struct esas2r_disc_context *dc = &a->disc_ctx; in esas2r_disc_queue_event() local
298 dc->disc_evt |= disc_evt; in esas2r_disc_queue_event()
314 struct esas2r_disc_context *dc = &a->disc_ctx; in esas2r_disc_start_port() local
326 if (dc->disc_evt) { in esas2r_disc_start_port()
352 esas2r_trace("disc_evt: %d", dc->disc_evt); in esas2r_disc_start_port()
354 dc->flags = 0; in esas2r_disc_start_port()
357 dc->flags |= DCF_POLLED; in esas2r_disc_start_port()
359 rq->interrupt_cx = dc; in esas2r_disc_start_port()
363 if (dc->disc_evt & DCDE_DEV_SCAN) { in esas2r_disc_start_port()
364 dc->disc_evt &= ~DCDE_DEV_SCAN; in esas2r_disc_start_port()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/
H A Ddcn401_resource.c6 #include "dc.h"
761 ctx->dc->caps.extended_aux_timeout_support); in dcn401_aux_engine_create()
1296 static unsigned int dcn401_calc_num_avail_chans_for_mall(struct dc *dc, unsigned int num_chans) in dcn401_calc_num_avail_chans_for_mall() argument
1310 if (ASICREV_IS_GC_12_0_0_A0(dc->ctx->asic_id.hw_internal_rev)) { in dcn401_calc_num_avail_chans_for_mall()
1312 } else if (ASICREV_IS_GC_12_0_1_A0(dc->ctx->asic_id.hw_internal_rev)) { in dcn401_calc_num_avail_chans_for_mall()
1499 struct dc *dc = pool->base.oem_device->ctx->dc; in dcn401_resource_destruct() local
1501 dc->link_srv->destroy_ddc_service(&pool->base.oem_device); in dcn401_resource_destruct()
1516 dm_error("DC: failed to create dwbc401!\n"); in dcn401_dwbc_create()
1547 dm_error("DC: failed to create mcif_wb30!\n"); in dcn401_mmhubbub_create()
1586 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc); in dcn401_dsc_create()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/
H A Ddce110_hwseq.c27 #include "dc.h"
90 struct dc_context *ctx = dc->ctx
207 struct dc *dc, in dce110_enable_display_power_gating() argument
214 struct dc_context *ctx = dc->ctx; in dce110_enable_display_power_gating()
215 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; in dce110_enable_display_power_gating()
283 dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, in dce110_set_input_transfer_func() argument
606 dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, in dce110_set_output_transfer_func() argument
668 const struct dc *dc = link->dc; in dce110_enable_stream() local
676 dc->hwss.update_info_frame(pipe_ctx); in dce110_enable_stream()
740 hpd = ctx->dc->link_srv->get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service); in dce110_edp_wait_for_hpd_ready()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc.h458 struct dc;
463 bool (*get_dcc_compression_cap)(const struct dc *dc,
466 bool (*get_subvp_en)(struct dc *dc, struct dc_state *context);
479 /* Structure to hold configuration flags set by dm at dc creation. */
592 * default, DC favors MPC_SPLIT_DYNAMIC.
596 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the
603 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not
609 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to
611 * user connects to a second display, DC will avoid pipe split.
644 * struct dc_clocks - DC pipe clocks
[all …]
/linux/drivers/clk/mvebu/
H A Ddove-divider.c51 static unsigned int dove_get_divider(struct dove_clk *dc) in dove_get_divider() argument
56 val = readl_relaxed(dc->base + DIV_CTRL0); in dove_get_divider()
57 val >>= dc->div_bit_start; in dove_get_divider()
59 divider = val & ~(~0 << dc->div_bit_size); in dove_get_divider()
61 if (dc->divider_table) in dove_get_divider()
62 divider = dc->divider_table[divider]; in dove_get_divider()
67 static int dove_calc_divider(const struct dove_clk *dc, unsigned long rate, in dove_calc_divider() argument
74 if (dc->divider_table) { in dove_calc_divider()
77 for (i = 0; dc->divider_table[i]; i++) in dove_calc_divider()
78 if (divider == dc->divider_table[i]) { in dove_calc_divider()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn321/
H A Ddcn321_fpu.c309 * override_max_clk_values - Overwrite the max clock frequencies with the max DC mode timings
398 //Overwrite max frequencies with max DC mode frequencies for DC mode systems in build_synthetic_soc_states()
499 // Insert entry with all max dc limits without bandwitch matching in build_synthetic_soc_states()
602 * -with passed few options from dc->config
604 * -with passed latency values (passed in ns units) in dc-> bb override for debugging purposes
610 void dcn321_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) in dcn321_update_bw_bounding_box_fpu() argument
613 /* Overrides from dc->config options */ in dcn321_update_bw_bounding_box_fpu()
614 dcn3_21_ip.clamp_min_dcfclk = dc->config.clamp_min_dcfclk; in dcn321_update_bw_bounding_box_fpu()
616 /* Override from passed dc->bb_overrides if available*/ in dcn321_update_bw_bounding_box_fpu()
617 if ((int)(dcn3_21_soc.sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns in dcn321_update_bw_bounding_box_fpu()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource_helpers.c40 struct dc *dc, in dcn32_helper_calculate_mall_bytes_for_cursor() argument
85 * @dc: current dc state
86 * @context: new dc state
91 struct dc *dc, in dcn32_helper_calculate_num_ways_for_subvp() argument
95 if (dc->debug.force_subvp_num_ways) { in dcn32_helper_calculate_num_ways_for_subvp()
96 return dc->debug.force_subvp_num_ways; in dcn32_helper_calculate_num_ways_for_subvp()
97 } else if (dc->res_pool->funcs->calculate_mall_ways_from_bytes) { in dcn32_helper_calculate_num_ways_for_subvp()
98 …return dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, context->bw_ctx.bw.dcn.mall_subvp_s… in dcn32_helper_calculate_num_ways_for_subvp()
107 void dcn32_merge_pipes_for_subvp(struct dc *dc, in dcn32_merge_pipes_for_subvp() argument
113 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_merge_pipes_for_subvp()
[all …]

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