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/linux/include/dt-bindings/clock/
H A Dtegra186-clock.h376 /** @brief output branch of PLL_C for ISP, controlled by gate CLK_ENB_PLLC_OUT_ISP */
378 /** @brief output branch of PLL_C for VI, controlled by gate CLK_ENB_PLLC_OUT_VE */
380 /** @brief output branch of PLL_C for AON domain, controlled by gate CLK_ENB_PLLC_OUT_AON */
384 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */
386 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */
388 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDF_IN */
398 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI1 */
400 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ISP */
402 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI */
404 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 */
[all …]
H A Dtegra234-clock.h12 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON */
18 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */
22 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */
24 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */
26 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB */
28 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN1 */
32 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN2 */
38 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */
40 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */
42 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */
[all …]
/linux/Documentation/devicetree/bindings/leds/
H A Dleds-bcm6328.yaml16 controller), which can either be controlled by software (exporting the 74x164
20 Some of these Serial LEDs are hardware controlled (e.g. ethernet LEDs) and
22 controlled, so the only chance to keep them working is by using this driver.
25 should be controlled by a hardware signal instead of the MODE register value,
30 controlled you are still able to make it blink or light it up if it isn't,
32 reason, hardware controlled LEDs aren't registered as LED class devices.
81 brcm,hardware-controlled:
83 description: Makes this LED hardware controlled.
149 brcm,hardware-controlled;
154 brcm,hardware-controlled;
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H A Dleds-lm3532.txt53 - reg : Indicates control bank the LED string is controlled by
55 - ti,led-mode : Defines if the LED strings are manually controlled or
56 if the LED strings are controlled by the ALS.
57 0x00 - LED strings are I2C controlled via full scale
59 0x01 - LED strings are ALS controlled
H A Dleds-lm3697.txt21 - reg : 0 - LED is Controlled by bank A
22 1 - LED is Controlled by bank B
39 HVLED string 1 and 3 are controlled by control bank A and HVLED 2 string is
40 controlled by control bank B.
/linux/drivers/pinctrl/nomadik/
H A Dpinctrl-ab8500.c393 ALTERNATE_FUNCTIONS(1, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO1, altA controlled by bit 0 */
394 ALTERNATE_FUNCTIONS(2, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO2, altA controlled by bit 1 */
395 ALTERNATE_FUNCTIONS(3, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO3, altA controlled by bit 2*/
396 ALTERNATE_FUNCTIONS(4, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO4, altA controlled by bit 3*/
399 ALTERNATE_FUNCTIONS(6, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO6, altA controlled by bit 5*/
400 ALTERNATE_FUNCTIONS(7, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO7, altA controlled by bit 6*/
401 ALTERNATE_FUNCTIONS(8, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO8, altA controlled by bit 7*/
403 ALTERNATE_FUNCTIONS(9, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO9, altA controlled by bit 0*/
404 …ALTERNATE_FUNCTIONS(10, 1, 0, UNUSED, 0, 1, 0), /* GPIO10, altA and altB controlled by bi…
405 …ALTERNATE_FUNCTIONS(11, 2, 1, UNUSED, 0, 1, 0), /* GPIO11, altA and altB controlled by bi…
[all …]
H A Dpinctrl-ab8505.c276 ALTERNATE_FUNCTIONS(1, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO1, altA controlled by bit 0 */
277 ALTERNATE_FUNCTIONS(2, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO2, altA controlled by bit 1 */
278 ALTERNATE_FUNCTIONS(3, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO3, altA controlled by bit 2*/
286 …ALTERNATE_FUNCTIONS(10, 1, 0, UNUSED, 1, 0, 0), /* GPIO10, altA and altB controlled by b…
287 ALTERNATE_FUNCTIONS(11, 2, 1, UNUSED, 0, 0, 0), /* GPIO11, altA controlled by bit 2 */
289 …ALTERNATE_FUNCTIONS(13, 4, 3, 4, 1, 0, 2), /* GPIO13, altA altB and altC controlled
290 ALTERNATE_FUNCTIONS(14, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO14, altA controlled by bit 5 */
298 ALTERNATE_FUNCTIONS(17, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO17, altA controlled by bit 0 */
299 ALTERNATE_FUNCTIONS(18, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO18, altA controlled by bit 0 */
300 ALTERNATE_FUNCTIONS(19, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO19, altA controlled by bit 0 */
[all …]
/linux/drivers/leds/trigger/
H A DKconfig15 This allows LEDs to be controlled by a programmable timer
26 controlled via sysfs. It's useful to notify the user on
39 This allows LEDs to be controlled by disk activity.
46 This allows LEDs to be controlled by MTD activity.
52 This allows LEDs to be controlled by a CPU load average.
60 This allows LEDs to be controlled as a backlight device: they
69 This allows LEDs to be controlled by active CPUs. This shows
78 This allows LEDs to be controlled by an immediate CPU usage.
87 This allows LEDs to be controlled by gpio events. It's good
112 This allows LEDs to be controlled as a camera flash/torch device.
[all …]
/linux/arch/mips/boot/dts/brcm/
H A Dbcm63268-comtrend-vr-3032u.dts29 brcm,hardware-controlled;
35 brcm,hardware-controlled;
66 brcm,hardware-controlled;
71 brcm,hardware-controlled;
76 brcm,hardware-controlled;
81 brcm,hardware-controlled;
86 brcm,hardware-controlled;
91 brcm,hardware-controlled;
96 brcm,hardware-controlled;
/linux/Documentation/devicetree/bindings/regulator/
H A Dmediatek,mt6873-dvfsrc-regulator.yaml7 title: MediaTek DVFSRC-controlled Regulators
11 are controlled with votes to the DVFSRC hardware.
25 description: DVFSRC-controlled SoC Vcore regulator
30 description: DVFSRC-controlled System Control Processor regulator
/linux/Documentation/devicetree/bindings/dma/
H A Dqcom,bam-dma.yaml52 Indicates supported number of DMA channels in a remotely controlled bam.
54 qcom,controlled-remotely:
57 Indicates that the bam is controlled by remote processor i.e. execution
72 controlled bam.
94 - qcom,controlled-remotely
/linux/drivers/mux/
H A DKconfig35 tristate "GPIO-controlled Multiplexer"
38 GPIO-controlled Multiplexer controller.
49 tristate "MMIO/Regmap register bitfield-controlled Multiplexer"
52 MMIO/Regmap register bitfield-controlled Multiplexer controller.
/linux/Documentation/devicetree/bindings/pwm/
H A Dgoogle,cros-ec-pwm.yaml7 title: PWM controlled by ChromeOS EC
15 (EC) and controlled via a host-command interface.
25 - description: PWM controlled using EC_PWM_TYPE_GENERIC channels.
28 - description: PWM controlled using CROS_EC_PWM_DT_<...> types.
/linux/Documentation/leds/
H A Dleds-lm3556.rst26 LM3556 Flash can be controlled through /sys/class/leds/flash/brightness file
29 ON / OFF will be controlled by STROBE pin.
54 LM3556 torch can be controlled through /sys/class/leds/torch/brightness file.
56 and ON / OFF will be controlled by TORCH pin.
98 Indicator brightness can be controlled through
/linux/include/dt-bindings/sound/
H A Dcs35l45.h57 * 1 = Pin acts as a GPIO, direction controlled by 'gpio-dir'
58 * 2 = Pin acts as MDSYNC, direction controlled by MDSYNC
63 * 1 = Pin acts as a GPIO, direction controlled by 'gpio-dir'
72 * 1 = Pin acts as a GPIO, direction controlled by 'gpio-dir'
/linux/Documentation/hwmon/
H A Dnzxt-smart2.rst31 be controlled (`pwm*` changes will be ignored). It is necessary because the
49 pwm[1-3] Controls fan speed: PWM duty cycle for PWM-controlled
54 pwm[1-3]_enable 1 if the fan can be controlled by writing to the
58 pwm[1-3]_mode Read-only, 1 for PWM-controlled fans, 0 for other fans
H A Damc6821.rst24 The pwm can be controlled either from software or automatically.
55 pwm1_enable rw regulator mode, 1=open loop, 2=fan controlled
56 by remote temperature, 3=fan controlled by
59 4=fan controlled by target rpm set with
/linux/include/uapi/linux/
H A Dvfio_ccw.h28 * Note: this is controlled by a capability
40 * Note: this is controlled by a capability
49 * Note: this is controlled by a capability
/linux/drivers/staging/iio/Documentation/
H A Dsysfs-bus-iio-dds8 which allows for pin controlled FSK Frequency Shift Keying
38 allows for pin controlled PSK Phase Shift Keying
68 phase is controlled by the respective phase and frequency
81 controlled together.
/linux/Documentation/fault-injection/
H A Dnotifier-error-inject.rst16 This feature is controlled through debugfs interface
35 This feature is controlled through debugfs interface
53 This feature is controlled through debugfs interface
66 This feature is controlled through debugfs interface
/linux/Documentation/devicetree/bindings/sound/
H A Dcirrus,cs35l45.yaml105 1 = Pin acts as a GPIO, direction controlled by 'gpio-dir'
106 2 = Pin acts as MDSYNC, direction controlled by MDSYNC
110 1 = Pin acts as a GPIO, direction controlled by 'gpio-dir'
118 1 = Pin acts as a GPIO, direction controlled by 'gpio-dir'
/linux/include/linux/firmware/qcom/
H A Dqcom_scm.h119 * Request TZ to program set of access controlled registers necessary
124 * Request TZ to program BCL id to access controlled register when BCL is
129 * Request TZ to program set of access controlled register for CLX feature
134 * Request TZ to program tsense ids to access controlled registers for reading
/linux/drivers/i2c/muxes/
H A DKconfig28 I2C busses connected through a MUX, which is controlled
41 I2C busses connected through a MUX, which in turn is controlled
96 I2C busses connected through a MUX, which is controlled
116 I2C busses connected through a MUX, which is controlled
/linux/include/linux/mfd/samsung/
H A Ds2mps14.h118 * controlled however it does not specify which register is used for that.
127 /* On/Off controlled by PWREN */
129 /* On/Off controlled by LDO10EN or EMMCEN */
/linux/drivers/clk/berlin/
H A Dberlin2-div.c33 * (A) input pll clock mux controlled by <PllSelect[1:n]>
34 * (B) input pll bypass mux controlled by <PllSwitch>
35 * (C) programmable clock divider controlled by <Select[1:n]>
37 * (E) programmable clock divider bypass controlled by <Switch>
38 * (F) constant div-by-3 clock mux controlled by <D3Switch>
39 * (G) clock gate controlled by <Enable>

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