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/linux/drivers/net/ethernet/mellanox/mlx5/core/steering/
H A Ddr_ste.c806 static void dr_ste_copy_mask_misc(char *mask, struct mlx5dr_match_misc *spec, bool clr) in dr_ste_copy_mask_misc() argument
808 spec->gre_c_present = IFC_GET_CLR(fte_match_set_misc, mask, gre_c_present, clr); in dr_ste_copy_mask_misc()
809 spec->gre_k_present = IFC_GET_CLR(fte_match_set_misc, mask, gre_k_present, clr); in dr_ste_copy_mask_misc()
810 spec->gre_s_present = IFC_GET_CLR(fte_match_set_misc, mask, gre_s_present, clr); in dr_ste_copy_mask_misc()
811 spec->source_vhca_port = IFC_GET_CLR(fte_match_set_misc, mask, source_vhca_port, clr); in dr_ste_copy_mask_misc()
812 spec->source_sqn = IFC_GET_CLR(fte_match_set_misc, mask, source_sqn, clr); in dr_ste_copy_mask_misc()
814 spec->source_port = IFC_GET_CLR(fte_match_set_misc, mask, source_port, clr); in dr_ste_copy_mask_misc()
816 IFC_GET_CLR(fte_match_set_misc, mask, source_eswitch_owner_vhca_id, clr); in dr_ste_copy_mask_misc()
818 spec->outer_second_prio = IFC_GET_CLR(fte_match_set_misc, mask, outer_second_prio, clr); in dr_ste_copy_mask_misc()
819 spec->outer_second_cfi = IFC_GET_CLR(fte_match_set_misc, mask, outer_second_cfi, clr); in dr_ste_copy_mask_misc()
[all …]
/linux/drivers/net/ethernet/intel/e1000e/
H A Dregs.h32 #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
121 #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
122 #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
123 #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
124 #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
125 #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
126 #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
127 #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
128 #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
129 #define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
[all …]
/linux/drivers/net/ethernet/intel/igc/
H A Digc_regs.h133 #define IGC_CRCERRS 0x04000 /* CRC Error Count - R/clr */
134 #define IGC_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
135 #define IGC_RXERRC 0x0400C /* Receive Error Count - R/clr */
136 #define IGC_MPC 0x04010 /* Missed Packet Count - R/clr */
137 #define IGC_SCC 0x04014 /* Single Collision Count - R/clr */
138 #define IGC_ECOL 0x04018 /* Excessive Collision Count - R/clr */
139 #define IGC_MCC 0x0401C /* Multiple Collision Count - R/clr */
140 #define IGC_LATECOL 0x04020 /* Late Collision Count - R/clr */
141 #define IGC_COLC 0x04028 /* Collision Count - R/clr */
142 #define IGC_RERC 0x0402C /* Receive Error Count - R/clr */
[all …]
/linux/drivers/net/ethernet/intel/igb/
H A De1000_regs.h21 #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
30 #define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */
187 #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
188 #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
189 #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
190 #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
191 #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
192 #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
193 #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
194 #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
[all …]
/linux/include/trace/events/
H A Dthp.h40 TP_PROTO(unsigned long addr, unsigned long pte, unsigned long clr, unsigned long set),
41 TP_ARGS(addr, pte, clr, set),
45 __field(unsigned long, clr)
52 __entry->clr = clr;
57 …page update at addr 0x%lx and pte = 0x%lx clr = 0x%lx, set = 0x%lx", __entry->addr, __entry->pte, …
61 TP_PROTO(unsigned long addr, unsigned long pmd, unsigned long clr, unsigned long set),
62 TP_ARGS(addr, pmd, clr, set)
66 TP_PROTO(unsigned long addr, unsigned long pud, unsigned long clr, unsigned long set),
67 TP_ARGS(addr, pud, clr, set)
/linux/arch/m68k/math-emu/
H A Dfp_util.S70 2: clr.l %d0
99 clr.l %d1 | sign defaults to zero
109 clr.l (%a0)
116 clr.l (%a0)+
117 clr.l (%a0)+
118 clr.l (%a0)
142 clr.l (%a0) | low lword = 0
236 clr.b (%a0)
274 clr.l %d0
279 clr.w -(%a0)
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/linux/drivers/video/fbdev/
H A Datafb_utils.h85 " lsr.l #1,%1 ; jcc 1f ; clr.b (%0)+\n" in fb_memclear()
86 "1: lsr.l #1,%1 ; jcc 1f ; clr.w (%0)+\n" in fb_memclear()
87 "1: lsr.l #1,%1 ; jcc 1f ; clr.l (%0)+\n" in fb_memclear()
88 "1: lsr.l #1,%1 ; jcc 1f ; clr.l (%0)+ ; clr.l (%0)+\n" in fb_memclear()
96 " lsr.l #1,%2 ; jcc 1f ; clr.b (%0)+ ; subq.w #1,%1\n" in fb_memclear()
98 " clr.w (%0)+ ; subq.w #2,%1 ; jra 2f\n" in fb_memclear()
100 " clr.w (%0)+ ; subq.w #2,%1\n" in fb_memclear()
102 " lsr.l #1,%1 ; jcc 3f ; clr.l (%0)+\n" in fb_memclear()
103 "3: lsr.l #1,%1 ; jcc 4f ; clr.l (%0)+ ; clr.l (%0)+\n" in fb_memclear()
105 "5: clr.l (%0)+; clr.l (%0)+ ; clr.l (%0)+ ; clr.l (%0)+\n" in fb_memclear()
[all …]
/linux/arch/m68k/ifpsp060/src/
H A Ditest.S81 clr.l TESTCTR(%a6)
91 clr.l TESTCTR(%a6)
101 clr.l TESTCTR(%a6)
111 clr.l TESTCTR(%a6)
121 clr.l TESTCTR(%a6)
132 clr.l TESTCTR(%a6)
142 clr.l TESTCTR(%a6)
169 clr.l %d1
181 clr.l IREGS+0x8(%a6)
182 clr.l IREGS+0xc(%a6)
[all …]
/linux/arch/sparc/lib/
H A Dffs.S14 clr %o0
21 clr %o1 /* 2 */
25 1: clr %o2
31 clr %o3
34 clr %o4
40 clr %o5
/linux/Documentation/admin-guide/
H A Dmono.rst5 (in the form of .exe files) without the need to use the mono CLR
11 1) You MUST FIRST install the Mono CLR support, either by downloading
21 Once the Mono CLR support has been installed, just check that
50 # Register support for .NET CLR binaries
53 # the Mono CLR runtime (usually /usr/local/bin/mono
55 echo ':CLR:M::MZ::/usr/bin/mono:' > /proc/sys/fs/binfmt_misc/register
/linux/arch/arm64/kvm/hyp/nvhe/
H A Dtimer-sr.c42 u64 clr = 0, set = 0; in __timer_enable_traps() local
49 clr = CNTHCTL_EL1PCEN; in __timer_enable_traps()
54 clr |= CNTHCTL_EL1PCTEN; in __timer_enable_traps()
57 clr <<= 10; in __timer_enable_traps()
61 sysreg_clear_set(cnthctl_el2, clr, set); in __timer_enable_traps()
/linux/arch/arm64/include/asm/
H A Dkvm_emulate.h550 #define __cpacr_to_cptr_clr(clr, set) \ argument
560 if ((clr) & CPACR_ELx_TTA) \
562 if ((clr) & CPTR_EL2_TAM) \
564 if ((clr) & CPTR_EL2_TCPAC) \
570 #define __cpacr_to_cptr_set(clr, set) \ argument
574 if ((clr) & CPACR_ELx_FPEN) \
576 if ((clr) & CPACR_ELx_ZEN) \
578 if ((clr) & CPACR_ELx_SMEN) \
590 #define cpacr_clear_set(clr, set) \ argument
593 BUILD_BUG_ON((clr) & CPACR_ELx_E0POE); \
[all …]
/linux/arch/m68k/ifpsp060/
H A Dos.S94 clr.l %d1 | return success
101 clr.l %d1 | return success
127 clr.l %d1 | return success
134 clr.l %d1 | return success
151 clr.l %d0 | clear whole longword
152 clr.l %d1 | assume success
187 clr.l %d1 | assume success
188 clr.l %d0 | clear whole longword
223 clr.l %d1 | assume success
245 clr.l %d1 | assume success
[all …]
/linux/arch/powerpc/include/asm/nohash/32/
H A Dpte-8xx.h123 unsigned long clr, unsigned long set, int huge);
135 unsigned long clr = ~pte_val(entry) & _PAGE_RO; in __ptep_set_access_flags() local
138 pte_update(vma->vm_mm, address, ptep, clr, set, huge); in __ptep_set_access_flags()
188 unsigned long clr, unsigned long set, int huge) in __pte_update() argument
192 pte_basic_t new = (old & ~(pte_basic_t)clr) | set; in __pte_update()
211 unsigned long clr, unsigned long set, int huge) in pte_update() argument
218 old = __pte_update(mm, addr, pte_offset_kernel(pmdp, 0), clr, set, huge); in pte_update()
219 __pte_update(mm, addr, pte_offset_kernel(pmdp + 1, 0), clr, set, huge); in pte_update()
221 old = __pte_update(mm, addr, ptep, clr, set, huge); in pte_update()
/linux/drivers/clocksource/
H A Dtimer-armada-370-xp.c88 static void local_timer_ctrl_clrset(u32 clr, u32 set) in local_timer_ctrl_clrset() argument
90 writel((readl(local_base + TIMER_CTRL_OFF) & ~clr) | set, in local_timer_ctrl_clrset()
173 u32 clr = 0, set = 0; in armada_370_xp_timer_starting_cpu() local
178 clr = TIMER0_25MHZ; in armada_370_xp_timer_starting_cpu()
179 local_timer_ctrl_clrset(clr, set); in armada_370_xp_timer_starting_cpu()
242 u32 clr = 0, set = 0; in armada_370_xp_timer_common_init() local
261 clr = TIMER0_25MHZ; in armada_370_xp_timer_common_init()
264 atomic_io_modify(timer_base + TIMER_CTRL_OFF, clr | set, set); in armada_370_xp_timer_common_init()
265 local_timer_ctrl_clrset(clr, set); in armada_370_xp_timer_common_init()
/linux/drivers/staging/media/omap4iss/
H A Diss.h187 * @clr: bit mask to be cleared
191 u32 offset, u32 clr) in iss_reg_clr() argument
195 iss_reg_write(iss, res, offset, v & ~clr); in iss_reg_clr()
219 * @clr: bit mask to be cleared
222 * Clear the clr mask first and then set the set mask.
226 u32 offset, u32 clr, u32 set) in iss_reg_update() argument
230 iss_reg_write(iss, res, offset, (v & ~clr) | set); in iss_reg_update()
/linux/arch/powerpc/include/asm/
H A Ddcr-native.h112 unsigned clr, unsigned set) in __dcri_clrset() argument
120 val = (mfdcrx(base_data) & ~clr) | set; in __dcri_clrset()
124 val = (__mfdcr(base_data) & ~clr) | set; in __dcri_clrset()
138 #define dcri_clrset(base, reg, clr, set) __dcri_clrset(DCRN_ ## base ## _CONFIG_ADDR, \ argument
140 reg, clr, set)
/linux/arch/arm/mach-rpc/
H A Dirq.c14 #define CLR 0x04 macro
132 writeb(mask, base + CLR); in iomd_irq_mask_ack()
168 unsigned int irq, clr, set; in rpc_init_irq() local
181 clr = IRQ_NOREQUEST; in rpc_init_irq()
185 clr |= IRQ_NOPROBE; in rpc_init_irq()
195 irq_modify_status(irq, clr, set); in rpc_init_irq()
203 irq_modify_status(irq, clr, set); in rpc_init_irq()
211 irq_modify_status(irq, clr, set); in rpc_init_irq()
218 irq_modify_status(irq, clr, set); in rpc_init_irq()
/linux/drivers/gpio/
H A Dgpio-mmio.c470 * - set/clear pair (named "set" and "clr").
475 * by clearing a bit. For the set clr pair, this drives a 1 by setting a bit
490 void __iomem *clr, in bgpio_setup_io() argument
498 if (set && clr) { in bgpio_setup_io()
500 gc->reg_clr = clr; in bgpio_setup_io()
503 } else if (set && !clr) { in bgpio_setup_io()
582 * @clr: MMIO address for the register to CLEAR the value of the GPIO lines, it is
600 void __iomem *clr, void __iomem *dirout, void __iomem *dirin, in bgpio_init() argument
623 ret = bgpio_setup_io(gc, dat, set, clr, flags); in bgpio_init()
722 void __iomem *clr; in bgpio_pdev_probe() local
[all …]
/linux/drivers/gpu/drm/meson/
H A Dmeson_dw_mipi_dsi.h135 /* [31:16] RW intr_stat/clr. Default 0.
139 * [ 21] stat/clr of eof interrupt
141 * [ 19] stat/clr of de_rise interrupt
142 * [ 18] stat/clr of vs_fall interrupt
143 * [ 17] stat/clr of vs_rise interrupt
144 * [ 16] stat/clr of dwc_edpite interrupt
/linux/drivers/gpu/drm/nouveau/dispnv50/
H A Dwndw.c130 union nv50_wndw_atom_mask clr = { in nv50_wndw_flush_clr() local
131 .mask = asyw->clr.mask & ~(flush ? 0 : asyw->set.mask), in nv50_wndw_flush_clr()
133 if (clr.sema ) wndw->func-> sema_clr(wndw); in nv50_wndw_flush_clr()
134 if (clr.ntfy ) wndw->func-> ntfy_clr(wndw); in nv50_wndw_flush_clr()
135 if (clr.xlut ) wndw->func-> xlut_clr(wndw); in nv50_wndw_flush_clr()
136 if (clr.csc ) wndw->func-> csc_clr(wndw); in nv50_wndw_flush_clr()
137 if (clr.image) wndw->func->image_clr(wndw); in nv50_wndw_flush_clr()
413 asyw->clr.xlut = armw->xlut.handle != 0; in nv50_wndw_atomic_check_lut()
428 asyw->clr.csc = armw->csc.valid; in nv50_wndw_atomic_check_lut()
504 asyw->clr.ntfy = armw->ntfy.handle != 0; in nv50_wndw_atomic_check()
[all …]
H A Dhead.c43 union nv50_head_atom_mask clr = { in nv50_head_flush_clr() local
44 .mask = asyh->clr.mask & ~(flush ? 0 : asyh->set.mask), in nv50_head_flush_clr()
46 if (clr.crc) nv50_crc_atomic_clr(head); in nv50_head_flush_clr()
47 if (clr.olut) head->func->olut_clr(head); in nv50_head_flush_clr()
48 if (clr.core) head->func->core_clr(head); in nv50_head_flush_clr()
49 if (clr.curs) head->func->curs_clr(head); in nv50_head_flush_clr()
412 asyh->clr.core = true; in nv50_head_atomic_check()
420 asyh->clr.curs = true; in nv50_head_atomic_check()
428 asyh->clr.olut = true; in nv50_head_atomic_check()
431 asyh->clr.olut = armh->olut.visible; in nv50_head_atomic_check()
[all …]
/linux/drivers/net/ethernet/intel/e1000/
H A De1000_hw.h773 * R/clr - register is read only and is cleared when read
799 #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
914 #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
915 #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
916 #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
917 #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
918 #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
919 #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
920 #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
921 #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
[all …]
/linux/drivers/net/wireless/ath/ath9k/
H A Dar9003_wow.c127 u32 set, clr; in ath9k_hw_wow_apply_pattern() local
160 clr = AR_WOW_LENGTH1_MASK(pattern_count); in ath9k_hw_wow_apply_pattern()
161 REG_RMW(ah, AR_WOW_LENGTH1, set, clr); in ath9k_hw_wow_apply_pattern()
165 clr = AR_WOW_LENGTH2_MASK(pattern_count); in ath9k_hw_wow_apply_pattern()
166 REG_RMW(ah, AR_WOW_LENGTH2, set, clr); in ath9k_hw_wow_apply_pattern()
170 clr = AR_WOW_LENGTH3_MASK(pattern_count); in ath9k_hw_wow_apply_pattern()
171 REG_RMW(ah, AR_WOW_LENGTH3, set, clr); in ath9k_hw_wow_apply_pattern()
175 clr = AR_WOW_LENGTH4_MASK(pattern_count); in ath9k_hw_wow_apply_pattern()
176 REG_RMW(ah, AR_WOW_LENGTH4, set, clr); in ath9k_hw_wow_apply_pattern()
/linux/kernel/irq/
H A Ddevres.c237 unsigned int clr; member
245 irq_remove_generic_chip(this->gc, this->msk, this->clr, this->set); in devm_irq_remove_generic_chip()
256 * @clr: IRQ_* bits to clear
265 unsigned int clr, unsigned int set) in devm_irq_setup_generic_chip() argument
274 irq_setup_generic_chip(gc, msk, flags, clr, set); in devm_irq_setup_generic_chip()
278 dr->clr = clr; in devm_irq_setup_generic_chip()

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