Searched full:bridge0 (Results 1 – 3 of 3) sorted by relevance
93 | | H | | |==>| Bridge0 |<==>| PRR0 | |108 a soft logic bridge (Bridge0-2) in the FPGA. The contents of each PRR can be
755 /* check is endpoint is attach to host-bridge0 */ in mock_init_hdm_decoder() 772 * attached to host-bridge0 mock a fake / static RAM region. All in mock_init_hdm_decoder()
608 What: /sys/bus/cxl/devices/nvdimm-bridge0/ndbusX/nmemY/cxl/dirty_shutdown