Searched +full:5 +full:vdc (Results 1 – 2 of 2) sorted by relevance
94 [MSTP74] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR7, 4, 0), /* VDC */120 CLKDEV_ICK_ID("fck", "sh-sci.5", &mstp_clks[MSTP77]),
36 * 5 110Hz 750uV 22.956 #define MPC624_DIO 5 /* read/write to/from digital I/O ports */60 #define MPC624_ADBUSY BIT(5)210 * We always write 0 to GNSWA bit, so the channel range is +-/10.1Vdc in mpc624_ai_insn_read()265 case 5: in mpc624_attach()