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/freebsd/sys/contrib/zstd/lib/compress/
H A Dclevels.h5 * This source code is licensed under both the BSD-style license (found in the
8 * You may select, at your option, one of the above-listed licenses.
17 /*-===== Pre-defined compression levels =====-*/
25 static const ZSTD_compressionParameters ZSTD_defaultCParameters[4][ZSTD_MAX_CLEVEL+1] = {
26 { /* "default" - for any srcSize > 256 KB */
29 { 19, 13, 14, 1, 7, 0, ZSTD_fast }, /* level 1 */
30 { 20, 15, 16, 1, 6, 0, ZSTD_fast }, /* level 2 */
31 { 21, 16, 17, 1, 5, 0, ZSTD_dfast }, /* level 3 */
32 { 21, 18, 18, 1, 5, 0, ZSTD_dfast }, /* level 4 */
33 { 21, 18, 19, 3, 5, 2, ZSTD_greedy }, /* level 5 */
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/freebsd/secure/lib/libcrypto/man/man7/
H A Dossl-guide-migration.71 .\" -*- mode: troff; coding: utf-8 -*-
57 .IX Title "OSSL-GUIDE-MIGRATION 7ossl"
58 .TH OSSL-GUIDE-MIGRATION 7ossl 2025-09-30 3.5.4 OpenSSL
64 ossl\-guide\-migration, migration_guide
65 \&\- OpenSSL Guide: Migrating from older OpenSSL versions
80 The FIPS provider in OpenSSL 3.1 includes some non-FIPS validated algorithms,
83 .IP "Triple DES ECB" 4
86 .IP "Triple DES CBC" 4
88 .IP EdDSA 4
113 licenses <https://www.openssl.org/source/license-openssl-ssleay.txt>
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/freebsd/secure/lib/libcrypto/man/man3/
H A DSSL_CTX_set_security_level.31 .\" -*- mode: troff; coding: utf-8 -*-
58 .TH SSL_CTX_SET_SECURITY_LEVEL 3ossl 2025-09-30 3.5.4 OpenSSL
64 …security_ex_data, SSL_CTX_get0_security_ex_data, SSL_get0_security_ex_data \- SSL/TLS security fra…
70 \& void SSL_CTX_set_security_level(SSL_CTX *ctx, int level);
71 \& void SSL_set_security_level(SSL *s, int level);
101 the security level to \fBlevel\fR. If not set the library default security level
105 retrieve the current security level.
122 of each level is described below.
123 .IP "\fBLevel 0\fR" 4
124 .IX Item "Level 0"
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/freebsd/sys/contrib/device-tree/src/arm64/hisilicon/
H A Dhip07.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
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/freebsd/lib/libpmc/pmu-events/arch/s390/cf_z13/
H A Dextended.json5 "BriefDescription": "L1D Read-only Exclusive Writes",
6 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in…
12 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
18 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
23 "BriefDescription": "DTLB1 One-Megabyte Page Writes",
24 …on": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a …
29 "BriefDescription": "DTLB1 Two-Gigabyte Page Writes",
30 …on": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a …
36 …tion": "A directory write to the Level-1 Data cache directory where the returned cache line was so…
42 …"PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation …
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/freebsd/sys/contrib/device-tree/Bindings/arm/socionext/
H A Dsocionext,uniphier-system-cache.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/socionext/socionext,uniphier-system-cache.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache
11 controller system. All of them have a level 2 cache controller, and some
12 have a level 3 cache controller as well.
15 - Masahiro Yamada <yamada.masahiro@socionext.com>
19 const: socionext,uniphier-system-cache
33 maxItems: 4
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/freebsd/sys/contrib/device-tree/Bindings/cache/
H A Dsocionext,uniphier-system-cache.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cache/socionext,uniphier-system-cache.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache
11 controller system. All of them have a level 2 cache controller, and some
12 have a level 3 cache controller as well.
15 - Masahiro Yamada <yamada.masahiro@socionext.com>
19 const: socionext,uniphier-system-cache
33 maxItems: 4
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/freebsd/sys/contrib/device-tree/src/arm64/rockchip/
H A Drockchip-pinconf.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /omit-if-no-ref/
8 pcfg_pull_up: pcfg-pull-up {
9 bias-pull-up;
12 /omit-if-no-ref/
13 pcfg_pull_down: pcfg-pull-down {
14 bias-pull-down;
17 /omit-if-no-ref/
18 pcfg_pull_none: pcfg-pull-none {
19 bias-disable;
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/freebsd/share/man/man4/
H A Dmac_mls.41 .\" Copyright (c) 2002-2004 Networks Associates Technology, Inc.
7 .\" DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the
36 .Nd "Multi-Level Security confidentiality policy"
40 .Bd -ragged -offset indent
47 .Bd -ragged -offset indent
53 .Bd -literal -offset indent
59 policy module implements the Multi-Level Security, or MLS model,
63 each subject's MLS label contains information on its clearance level,
67 made up of a sensitivity level and zero or more compartments.
71 The sensitivity level is expressed as a value between 0 and
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H A Dcpufreq.425 .Dd April 4, 2022
38 .Fn cpufreq_set "device_t dev" "const struct cf_level *level" "int priority"
40 .Fn cpufreq_get "device_t dev" "struct cf_level *level"
79 configured P-state.)
87 .Bl -tag -width indent
111 If enabled, the AMD hwpstate driver limits administrative control of P-states
117 P-state, which results in the inability to ever raise the P-state back to P0
126 .Bl -tag -compact -width "hwpstate_intel(4)"
129 .It Xr est 4
133 .It Xr hwpstate_intel 4
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H A Dsmp.424 .Dd January 4, 2019
29 .Nd description of the FreeBSD Symmetric Multi-Processor kernel
35 kernel implements symmetric multi-processor support.
43 the read-only sysctl variable
46 The number of online threads per CPU core is available in the read-only sysctl
50 read-only sysctl variable
54 allows specific CPUs on a multi-processor system to be disabled.
68 .Xr sched_ule 4
70 algorithms to make better use of modern multi-core CPUs.
74 The top level XML tag is <groups>, which encloses one or more <group> tags
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H A Dpsm.43 .\" Kazutaka YOKOTA <yokota@zodiac.mech.utsunomiya-u.ac.jp>
94 The current operation level can be set via an ioctl call.
96 At the level zero the basic support is provided; the device driver will report
99 The movement and status are encoded in a series of fixed-length data packets
102 This is the default level of operation and the driver is initially
103 at this level when opened by the user program.
105 The operation level one, the `extended' level, supports a roller (or wheel),
108 8 byte data packets are sent to the user program at this level.
110 At the operation level two, data from the pointing device is passed to the
118 the driver at this level.
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/freebsd/sys/contrib/device-tree/Bindings/cpufreq/
H A Dcpufreq-qcom-hw.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
21 - description: v1 of CPUFREQ HW
23 - enum:
24 - qcom,qcm2290-cpufreq-hw
25 - qcom,sc7180-cpufreq-hw
26 - qcom,sc8180x-cpufreq-hw
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/freebsd/lib/libpmc/pmu-events/arch/s390/cf_z196/
H A Dextended.json6 …iption": "A directory write to the Level-1 D-Cache directory where the returned cache line was sou…
12 …iption": "A directory write to the Level-1 I-Cache directory where the returned cache line was sou…
18 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
24 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle…
30 "PublicDescription": "Incremented by one for every store sent to Level-2 cache"
35 "BriefDescription": "L1D Off-Book L3 Sourced Writes",
36 …on": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced…
41 "BriefDescription": "L1D On-Book L4 Sourced Writes",
42 …on": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced…
47 "BriefDescription": "L1I On-Book L4 Sourced Writes",
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/freebsd/contrib/ofed/infiniband-diags/man/
H A Dinfiniband-diags.83 .TH INFINIBAND-DIAGS 8 "" "" "Open IB Diagnostics"
5 INFINIBAND-DIAGS \-
7 .nr rst2man-indent-level 0
10 \\$1 \\n[an-margin]
11 level \\n[rst2man-indent-level]
12 level margin: \\n[rst2man-indent\\n[rst2man-indent-level]]
13 -
14 \\n[rst2man-indent0]
15 \\n[rst2man-indent1]
16 \\n[rst2man-indent2]
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H A Dibroute.85 IBROUTE \-
7 .nr rst2man-indent-level 0
10 \\$1 \\n[an-margin]
11 level \\n[rst2man-indent-level]
12 level margin: \\n[rst2man-indent\\n[rst2man-indent-level]]
13 -
14 \\n[rst2man-indent0]
15 \\n[rst2man-indent1]
16 \\n[rst2man-indent2]
21 . nr rst2man-indent\\n[rst2man-indent-level] \\n[an-margin]
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/freebsd/usr.bin/m4/TEST/
H A Dmath.m42 dnl If you think you have a short-circuiting m4, run us m4 -DSHORCIRCUIT=yes
4 dnl first level of precedence
5 ifelse(expr(-7),-7,,`failed -
7 ifelse(expr(- -2),2,,`failed -
13 ifelse(expr(~-1),0,,`failed ~
15 dnl next level of precedence
28 ifelse(expr(2%-1),0,,`failed %
30 dnl next level of precedence
31 ifelse(expr(2+2),4,,`failed +
33 ifelse(expr(2+-2),0,,`failed +
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/freebsd/tools/tools/usbtest/
H A Dusbtest.c1 /*-
2 * Copyright (c) 2010-2022 Hans Petter Selasky
79 temp |= (-0x800000); in usb_ts_rand_noise()
85 usb_ts_show_menu(uint8_t level, const char *title, const char *fmt,...) in usb_ts_show_menu() argument
100 for (x = 0; x != level; x++) { in usb_ts_show_menu()
101 if ((x + 1) == level) in usb_ts_show_menu()
107 printf("] - %s:\n\n", title); in usb_ts_show_menu()
112 printf("%s", indent[level]); in usb_ts_show_menu()
131 usb_ts_select[level] = retval; in usb_ts_show_menu()
144 ptr[size - 1] = 0; in get_string()
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/freebsd/sys/x86/x86/
H A Didentcpu.c1 /*-
22 * 4. Neither the name of the University nor the names of its contributors
71 #include <xen/xen-os.h>
154 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch) in sysctl_hw_machine()
199 "Intel Pentium 4"
222 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */
252 u_int regs[4], i; in printcpuinfo()
313 "DX2 Write-Back Enhanced"); in printcpuinfo()
325 strcat(cpu_model, " A-step"); in printcpuinfo()
343 strcat(cpu_model, "/P55C (quarter-micron)"); in printcpuinfo()
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/freebsd/contrib/wpa/src/utils/
H A Dwpa_debug.h3 * Copyright (c) 2002-2013, Jouni Malinen <j@w1.fi>
19 /* Debugging function - conditional printf and hex dump. Driver wrappers can
55 * wpa_debug_printf_timestamp - Print timestamp for debug output
64 * wpa_printf - conditional printf
65 * @level: priority level (MSG_*) of the message
74 void wpa_printf(int level, const char *fmt, ...)
78 * wpa_hexdump - conditional hex dump
79 * @level: priority level (MSG_*) of the message
88 void wpa_hexdump(int level, const char *title, const void *buf, size_t len);
90 static inline void wpa_hexdump_buf(int level, const char *title, in wpa_hexdump_buf() argument
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/freebsd/lib/libpmc/pmu-events/arch/s390/cf_zec12/
H A Dextended.json6 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
12 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle…
18 …tion": "A directory write to the Level-1 Data cache directory where the returned cache line was so…
24 …n": "A directory write to the Level-1 Instruction cache directory where the returned cache line wa…
30 …tion": "A directory write to the Level-1 Data cache directory where the returned cache line was so…
36 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
42 …"PublicDescription": "A directory write to the Level-1 Data cache where the installed cache line w…
48 …"PublicDescription": "A directory write to the Level-1 Instruction cache where the installed cache…
53 "BriefDescription": "L1D Read-only Exclusive Writes",
54 …"PublicDescription": "A directory write to the Level-1 D-Cache where the line was originally in a …
[all …]
/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dimg,pdc-intc.txt10 - compatible: Specifies the compatibility list for the interrupt controller.
11 The type shall be <string> and the value shall include "img,pdc-intc".
13 - reg: Specifies the base PDC physical address(s) and size(s) of the
14 addressable register space. The type shall be <prop-encoded-array>.
16 - interrupt-controller: The presence of this property identifies the node
19 - #interrupt-cells: Specifies the number of cells needed to encode an
22 - num-perips: Number of waking peripherals.
24 - num-syswakes: Number of SysWake inputs.
26 - interrupts: List of interrupt specifiers. The first specifier shall be the
34 - <1st-cell>: The interrupt-number that identifies the interrupt source.
[all …]
/freebsd/sys/contrib/dpdk_rte_lpm/
H A Drte_log.h1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
35 uint32_t level; /**< Log level. */ member
49 #define RTE_LOGTYPE_TIMER 4 /**< Log related to timers. */
68 #define RTE_LOGTYPE_USER1 24 /**< User-defined log type 1. */
69 #define RTE_LOGTYPE_USER2 25 /**< User-defined log type 2. */
70 #define RTE_LOGTYPE_USER3 26 /**< User-defined log type 3. */
71 #define RTE_LOGTYPE_USER4 27 /**< User-defined log type 4. */
72 #define RTE_LOGTYPE_USER5 28 /**< User-defined log type 5. */
73 #define RTE_LOGTYPE_USER6 29 /**< User-defined log type 6. */
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/freebsd/contrib/libarchive/libarchive/
H A Darchive_write_set_options.31 .\" Copyright (c) 2003-2010 Tim Kientzle
35 Streaming Archive Library (libarchive, -larchive)
66 .Bl -tag -width indent
71 Specifies an option that will be passed to the currently-registered
143 is a comma-separated list of options.
153 .Bl -tag -compact -width indent
170 .Bl -tag -compact -width indent
172 .Bl -tag -compact -width indent
179 .Bl -tag -compact -width indent
180 .It Cm compression-level
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/freebsd/sys/contrib/device-tree/include/dt-bindings/pinctrl/
H A Dqcom,pmic-mpp.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Multi-Purpose Pin binding.
10 /* power-source */
12 /* Digital Input/Output: level [PM8058] */
18 /* Digital Input/Output: level [PM8901] */
23 #define PM8901_MPP_VPH 4
25 /* Digital Input/Output: level [PM8921] */
28 #define PM8921_MPP_L17 4
31 /* Digital Input/Output: level [PM8821] */
35 /* Digital Input/Output: level [PM8018] */
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