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/linux/drivers/mtd/nand/raw/
H A Dnand_ids.c29 {"TC58NVG0S3E 1G 3.3V 8-bit",
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
38 {"TC58NVG3S0F 8G 3.3V 8-bit",
41 {"TC58NVG5D2 32G 3.3V 8-bit",
44 {"TC58NVG6D2 64G 3.3V 8-bit",
47 {"SDTNQGAMA 64G 3.3V 8-bit",
50 {"SDTNRGAMA 64G 3.3V 8-bit",
53 {"H27UCG8T2ATR-BC 64G 3.3V 8-bit",
57 {"H27UCG8T2ETR-BC 64G 3.3V 8-bit",
[all …]
H A Dsm_common.c18 oobregion->length = 3; in oob_sm_ooblayout_ecc()
19 oobregion->offset = ((section + 1) * 8) - 3; in oob_sm_ooblayout_ecc()
67 oobregion->length = 3; in oob_sm_small_ooblayout_ecc()
79 oobregion->offset = 3; in oob_sm_small_ooblayout_free()
129 LEGACY_ID_NAND("SmartMedia 2MiB 3,3V ROM", 0x5d, 2, SZ_8K, NAND_ROM),
130 LEGACY_ID_NAND("SmartMedia 4MiB 3,3V", 0xe3, 4, SZ_8K, 0),
131 LEGACY_ID_NAND("SmartMedia 4MiB 3,3/5V", 0xe5, 4, SZ_8K, 0),
132 LEGACY_ID_NAND("SmartMedia 4MiB 5V", 0x6b, 4, SZ_8K, 0),
133 LEGACY_ID_NAND("SmartMedia 4MiB 3,3V ROM", 0xd5, 4, SZ_8K, NAND_ROM),
134 LEGACY_ID_NAND("SmartMedia 8MiB 3,3V", 0xe6, 8, SZ_8K, 0),
[all …]
/linux/Documentation/hwmon/
H A Ddme1737.rst63 and SCH5127 Super-I/O chips. These chips feature monitoring of 3 temp sensors
64 temp[1-3] (2 remote diodes and 1 internal), 8 voltages in[0-7] (7 external and
66 up to 5 PWM outputs pwm[1-3,5-6] for controlling fan speeds both manually and
70 Fan[3-6] and pwm[3,5-6] are optional features and their availability depends on
74 For the SCH311x and SCH5127, fan[1-3] and pwm[1-3] are always present and
94 in0: +5VTR (+5V standby) 0V - 6.64V
95 in1: Vccp (processor core) 0V - 3V
96 in2: VCC (internal +3.3V) 0V - 4.38V
97 in3: +5V 0V - 6.64V
98 in4: +12V 0V - 16V
[all …]
H A Dltc4245.rst52 in1_input 12v input voltage (mV)
53 in2_input 5v input voltage (mV)
54 in3_input 3v input voltage (mV)
55 in4_input Vee (-12v) input voltage (mV)
57 in1_min_alarm 12v input undervoltage alarm
58 in2_min_alarm 5v input undervoltage alarm
59 in3_min_alarm 3v input undervoltage alarm
60 in4_min_alarm Vee (-12v) input undervoltage alarm
62 curr1_input 12v current (mA)
63 curr2_input 5v current (mA)
[all …]
/linux/lib/crypto/
H A Dblake2s-generic.c20 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 },
21 { 14, 10, 4, 8, 9, 15, 13, 6, 1, 12, 0, 2, 11, 7, 5, 3 },
22 { 11, 8, 12, 0, 5, 2, 15, 13, 10, 14, 3, 6, 7, 1, 9, 4 },
23 { 7, 9, 3, 1, 13, 12, 11, 14, 2, 6, 5, 10, 4, 0, 15, 8 },
24 { 9, 0, 5, 7, 2, 4, 10, 15, 14, 1, 11, 12, 6, 8, 3, 13 },
25 { 2, 12, 6, 10, 0, 11, 8, 3, 4, 13, 7, 5, 15, 14, 1, 9 },
26 { 12, 5, 1, 15, 14, 13, 4, 10, 0, 7, 6, 3, 9, 2, 8, 11 },
27 { 13, 11, 7, 14, 12, 1, 3, 9, 5, 0, 15, 4, 8, 6, 2, 10 },
28 { 6, 15, 14, 9, 11, 3, 0, 8, 12, 2, 13, 7, 1, 4, 10, 5 },
29 { 10, 2, 8, 4, 7, 6, 1, 5, 15, 11, 9, 14, 3, 12, 13, 0 },
[all …]
/linux/Documentation/userspace-api/media/v4l/
H A Dsubdev-formats.rst124 :widths: 3 1 4
225 :widths: 36 7 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
262 - 3
291 - r\ :sub:`3`
295 - g\ :sub:`3`
299 - b\ :sub:`3`
336 - r\ :sub:`3`
367 - g\ :sub:`3`
371 - b\ :sub:`3`
404 - g\ :sub:`3`
[all …]
/linux/crypto/
H A Dblake2b_generic.c26 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 },
27 { 14, 10, 4, 8, 9, 15, 13, 6, 1, 12, 0, 2, 11, 7, 5, 3 },
28 { 11, 8, 12, 0, 5, 2, 15, 13, 10, 14, 3, 6, 7, 1, 9, 4 },
29 { 7, 9, 3, 1, 13, 12, 11, 14, 2, 6, 5, 10, 4, 0, 15, 8 },
30 { 9, 0, 5, 7, 2, 4, 10, 15, 14, 1, 11, 12, 6, 8, 3, 13 },
31 { 2, 12, 6, 10, 0, 11, 8, 3, 4, 13, 7, 5, 15, 14, 1, 9 },
32 { 12, 5, 1, 15, 14, 13, 4, 10, 0, 7, 6, 3, 9, 2, 8, 11 },
33 { 13, 11, 7, 14, 12, 1, 3, 9, 5, 0, 15, 4, 8, 6, 2, 10 },
34 { 6, 15, 14, 9, 11, 3, 0, 8, 12, 2, 13, 7, 1, 4, 10, 5 },
35 { 10, 2, 8, 4, 7, 6, 1, 5, 15, 11, 9, 14, 3, 12, 13, 0 },
[all …]
/linux/fs/bcachefs/
H A Dsiphash.c1 // SPDX-License-Identifier: BSD-3-Clause
2 /* $OpenBSD: siphash.c,v 1.3 2015/02/20 11:51:03 tedu Exp $ */
16 * 3. The name of the author may not be used to endorse or promote
57 ctx->v[0] += ctx->v[1]; in SipHash_Rounds()
58 ctx->v[2] += ctx->v[3]; in SipHash_Rounds()
59 ctx->v[1] = rol64(ctx->v[1], 13); in SipHash_Rounds()
60 ctx->v[3] = rol64(ctx->v[3], 16); in SipHash_Rounds()
62 ctx->v[1] ^= ctx->v[0]; in SipHash_Rounds()
63 ctx->v[3] ^= ctx->v[2]; in SipHash_Rounds()
64 ctx->v[0] = rol64(ctx->v[0], 32); in SipHash_Rounds()
[all …]
/linux/drivers/pci/controller/
H A Dpci-thunder-ecam.c16 static void set_val(u32 v, int where, int size, u32 *val) in set_val() argument
18 int shift = (where & 3) * 8; in set_val()
20 pr_debug("set_val %04x: %08x\n", (unsigned int)(where & ~3), v); in set_val()
21 v >>= shift; in set_val()
23 v &= 0xff; in set_val()
25 v &= 0xffff; in set_val()
26 *val = v; in set_val()
33 u32 v; in handle_ea_bar() local
35 /* Entries are 16-byte aligned; bits[2,3] select word in entry */ in handle_ea_bar()
47 v = readl(addr); in handle_ea_bar()
[all …]
/linux/drivers/staging/media/sunxi/sun6i-isp/
H A Dsun6i_isp_reg.h21 #define SUN6I_ISP_FE_CFG_SRC0_MODE(v) (((v) << 8) & GENMASK(9, 8)) argument
22 #define SUN6I_ISP_FE_CFG_SRC1_MODE(v) (((v) << 16) & GENMASK(17, 16)) argument
28 #define SUN6I_ISP_FE_CTRL_LUT_UPDATE BIT(3)
33 #define SUN6I_ISP_FE_CTRL_OUTPUT_SPEED_CTRL(v) (((v) << 16) & GENMASK(17, 16)) argument
40 #define SUN6I_ISP_FE_INT_EN_PARA_LOAD BIT(3)
51 #define SUN6I_ISP_FE_INT_STA_PARA_LOAD BIT(3)
81 #define SUN6I_ISP_MODULE_EN_DPC_OTF BIT(3)
104 #define SUN6I_ISP_MODE_INPUT_FMT(v) ((v) & GENMASK(2, 0)) argument
105 #define SUN6I_ISP_MODE_INPUT_YUV_SEQ(v) (((v) << 3) & GENMASK(4, 3)) argument
106 #define SUN6I_ISP_MODE_OTF_DPC(v) (((v) << 16) & BIT(16)) argument
[all …]
/linux/tools/testing/selftests/rseq/
H A Drseq-arm64-bits.h15 int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_storev)(intptr_t *v, intptr_t expect, intptr_t newv, int c… in RSEQ_TEMPLATE_IDENTIFIER()
20 RSEQ_ASM_DEFINE_TABLE(1, 2f, 3f, 4f) in RSEQ_TEMPLATE_IDENTIFIER()
28 RSEQ_INJECT_ASM(3) in RSEQ_TEMPLATE_IDENTIFIER()
29 RSEQ_ASM_OP_CMPEQ(v, expect, %l[cmpfail]) in RSEQ_TEMPLATE_IDENTIFIER()
33 RSEQ_ASM_OP_CMPEQ(v, expect, %l[error2]) in RSEQ_TEMPLATE_IDENTIFIER()
35 RSEQ_ASM_OP_FINAL_STORE(newv, v, 3) in RSEQ_TEMPLATE_IDENTIFIER()
42 [v] "Qo" (*v), in RSEQ_TEMPLATE_IDENTIFIER()
72 int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpnev_storeoffp_load)(intptr_t *v, intptr_t expectnot, in RSEQ_TEMPLATE_IDENTIFIER()
78 RSEQ_ASM_DEFINE_TABLE(1, 2f, 3f, 4f) in RSEQ_TEMPLATE_IDENTIFIER()
86 RSEQ_INJECT_ASM(3) in RSEQ_TEMPLATE_IDENTIFIER()
[all …]
H A Drseq-riscv-bits.h9 int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_storev)(intptr_t *v, intptr_t expect, intptr_t newv, int c… in RSEQ_TEMPLATE_IDENTIFIER()
13 __asm__ __volatile__ goto(RSEQ_ASM_DEFINE_TABLE(1, 2f, 3f, 4f) in RSEQ_TEMPLATE_IDENTIFIER()
21 RSEQ_INJECT_ASM(3) in RSEQ_TEMPLATE_IDENTIFIER()
22 RSEQ_ASM_OP_CMPEQ(v, expect, "%l[cmpfail]") in RSEQ_TEMPLATE_IDENTIFIER()
26 RSEQ_ASM_OP_CMPEQ(v, expect, "%l[error2]") in RSEQ_TEMPLATE_IDENTIFIER()
28 RSEQ_ASM_OP_FINAL_STORE(newv, v, 3) in RSEQ_TEMPLATE_IDENTIFIER()
35 [v] "m" (*v), in RSEQ_TEMPLATE_IDENTIFIER()
62 int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpnev_storeoffp_load)(intptr_t *v, intptr_t expectnot, in RSEQ_TEMPLATE_IDENTIFIER()
67 __asm__ __volatile__ goto(RSEQ_ASM_DEFINE_TABLE(1, 2f, 3f, 4f) in RSEQ_TEMPLATE_IDENTIFIER()
75 RSEQ_INJECT_ASM(3) in RSEQ_TEMPLATE_IDENTIFIER()
[all …]
H A Drseq-ppc-bits.h15 int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_storev)(intptr_t *v, intptr_t expect, intptr_t newv, int c… in RSEQ_TEMPLATE_IDENTIFIER()
20 RSEQ_ASM_DEFINE_TABLE(3, 1f, 2f, 4f) /* start, commit, abort */ in RSEQ_TEMPLATE_IDENTIFIER()
27 RSEQ_ASM_STORE_RSEQ_CS(1, 3b, rseq_cs) in RSEQ_TEMPLATE_IDENTIFIER()
30 RSEQ_INJECT_ASM(3) in RSEQ_TEMPLATE_IDENTIFIER()
31 /* cmp @v equal to @expect */ in RSEQ_TEMPLATE_IDENTIFIER()
32 RSEQ_ASM_OP_CMPEQ(v, expect, %l[cmpfail]) in RSEQ_TEMPLATE_IDENTIFIER()
37 /* cmp @v equal to @expect */ in RSEQ_TEMPLATE_IDENTIFIER()
38 RSEQ_ASM_OP_CMPEQ(v, expect, %l[error2]) in RSEQ_TEMPLATE_IDENTIFIER()
41 RSEQ_ASM_OP_FINAL_STORE(newv, v, 2) in RSEQ_TEMPLATE_IDENTIFIER()
48 [v] "m" (*v), in RSEQ_TEMPLATE_IDENTIFIER()
[all …]
H A Drseq-x86-bits.h16 int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_storev)(intptr_t *v, intptr_t expect, intptr_t newv, int c… in RSEQ_TEMPLATE_IDENTIFIER()
21 RSEQ_ASM_DEFINE_TABLE(3, 1f, 2f, 4f) /* start, commit, abort */ in RSEQ_TEMPLATE_IDENTIFIER()
28 RSEQ_ASM_STORE_RSEQ_CS(1, 3b, RSEQ_ASM_TP_SEGMENT:RSEQ_CS_OFFSET(%[rseq_offset])) in RSEQ_TEMPLATE_IDENTIFIER()
30 RSEQ_INJECT_ASM(3) in RSEQ_TEMPLATE_IDENTIFIER()
31 "cmpq %[v], %[expect]\n\t" in RSEQ_TEMPLATE_IDENTIFIER()
36 "cmpq %[v], %[expect]\n\t" in RSEQ_TEMPLATE_IDENTIFIER()
40 "movq %[newv], %[v]\n\t" in RSEQ_TEMPLATE_IDENTIFIER()
47 [v] "m" (*v), in RSEQ_TEMPLATE_IDENTIFIER()
77 * Compare @v against @expectnot. When it does _not_ match, load @v
78 * into @load, and store the content of *@v + voffp into @v.
[all …]
/linux/Documentation/fb/
H A Dviafb.modes29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
33 geometry 480 640 480 640 32 timings 39722 72 24 19 1 48 3 endmode
41 # 8 chars 3 lines
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
54 geometry 640 480 640 480 32 timings 31747 120 16 16 1 64 3 endmode
62 # 7 chars 3 lines
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
75 geometry 640 480 640 480 32 timings 27777 80 56 25 1 56 3 endmode
83 # 8 chars 3 lines
[all …]
/linux/tools/testing/selftests/kvm/aarch64/
H A Dvgic_init.c77 struct vm_gic v; in vm_gic_create_with_vcpus() local
79 v.gic_dev_type = gic_dev_type; in vm_gic_create_with_vcpus()
80 v.vm = vm_create_with_vcpus(nr_vcpus, guest_code, vcpus); in vm_gic_create_with_vcpus()
81 v.gic_fd = kvm_create_device(v.vm, gic_dev_type); in vm_gic_create_with_vcpus()
83 return v; in vm_gic_create_with_vcpus()
88 struct vm_gic v; in vm_gic_create_barebones() local
90 v.gic_dev_type = gic_dev_type; in vm_gic_create_barebones()
91 v.vm = vm_create_barebones(); in vm_gic_create_barebones()
92 v.gic_fd = kvm_create_device(v.vm, gic_dev_type); in vm_gic_create_barebones()
94 return v; in vm_gic_create_barebones()
[all …]
/linux/arch/arm/include/asm/
H A Datomic.h25 #define arch_atomic_read(v) READ_ONCE((v)->counter) argument
26 #define arch_atomic_set(v,i) WRITE_ONCE(((v)->counter), (i)) argument
37 static inline void arch_atomic_##op(int i, atomic_t *v) \
42 prefetchw(&v->counter); \
44 "1: ldrex %0, [%3]\n" \
46 " strex %1, %0, [%3]\n" \
49 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter) \
50 : "r" (&v->counter), "Ir" (i) \
55 static inline int arch_atomic_##op##_return_relaxed(int i, atomic_t *v) \
60 prefetchw(&v->counter); \
[all …]
/linux/arch/arm/crypto/
H A Dblake2s-core.S113 // Execute one round of BLAKE2s by updating the state matrix v[0..15]. v[0..9]
115 // spilling v[8..9], then to v[9..15], then to the message block. r10-r12 and
132 // (v[0], v[4], v[8], v[12]) and (v[1], v[5], v[9], v[13]).
133 __ldrd r10, r11, sp, 16 // load v[12] and v[13]
140 // (v[2], v[6], v[10], v[14]) and (v[3], v[7], v[11], v[15]).
141 __ldrd r8, r9, sp, 8 // load v[10] and v[11]
142 __ldrd r10, r11, sp, 24 // load v[14] and v[15]
145 str r10, [sp, #24] // store v[14]
146 // v[10], v[11], and v[15] are used below, so no need to store them yet.
152 // (v[0], v[5], v[10], v[15]) and (v[1], v[6], v[11], v[12]).
[all …]
H A Dblake2b-neon-core.S53 .byte 3, 4, 5, 6, 7, 0, 1, 2
55 .byte 2, 3, 4, 5, 6, 7, 0, 1
63 // Execute one round of BLAKE2b by updating the state matrix v[0..15] in the
73 // (v[0], v[4], v[8], v[12]), (v[1], v[5], v[9], v[13]),
74 // (v[2], v[6], v[10], v[14]), and (v[3], v[7], v[11], v[15]).
145 // (v[0], v[5], v[10], v[15]), (v[1], v[6], v[11], v[12]),
146 // (v[2], v[7], v[8], v[13]), and (v[3], v[4], v[9], v[14]).
259 vld1.64 {q0-q1}, [ip]! // Load h[0..3]
264 vld1.64 {q4-q5}, [r10]! // Load IV[0..3]
274 // 'v'. Fortunately, there are exactly enough NEON registers to fit the
[all …]
/linux/drivers/i3c/master/mipi-i3c-hci/
H A Dcmd_v2.c1 // SPDX-License-Identifier: BSD-3-Clause
26 #define CMD_U3_HDR_TSP_ML_CTRL(v) FIELD_PREP(W3_MASK(107, 104), v) argument
27 #define CMD_U3_IDB4(v) FIELD_PREP(W3_MASK(103, 96), v) argument
28 #define CMD_U3_HDR_CMD(v) FIELD_PREP(W3_MASK(103, 96), v) argument
29 #define CMD_U2_IDB3(v) FIELD_PREP(W2_MASK( 95, 88), v) argument
30 #define CMD_U2_HDR_BT(v) FIELD_PREP(W2_MASK( 95, 88), v) argument
31 #define CMD_U2_IDB2(v) FIELD_PREP(W2_MASK( 87, 80), v) argument
32 #define CMD_U2_BT_CMD2(v) FIELD_PREP(W2_MASK( 87, 80), v) argument
33 #define CMD_U2_IDB1(v) FIELD_PREP(W2_MASK( 79, 72), v) argument
34 #define CMD_U2_BT_CMD1(v) FIELD_PREP(W2_MASK( 79, 72), v) argument
[all …]
/linux/tools/testing/selftests/net/forwarding/
H A Dip6gre_custom_multipath_hash.sh24 # | loc=2001:db8:3::1 |
25 # | rem=2001:db8:3::2 -. |
27 # | v |
62 # | loc=2001:db8:3::2 | |
63 # | rem=2001:db8:3::1 -' |
90 ip route add vrf v$h1 default via 198.51.100.1 dev $h1
91 ip -6 route add vrf v$h1 default via 2001:db8:1::1 dev $h1
96 ip -6 route del vrf v$h1 default
97 ip route del vrf v$h1 default
104 __simple_if_init $ul1 v$ol1 2001:db8:10::1/64
[all …]
H A Dip6gre_lib.sh25 # | loc=2001:db8:3::1 |
26 # | rem=2001:db8:3::2 --. |
31 # | v |
52 # | loc=2001:db8:3::2 | |
53 # | rem=2001:db8:3::1 --' |
58 # | VRF v$ol2 | 2001:db8:2::2/64 |
85 # | | loc=2001:db8:3::1 | |
86 # | | rem=2001:db8:3::2 | |
89 # | | VRF v$ol1 | | |
93 # | | VRF v$ul1 | | |
[all …]
/linux/sound/soc/codecs/
H A Dcs43130.h45 #define CS43130_PLL_SET_3 0x030003 /* PLL Setting 3 */
88 #define CS43130_DSD_PATH_CTL_3 0x070006 /* DSD Proc Path Sig Ctl 3 */
119 #define CS43130_INT_STATUS_3 0x0F0002 /* Interrupt Status 3 */
124 #define CS43130_INT_MASK_3 0x0F0012 /* Interrupt Mask 3 */
152 #define CS43130_XTAL_ERR_INT_SHIFT 3
166 #define CS43130_HPLOAD_AC_INT_SHIFT 3
205 #define CS43130_SP_5050_SHIFT 3
211 #define CS43130_SP_SCPOL_OUT_SHIFT 3
229 #define CS43130_PDN_XTAL_SHIFT 3
236 #define CS43130_HP_IN_EN_SHIFT 3
[all …]
/linux/arch/powerpc/include/asm/
H A Datomic.h27 static __inline__ int arch_atomic_read(const atomic_t *v) in arch_atomic_read() argument
33 __asm__ __volatile__("lwz %0,0(%1)" : "=r"(t) : "b"(&v->counter)); in arch_atomic_read()
35 __asm__ __volatile__("lwz%U1%X1 %0,%1" : "=r"(t) : "m<>"(v->counter)); in arch_atomic_read()
40 static __inline__ void arch_atomic_set(atomic_t *v, int i) in arch_atomic_set() argument
44 __asm__ __volatile__("stw %1,0(%2)" : "=m"(v->counter) : "r"(i), "b"(&v->counter)); in arch_atomic_set()
46 __asm__ __volatile__("stw%U0%X0 %1,%0" : "=m<>"(v->counter) : "r"(i)); in arch_atomic_set()
50 static __inline__ void arch_atomic_##op(int a, atomic_t *v) \
55 "1: lwarx %0,0,%3 # atomic_" #op "\n" \
57 " stwcx. %0,0,%3 \n" \
59 : "=&r" (t), "+m" (v->counter) \
[all …]
/linux/arch/alpha/include/asm/
H A Datomic.h29 #define arch_atomic_read(v) READ_ONCE((v)->counter) argument
30 #define arch_atomic64_read(v) READ_ONCE((v)->counter) argument
32 #define arch_atomic_set(v,i) WRITE_ONCE((v)->counter, (i)) argument
33 #define arch_atomic64_set(v,i) WRITE_ONCE((v)->counter, (i)) argument
42 static __inline__ void arch_atomic_##op(int i, atomic_t * v) \
53 :"=&r" (temp), "=m" (v->counter) \
54 :"Ir" (i), "m" (v->counter)); \
58 static inline int arch_atomic_##op##_return_relaxed(int i, atomic_t *v) \
63 " " #asm_op " %0,%3,%2\n" \
64 " " #asm_op " %0,%3,%0\n" \
[all …]

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