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/linux/drivers/net/wireless/mediatek/mt76/mt7615/
H A Dmac.h1 /* SPDX-License-Identifier: ISC */
15 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
16 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
17 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
18 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
19 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
20 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
23 #define MT_RXD1_NORMAL_PAYLOAD_FORMAT GENMASK(25, 24)
25 #define MT_RXD1_MID_AMSDU_FRAME BIT(1)
26 #define MT_RXD1_LAST_AMSDU_FRAME BIT(0)
[all …]
/linux/drivers/net/wireless/mediatek/mt76/
H A Dmt76_connac2_mac.h1 /* SPDX-License-Identifier: ISC */
46 #define MT_TX_FREE_PAIR BIT(31)
51 #define MT_TXD0_PKT_FMT GENMASK(24, 23)
55 #define MT_TXD1_LONG_FORMAT BIT(31)
56 #define MT_TXD1_TGID BIT(30)
57 #define MT_TXD1_OWN_MAC GENMASK(29, 24)
58 #define MT_TXD1_AMSDU BIT(23)
63 #define MT_TXD1_ETH_802_3 BIT(15)
64 #define MT_TXD1_VTA BIT(10)
67 #define MT_TXD2_FIX_RATE BIT(31)
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/linux/drivers/staging/sm750fb/
H A Dsm750_accel.h1 /* SPDX-License-Identifier: GPL-2.0 */
25 #define DE_SOURCE_WRAP BIT(31)
32 #define DE_DESTINATION_WRAP BIT(31)
43 #define DE_CONTROL_STATUS BIT(31)
44 #define DE_CONTROL_PATTERN BIT(30)
45 #define DE_CONTROL_UPDATE_DESTINATION_X BIT(29)
46 #define DE_CONTROL_QUICK_START BIT(28)
47 #define DE_CONTROL_DIRECTION BIT(27)
48 #define DE_CONTROL_MAJOR BIT(26)
49 #define DE_CONTROL_STEP_X BIT(25)
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H A Dddk750_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 #define DE_STATE1_DE_ABORT BIT(0)
10 #define DE_STATE2_DE_FIFO_EMPTY BIT(3)
11 #define DE_STATE2_DE_STATUS_BUSY BIT(2)
12 #define DE_STATE2_DE_MEM_FIFO_EMPTY BIT(1)
20 #define SYSTEM_CTRL_PCI_BURST BIT(29)
21 #define SYSTEM_CTRL_PCI_MASTER BIT(25)
22 #define SYSTEM_CTRL_LATENCY_TIMER_OFF BIT(24)
23 #define SYSTEM_CTRL_DE_FIFO_EMPTY BIT(23)
24 #define SYSTEM_CTRL_DE_STATUS_BUSY BIT(22)
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/linux/drivers/gpu/drm/mxsfb/
H A Dlcdif_regs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
39 #define CTRL_SFTRST BIT(31)
40 #define CTRL_CLKGATE BIT(30)
41 #define CTRL_BYPASS_COUNT BIT(19)
42 #define CTRL_VSYNC_MODE BIT(18)
43 #define CTRL_DOTCLK_MODE BIT(17)
44 #define CTRL_DATA_SELECT BIT(16)
54 #define CTRL_MASTER BIT(5)
55 #define CTRL_DF16 BIT(3)
56 #define CTRL_DF18 BIT(2)
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/linux/drivers/clk/sunxi-ng/
H A Dccu-sun6i-a31.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
7 * Based on ccu-sun8i-h3.c by Maxime Ripard.
10 #include <linux/clk-provider.h>
30 #include "ccu-sun6i-a31.h"
32 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu",
37 BIT(31), /* gate */
38 BIT(28), /* lock */
46 * With sigma-delta modulation for fractional-N on the audio PLL,
[all …]
H A Dccu-sun50i-h6.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
23 #include "ccu-sun50i-h6.h"
37 .enable = BIT(31),
38 .lock = BIT(28),
42 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
51 .enable = BIT(31),
52 .lock = BIT(28),
58 .hw.init = CLK_HW_INIT("pll-ddr0", "osc24M",
66 .enable = BIT(31),
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H A Dccu-sun20i-d1.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
26 #include "ccu-sun20i-d1.h"
38 .enable = BIT(27),
39 .lock = BIT(28),
43 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-cpux", osc24M,
52 .enable = BIT(27),
53 .lock = BIT(28),
59 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-ddr0", osc24M,
67 .enable = BIT(27),
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H A Dccu-sun55i-a523.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2023-2024 Arm Ltd.
9 #include <linux/clk-provider.h>
14 #include <dt-bindings/clock/sun55i-a523-ccu.h>
15 #include <dt-bindings/reset/sun55i-a523-ccu.h>
32 * The 24 MHz oscillator, the root of most of the clock tree.
33 * .fw_name is the string used in the DT "clock-names" property, used to
47 .enable = BIT(27),
48 .lock = BIT(28),
54 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-ddr0", osc24M,
[all …]
H A Dccu-sun50i-a100.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
23 #include "ccu-sun50i-a100.h"
25 #define SUN50I_A100_PLL_SDM_ENABLE BIT(24)
26 #define SUN50I_A100_PLL_OUTPUT_ENABLE BIT(27)
27 #define SUN50I_A100_PLL_LOCK BIT(28)
28 #define SUN50I_A100_PLL_LOCK_ENABLE BIT(29)
29 #define SUN50I_A100_PLL_ENABLE BIT(31)
50 .hw.init = CLK_HW_INIT("pll-cpux", "dcxo24M",
66 .hw.init = CLK_HW_INIT("pll-ddr0", "dcxo24M",
[all …]
H A Dccu-sun9i-a80.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved.
6 #include <linux/clk-provider.h>
21 #include "ccu-sun9i-a80.h"
28 * Neither mainline Linux, U-boot, nor the vendor BSPs use these.
36 .enable = BIT(31),
37 .lock = BIT(0),
43 .hw.init = CLK_HW_INIT("pll-c0cpux", "osc24M",
50 .enable = BIT(31),
51 .lock = BIT(1),
[all …]
H A Dccu-sun50i-h616.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
25 #include "ccu-sun50i-h616.h"
39 .enable = BIT(31),
40 .lock = BIT(28),
44 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
53 .enable = BIT(31),
54 .lock = BIT(28),
60 .hw.init = CLK_HW_INIT("pll-ddr0", "osc24M",
68 .enable = BIT(31),
[all …]
H A Dccu-sun8i-a33.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
24 #include "ccu-sun8i-a23-a33.h"
27 .enable = BIT(31),
28 .lock = BIT(28),
37 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
48 * With sigma-delta modulation for fractional-N on the audio PLL,
62 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
66 pll_audio_sdm_table, BIT(24),
67 0x284, BIT(31),
[all …]
H A Dccu-sun4i-a10.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
28 #include "ccu-sun4i-a10.h"
31 .enable = BIT(31),
38 .hw.init = CLK_HW_INIT("pll-core",
50 * With sigma-delta modulation for fractional-N on the audio PLL,
65 .enable = BIT(31),
69 0x00c, BIT(31)),
73 .hw.init = CLK_HW_INIT("pll-audio-base",
82 .enable = BIT(31),
[all …]
H A Dccu-sun8i-a23.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
25 #include "ccu-sun8i-a23-a33.h"
29 .enable = BIT(31),
30 .lock = BIT(28),
39 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
50 * With sigma-delta modulation for fractional-N on the audio PLL,
64 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
68 pll_audio_sdm_table, BIT(24),
69 0x284, BIT(31),
[all …]
/linux/sound/soc/mediatek/mt8186/
H A Dmt8186-reg.h1 /* SPDX-License-Identifier: GPL-2.0
3 * mt8186-reg.h -- Mediatek 8186 audio driver reg definition
12 /* reg bit enum */
26 #define RESERVED_MASK_SFT BIT(31)
28 #define AHB_IDLE_EN_INT_MASK_SFT BIT(30)
30 #define AHB_IDLE_EN_EXT_MASK_SFT BIT(29)
32 #define PDN_NLE_MASK_SFT BIT(28)
34 #define PDN_TML_MASK_SFT BIT(27)
36 #define PDN_DAC_PREDIS_MASK_SFT BIT(26)
38 #define PDN_DAC_MASK_SFT BIT(25)
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/linux/arch/alpha/lib/
H A Ddivide.S1 /* SPDX-License-Identifier: GPL-2.0 */
14 * __divqu: 64-bit unsigned long divide
15 * __remqu: 64-bit unsigned long remainder
16 * __divqs/__remqs: signed 64-bit
17 * __divlu/__remlu: unsigned 32-bit
18 * __divls/__remls: signed 32-bit
22 * $24 and $25, and return the result in $27. Register $28 may
27 * This is a rather simple bit-at-a-time algorithm: it's very good
28 * at dividing random 64-bit numbers, but the more usual case where
37 * $0 - current bit
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H A Dev6-divide.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-divide.S
5 * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
14 * __divqu: 64-bit unsigned long divide
15 * __remqu: 64-bit unsigned long remainder
16 * __divqs/__remqs: signed 64-bit
17 * __divlu/__remlu: unsigned 32-bit
18 * __divls/__remls: signed 32-bit
22 * $24 and $25, and return the result in $27. Register $28 may
27 * This is a rather simple bit-at-a-time algorithm: it's very good
[all …]
/linux/include/linux/mfd/syscon/
H A Dimx6q-iomuxc-gpr.h1 /* SPDX-License-Identifier: GPL-2.0-only */
40 #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_MASK (0x3 << 24)
41 #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7_MUXED (0x3 << 24)
42 #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7 (0x3 << 24)
43 #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_SSI3_SSI_SRCK (0x3 << 24)
44 #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_SSI3_RX_BIT_CLK (0x3 << 24)
69 #define IMX6Q_GPR0_DMAREQ_MUX_SEL7_MASK BIT(7)
71 #define IMX6Q_GPR0_DMAREQ_MUX_SEL7_IOMUX BIT(7)
72 #define IMX6Q_GPR0_DMAREQ_MUX_SEL6_MASK BIT(6)
74 #define IMX6Q_GPR0_DMAREQ_MUX_SEL6_I2C3 BIT(6)
[all …]
/linux/drivers/gpu/drm/tve200/
H A Dtve200_drm.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * Copyright (C) 2006-2008 Intel Corporation
28 /* Bits 2-31 are valid physical base addresses */
36 #define TVE200_INT_BUS_ERR BIT(7)
37 #define TVE200_INT_V_STATUS BIT(6) /* vertical blank */
38 #define TVE200_INT_V_NEXT_FRAME BIT(5)
39 #define TVE200_INT_U_NEXT_FRAME BIT(4)
40 #define TVE200_INT_Y_NEXT_FRAME BIT(3)
41 #define TVE200_INT_V_FIFO_UNDERRUN BIT(2)
42 #define TVE200_INT_U_FIFO_UNDERRUN BIT(1)
[all …]
/linux/drivers/gpu/drm/vc4/
H A Dvc4_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2014-2015 Broadcom
24 WARN_ON(!FIELD_FIT(hvs->vc4->gen == VC4_GEN_6_C ? \
27 FIELD_PREP(hvs->vc4->gen == VC4_GEN_6_C ? \
32 #define VC6_GET_FIELD(word, field) FIELD_GET(hvs->vc4->gen == VC4_GEN_6_C ? \
38 ((2 << 24) | \
61 # define V3D_L2CACTL_L2CCLR BIT(2)
62 # define V3D_L2CACTL_L2CDIS BIT(1)
63 # define V3D_L2CACTL_L2CENA BIT(0)
66 # define V3D_SLCACTL_T1CC_MASK VC4_MASK(27, 24)
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/linux/drivers/net/ethernet/amazon/ena/
H A Dena_eth_io_defs.h1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
3 * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved.
24 /* 15:0 : length - Buffer length in bytes, must
26 * to update like End-to-End CRC, Authentication GMAC
29 * the 4-byte added in the end for 802.3 Ethernet FCS
30 * 21:16 : req_id_hi - Request ID[15:10]
31 * 22 : reserved22 - MBZ
32 * 23 : meta_desc - MBZ
33 * 24 : phase
34 * 25 : reserved1 - MBZ
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/linux/drivers/net/phy/mscc/
H A Dmscc_macsec.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
17 #define CONTROL_IV0 BIT(5)
18 #define CONTROL_IV1 BIT(6)
19 #define CONTROL_IV2 BIT(7)
20 #define CONTROL_UPDATE_SEQ BIT(13)
21 #define CONTROL_IV_IN_SEQ BIT(14)
22 #define CONTROL_ENCRYPT_AUTH BIT(15)
23 #define CONTROL_KEY_IN_CTX BIT(16)
33 #define CONTROL_SEQ_MASK BIT(30)
34 #define CONTROL_CONTEXT_ID BIT(31)
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/linux/drivers/net/wireless/mediatek/mt76/mt7603/
H A Dmac.h1 /* SPDX-License-Identifier: ISC */
10 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
11 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
12 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
13 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
14 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
15 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
28 #define MT_RXD1_NORMAL_PAYLOAD_FORMAT GENMASK(25, 24)
29 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
30 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
[all …]
/linux/sound/soc/fsl/
H A Dfsl_sai.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright 2012-2013 Freescale Semiconductor, Inc.
9 #include <linux/dma/imx-dma.h>
49 #define FSL_SAI_TBCTN 0x78 /* SAI Transmit Bit Counter Register */
76 #define FSL_SAI_RBCTN 0xf8 /* SAI Receive Bit Counter Register */
93 #define FSL_SAI_CSR_TERE BIT(31)
94 #define FSL_SAI_CSR_SE BIT(30)
95 #define FSL_SAI_CSR_BCE BIT(28)
96 #define FSL_SAI_CSR_FR BIT(25)
97 #define FSL_SAI_CSR_SR BIT(24)
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