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Searched +full:18 +full:bpp (Results 1 – 25 of 177) sorted by relevance

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/linux/include/video/
H A Dsh_mobile_lcdc.h75 #define LDDFR_CF1 (1 << 18)
105 RGB8 = LDMT1R_MIFTYP_RGB8, /* 24bpp, 8:8:8 */
106 RGB9 = LDMT1R_MIFTYP_RGB9, /* 18bpp, 9:9 */
107 RGB12A = LDMT1R_MIFTYP_RGB12A, /* 24bpp, 12:12 */
108 RGB12B = LDMT1R_MIFTYP_RGB12B, /* 12bpp */
109 RGB16 = LDMT1R_MIFTYP_RGB16, /* 16bpp */
110 RGB18 = LDMT1R_MIFTYP_RGB18, /* 18bpp */
111 RGB24 = LDMT1R_MIFTYP_RGB24, /* 24bpp */
112 YUV422 = LDMT1R_MIFTYP_YCBCR, /* 16bpp */
113 SYS8A = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8A, /* 24bpp, 8:8:8 */
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/linux/drivers/gpu/drm/display/
H A Ddrm_dsc_helper.c166 /* PPS 18, 19 */ in drm_dsc_pps_payload_pack()
321 * For 6bpp, RC Buffer threshold 12 and 13 need a different value in drm_dsc_set_rc_buf_thresh()
343 u8 bpp; member
348 #define DSC_BPP(bpp) ((bpp) << 4) argument
352 * to DSC 1.1 fractional bpp underflow SCR (DSC_v1.1_E1.pdf)
358 .bpp = DSC_BPP(6), .bpc = 8,
368 .bpp = DSC_BPP(8), .bpc = 8,
378 .bpp = DSC_BPP(8), .bpc = 10,
392 .bpp = DSC_BPP(8), .bpc = 12,
396 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
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/linux/Documentation/fb/
H A Darkfb.rst19 * 4 bpp pseudocolor modes (with 18bit palette, two variants)
20 * 8 bpp pseudocolor mode (with 18bit palette)
21 * 16 bpp truecolor modes (RGB 555 and RGB 565)
22 * 24 bpp truecolor mode (RGB 888)
23 * 32 bpp truecolor mode (RGB 888)
24 * text mode (activated by bpp = 0)
36 There are two 4 bpp modes. First mode (selected if nonstd == 0) is mode with
54 * support for fontwidths != 8 in 4 bpp modes
H A Ds3fb.rst26 * 4 bpp pseudocolor modes (with 18bit palette, two variants)
27 * 8 bpp pseudocolor mode (with 18bit palette)
28 * 16 bpp truecolor modes (RGB 555 and RGB 565)
29 * 24 bpp truecolor mode (RGB 888) on (only on Virge VX)
30 * 32 bpp truecolor mode (RGB 888) on (not on Virge VX)
31 * text mode (activated by bpp = 0)
45 There are two 4 bpp modes. First mode (selected if nonstd == 0) is mode with
62 * 24 bpp mode support on more cards
63 * support for fontwidths != 8 in 4 bpp modes
H A Dvt8623fb.rst18 * 4 bpp pseudocolor modes (with 18bit palette, two variants)
19 * 8 bpp pseudocolor mode (with 18bit palette)
20 * 16 bpp truecolor mode (RGB 565)
21 * 32 bpp truecolor mode (RGB 888)
22 * text mode (activated by bpp = 0)
33 There are two 4 bpp modes. First mode (selected if nonstd == 0) is mode with
49 * support for fontwidths != 8 in 4 bpp modes
/linux/drivers/gpu/drm/gma500/
H A Doaktrail.h76 struct oaktrail_timing_info DTD;/*18 bytes, Standard definition */
89 /* Bit0: 16bpp (not supported in LNC), */
90 /* Bit1: 18bpp loosely packed, */
91 /* Bit2: 18bpp packed, */
92 /* Bit3: 24bpp */
105 struct oaktrail_timing_info DTD;/*18 bytes, Standard definition */
119 /* Bit0: 16bpp (not supported in LNC), */
120 /* Bit1: 18bpp loosely packed, */
121 /* Bit2: 18bpp packed, */
122 /* Bit3: 24bpp */
H A Dintel_bios.c55 dev_priv->edp.bpp = 18; in parse_edp()
59 dev_priv->edp.bpp); in parse_edp()
67 dev_priv->edp.bpp = 18; in parse_edp()
70 dev_priv->edp.bpp = 24; in parse_edp()
73 dev_priv->edp.bpp = 30; in parse_edp()
102 DRM_DEBUG_KMS("VBT reports EDP: Lane_count %d, Lane_rate %d, Bpp %d\n", in parse_edp()
103 dev_priv->edp.lanes, dev_priv->edp.rate, dev_priv->edp.bpp); in parse_edp()
/linux/drivers/gpu/drm/msm/disp/mdp4/
H A Dmdp4_lcdc_encoder.c52 int bpp, nchan, swap; in setup_phy() local
57 bpp = 3 * connector->display_info.bpc; in setup_phy()
59 if (!bpp) in setup_phy()
60 bpp = 18; in setup_phy()
66 switch (bpp) { in setup_phy()
121 case 18: in setup_phy()
165 DRM_DEV_ERROR(dev->dev, "unknown bpp: %d\n", bpp); in setup_phy()
310 /* TODO: hard-coded for 18bpp: */ in mdp4_lcdc_encoder_enable()
/linux/drivers/gpu/drm/i915/display/
H A Dintel_vdsc.c57 int bpp) in intel_vdsc_set_min_max_qp() argument
63 intel_lookup_range_min_qp(bpc, buf, bpp, vdsc_cfg->native_420); in intel_vdsc_set_min_max_qp()
65 intel_lookup_range_max_qp(bpc, buf, bpp, vdsc_cfg->native_420); in intel_vdsc_set_min_max_qp()
80 int bpp = fxp_q4_to_int(vdsc_cfg->bits_per_pixel); in calculate_rc_params() local
95 uncompressed_bpg_rate - 3 * bpp); in calculate_rc_params()
120 if (bpp >= 12) in calculate_rc_params()
122 else if (bpp >= 10) in calculate_rc_params()
123 vdsc_cfg->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2); in calculate_rc_params()
124 else if (bpp >= 8) in calculate_rc_params()
125 vdsc_cfg->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2); in calculate_rc_params()
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H A Dintel_qp_tables.c11 /* from BPP 6 to 24 in steps of 0.5 */
14 /* from BPP 6 to 30 in steps of 0.5 */
17 /* from BPP 6 to 36 in steps of 0.5 */
21 * is double the target bpp. The below values represent
22 * the target bpp.
24 /* from BPP 4 to 12 in steps of 0.5 */
27 /* from BPP 4 to 15 in steps of 0.5 */
30 /* from BPP 4 to 18 in steps of 0.5 */
147 { 18, 18, 17, 17, 16, 16, 16, 16, 15, 15, 14, 14, 14, 14, 13, 13, 13,
195 { 19, 19, 18, 18, 17, 17, 17, 17, 16, 16, 15, 15, 15, 15, 14, 14, 14,
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/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_dsc_1_2.c97 u32 bpp; in dpu_hw_dsc_config_1_2() local
125 data |= (_dsc_calc_output_buf_max_addr(hw_dsc, num_active_slice_per_enc) << 18); in dpu_hw_dsc_config_1_2()
137 bpp = dsc->bits_per_pixel; in dpu_hw_dsc_config_1_2()
138 /* as per hw requirement bpp should be programmed in dpu_hw_dsc_config_1_2()
142 bpp = 2 * bpp; in dpu_hw_dsc_config_1_2()
144 data |= bpp << 10; in dpu_hw_dsc_config_1_2()
304 (rc[3].range_bpg_offset << 18) | in dpu_hw_dsc_config_thresh_1_2()
323 (rc[8].range_bpg_offset << 18) | in dpu_hw_dsc_config_thresh_1_2()
342 (rc[13].range_bpg_offset << 18) | in dpu_hw_dsc_config_thresh_1_2()
/linux/drivers/gpu/drm/msm/dp/
H A Ddp_link.h74 * mdss_dp_test_bit_depth_to_bpp() - convert test bit depth to bpp
77 * Returns the bits per pixel (bpp) to be used corresponding to the
91 return 18; in dp_link_bit_depth_to_bpp()
103 u32 dp_link_get_test_bits_depth(struct dp_link *dp_link, u32 bpp);
H A Ddp_panel.c94 const u32 max_supported_bpp = 30, min_supported_bpp = 18; in dp_panel_get_supported_bpp()
95 u32 bpp, data_rate_khz; in dp_panel_get_supported_bpp() local
97 bpp = min(mode_edid_bpp, max_supported_bpp); in dp_panel_get_supported_bpp()
103 if (mode_pclk_khz * bpp <= data_rate_khz) in dp_panel_get_supported_bpp()
104 return bpp; in dp_panel_get_supported_bpp()
105 bpp -= 6; in dp_panel_get_supported_bpp()
106 } while (bpp > min_supported_bpp); in dp_panel_get_supported_bpp()
179 u32 bpp; in dp_panel_get_mode_bpp() local
189 bpp = dp_link_bit_depth_to_bpp( in dp_panel_get_mode_bpp()
192 bpp = dp_panel_get_supported_bpp(dp_panel, mode_edid_bpp, in dp_panel_get_mode_bpp()
[all …]
/linux/drivers/gpu/drm/ast/
H A Dast_reg.h37 #define AST_IO_VGACRCB_HWC_16BPP BIT(0) /* set: ARGB4444, cleared: 2bpp palette */
85 * CRE0[7:0]: MISC0 ((0x00: 18-bpp) or (0x20: 24-bpp)
/linux/drivers/gpu/drm/radeon/
H A Dsi_reg.h50 /* 8 BPP */
52 /* 16 BPP */
59 /* 32 BPP */
81 # define SI_GRPH_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 18)
/linux/drivers/video/fbdev/
H A Dpxafb.c241 /* calculate pixel depth, transparency bit included, >=16bpp formats _only_ */
248 /* calculate 4-bit BPP value for LCCR3 and OVLxC1 */
251 int bpp = -EINVAL; in pxafb_var_to_bpp() local
254 case 1: bpp = 0; break; in pxafb_var_to_bpp()
255 case 2: bpp = 1; break; in pxafb_var_to_bpp()
256 case 4: bpp = 2; break; in pxafb_var_to_bpp()
257 case 8: bpp = 3; break; in pxafb_var_to_bpp()
258 case 16: bpp = 4; break; in pxafb_var_to_bpp()
261 case 18: bpp = 6; break; /* 18-bits/pixel packed */ in pxafb_var_to_bpp()
262 case 19: bpp = 8; break; /* 19-bits/pixel packed */ in pxafb_var_to_bpp()
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H A Datafb.c125 short bpp; member
221 2, 130, 66, 194, 34, 162, 98, 226, 18, 146, 82, 210, 50, 178, 114, 242,
497 "vga", 60, 640, 480, 39721, 42, 18, 31, 11, 100, 3,
501 "vga70", 70, 640, 400, 39721, 42, 18, 31, 11, 100, 3,
511 "falh", 60, 896, 608, 32000, 18, 42, 31, 1, 96,3,
583 int bpp = var->bits_per_pixel; in tt_decode_var() local
588 if (bpp > 1 || xres > sttt_xres * 2 || yres > tt_yres * 2) in tt_decode_var()
593 bpp = 1; in tt_decode_var()
595 if (bpp > 8 || xres > sttt_xres || yres > tt_yres) in tt_decode_var()
597 if (bpp > 4) { in tt_decode_var()
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H A Dau1100fb.h78 u32 bpp; /* Maximum depth supported */ member
125 #define LCD_CONTROL_SBPPF_BIT 18
202 #define LCD_CLKCONTROL_IB (1<<18)
277 .bpp = 16,
290 .bpp = 16,
301 .bpp = 16,
328 .bpp = 4,
350 .bpp = 16,
362 .bpp = 16,
H A Ds3c-fb.c116 * @valid_bpp: 1 bit per BPP setting to show valid bits-per-pixel.
118 * valid_bpp bit x is set if (x+1)BPP is supported.
225 * @bpp: The bit depth.
227 static bool s3c_fb_validate_win_bpp(struct s3c_fb_win *win, unsigned int bpp) in s3c_fb_validate_win_bpp() argument
229 return win->variant.valid_bpp & VALID_BPP(bpp); in s3c_fb_validate_win_bpp()
252 dev_dbg(sfb->dev, "win %d: unsupported bpp %d\n", in s3c_fb_check_var()
286 var->transp.offset = 18; in s3c_fb_check_var()
289 case 18: in s3c_fb_check_var()
302 /* 16 bpp, 565 format */ in s3c_fb_check_var()
318 /* our 24bpp is unpacked, so 32bpp */ in s3c_fb_check_var()
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/linux/drivers/media/platform/nxp/
H A Dimx7-media-csi.c64 #define BIT_RXFF_INTEN BIT(18)
116 #define BIT_RXFF_INT BIT(18)
130 /* csi control reg 18 */
141 #define BIT_MASK_OPTION_FIRST_FRAME (0 << 18)
142 #define BIT_MASK_OPTION_CSI_EN (1 << 18)
143 #define BIT_MASK_OPTION_SECOND_FRAME (2 << 18)
144 #define BIT_MASK_OPTION_ON_DATA (3 << 18)
200 int bpp; /* total bpp */ member
835 * in single (8bpp) or double (16bpp) component modes. Image format variants
865 .bpp = 16,
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/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_opp.c100 * 1) set truncation depth: 0 for 18 bpp or 1 for 24 bpp
145 * 1) set truncation depth: 0 for 18 bpp or 1 for 24 bpp
187 * 2) set spatial dithering depth: 0 for 18bpp or 1 for 24bpp
/linux/fs/xfs/
H A Dxfs_buf.h39 #define _XBF_LOGRECOVERY (1u << 18)/* log recovery buffer */
232 int nmaps, xfs_buf_flags_t flags, struct xfs_buf **bpp);
234 int nmaps, xfs_buf_flags_t flags, struct xfs_buf **bpp,
246 struct xfs_buf **bpp) in xfs_buf_incore() argument
250 return xfs_buf_get_map(target, &map, 1, XBF_INCORE | flags, bpp); in xfs_buf_incore()
258 struct xfs_buf **bpp) in xfs_buf_get() argument
262 return xfs_buf_get_map(target, &map, 1, 0, bpp); in xfs_buf_get()
271 struct xfs_buf **bpp, in xfs_buf_read() argument
276 return xfs_buf_read_map(target, &map, 1, flags, bpp, ops, in xfs_buf_read()
292 xfs_buf_flags_t flags, struct xfs_buf **bpp);
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/linux/drivers/gpu/drm/sun4i/
H A Dsun6i_mipi_dsi.c46 #define SUN6I_DSI_BASIC_CTL0_HS_EOTP_EN BIT(18)
215 BIT(12) | BIT(15) | BIT(18) | BIT(20) | BIT(21) | BIT(22)),
219 BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(22) | BIT(23)),
221 BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(21) | BIT(22) |
380 unsigned int Bpp = mipi_dsi_pixel_format_to_bpp(device->format) / 8; in sun6i_dsi_get_line_num() local
382 return mode->htotal * Bpp / device->lanes; in sun6i_dsi_get_line_num()
404 unsigned int Bpp = mipi_dsi_pixel_format_to_bpp(device->format) / 8; in sun6i_dsi_get_drq_edge1() local
409 edge1 += (mode->hdisplay + hbp + 20) * Bpp / device->lanes; in sun6i_dsi_get_drq_edge1()
534 int Bpp = mipi_dsi_pixel_format_to_bpp(device->format) / 8; in sun6i_dsi_setup_timings() local
543 hblk = mode->hdisplay * Bpp; in sun6i_dsi_setup_timings()
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/linux/drivers/gpu/drm/nouveau/dispnv04/
H A Dhw.h56 extern void nouveau_calc_arb(struct drm_device *, int vclk, int bpp,
367 (cre_heb & ~0x40) | ((offset >> 18) & 0x40)); in nv_set_crtc_base()
389 nv_pitch_align(struct drm_device *dev, uint32_t width, int bpp) in nv_pitch_align() argument
394 if (bpp == 15) in nv_pitch_align()
395 bpp = 16; in nv_pitch_align()
396 if (bpp == 24) in nv_pitch_align()
397 bpp = 8; in nv_pitch_align()
401 mask = 128 / bpp - 1; in nv_pitch_align()
403 mask = 512 / bpp - 1; in nv_pitch_align()
/linux/drivers/gpu/drm/bridge/cadence/
H A Dcdns-dsi-core.c47 #define DISP_EOT_GEN BIT(18)
64 #define SWAP_PINS_DAT(x) BIT(18 + ((x) * 2))
135 #define ERR_CONT_LP(x, l) BIT(18 + ((x) * 4) + (l))
147 #define PPI_C_TX_READY_HS BIT(18)
235 #define RD_DCS BIT(18)
268 #define BURST_MODE BIT(18)
475 int bpp; in cdns_dsi_mode2cfg() local
482 bpp = mipi_dsi_pixel_format_to_bpp(output->dev->format); in cdns_dsi_mode2cfg()
492 dsi_cfg->hbp = dpi_to_dsi_timing(tmp, bpp, DSI_HBP_FRAME_OVERHEAD); in cdns_dsi_mode2cfg()
500 dsi_cfg->hsa = dpi_to_dsi_timing(tmp, bpp, in cdns_dsi_mode2cfg()
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