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26 #. Increase code-reuse27 #. Increase overall code-maintainability67 for one of the users. (e.g. "git grep fsl,.*-mdio arch/powerpc/boot/dts/")72 The Reduced Gigabit Medium Independent Interface (RGMII) is a 12-pin84 or the PCB traces insert the correct 1.5-2ns delay97 * PHY devices may offer sub-nanosecond granularity in how they allow a98 receiver/transmitter side delay (e.g: 0.5, 1.0, 1.5ns) to be specified. Such115 PHY_INTERFACE_MODE_RGMII, it should make sure that the MAC-level delays are126 * Modifying the PCB design to include a fixed delay (e.g: using a specifically130 -----------------------------------------[all …]