Home
last modified time | relevance | path

Searched +full:100 +full:khz (Results 1 – 25 of 488) sorted by relevance

12345678910>>...20

/linux/Documentation/fb/
H A Dviafb.modes14 # Scan Frequency 31.469 kHz 59.94 Hz
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
39 # Scan Frequency 37.500 kHz 75.00 Hz
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
60 # Scan Frequency 43.269 kHz 85.00 Hz
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
81 # Scan Frequency 50.900 kHz 100.00 Hz
94 mode "640x480-100"
[all …]
/linux/drivers/cpufreq/
H A Dlongrun.c21 * longrun_{low,high}_freq is needed for the conversion of cpufreq kHz
56 ((longrun_high_freq - longrun_low_freq) / 100); in longrun_get_policy()
58 ((longrun_high_freq - longrun_low_freq) / 100); in longrun_get_policy()
81 pctg_lo = pctg_hi = 100; in longrun_set_policy()
84 ((longrun_high_freq - longrun_low_freq) / 100); in longrun_set_policy()
86 ((longrun_high_freq - longrun_low_freq) / 100); in longrun_set_policy()
89 if (pctg_hi > 100) in longrun_set_policy()
90 pctg_hi = 100; in longrun_set_policy()
183 *low_freq = msr_lo * 1000; /* to kHz */ in longrun_determine_freqs()
188 *high_freq = msr_lo * 1000; /* to kHz */ in longrun_determine_freqs()
[all …]
H A Dgx-suspmod.c89 #define PCI_VIDTC 0x8d /* video speedup timer counter register: typical 50 to 100ms */
132 * though. 781.25 kHz(!) for a 200 MHz processor -- wow. */
217 static unsigned int gx_validate_speed(unsigned int khz, u8 *on_duration, in gx_validate_speed() argument
229 tmp_off = ((khz * i) / stock_freq) & 0xff; in gx_validate_speed()
232 /* if this relation is closer to khz, use this. If it's equal, in gx_validate_speed()
234 if (abs(tmp_freq - khz) <= abs(old_tmp_freq - khz)) { in gx_validate_speed()
247 * set cpu speed in khz.
250 static void gx_set_cpuspeed(struct cpufreq_policy *policy, unsigned int khz) in gx_set_cpuspeed() argument
259 new_khz = gx_validate_speed(khz, &gx_params->on_duration, in gx_set_cpuspeed()
268 /* if new khz == 100% of CPU speed, it is special case */ in gx_set_cpuspeed()
[all …]
H A Dpowernow-k7.c80 70, 75, 80, 85, 90, 95, 100, 105,
377 * get a KHz value (e.g. 1266000). However, powernow-k7 works in powernow_acpi_init()
378 * with true KHz values (e.g. 1266768). To ensure that all in powernow_acpi_init()
381 * to ensure that perflib's computed KHz value is greater than in powernow_acpi_init()
382 * or equal to powernow's KHz value. in powernow_acpi_init()
478 if (latency < 100) { in powernow_decode_bios()
479 pr_info("BIOS set settling time to %d microseconds. Should be at least 100. Correcting.\n", in powernow_decode_bios()
481 latency = 100; in powernow_decode_bios()
527 * a multiple of 100000/3 khz, then we compute sgtc according
544 sgtc = 100 * m * latency; in fixup_sgtc()
/linux/drivers/video/fbdev/core/
H A Dmodedb.c39 /* 640x400 @ 70 Hz, 31.5 kHz hsync */
43 /* 640x480 @ 60 Hz, 31.5 kHz hsync */
47 /* 800x600 @ 56 Hz, 35.15 kHz hsync */
51 /* 1024x768 @ 87 Hz interlaced, 35.5 kHz hsync */
55 /* 640x400 @ 85 Hz, 37.86 kHz hsync */
59 /* 640x480 @ 72 Hz, 36.5 kHz hsync */
63 /* 640x480 @ 75 Hz, 37.50 kHz hsync */
67 /* 800x600 @ 60 Hz, 37.8 kHz hsync */
72 /* 640x480 @ 85 Hz, 43.27 kHz hsync */
76 /* 1152x864 @ 89 Hz interlaced, 44 kHz hsync */
[all …]
/linux/drivers/gpu/drm/amd/display/include/
H A Dgrph_object_ctrl_defs.h128 uint32_t pixel_clk; /* in KHz */
164 uint32_t crystal_frequency; /* in KHz */
165 uint32_t min_input_pxl_clk_pll_frequency; /* in KHz */
166 uint32_t max_input_pxl_clk_pll_frequency; /* in KHz */
167 uint32_t min_output_pxl_clk_pll_frequency; /* in KHz */
168 uint32_t max_output_pxl_clk_pll_frequency; /* in KHz */
176 uint32_t max_pixel_clock; /* in KHz */
177 uint32_t default_display_engine_pll_frequency; /* in KHz */
178 uint32_t external_clock_source_frequency_for_dp; /* in KHz */
179 uint32_t smu_gpu_pll_output_freq; /* in KHz */
[all …]
/linux/drivers/comedi/drivers/
H A Ddt2811.c74 #define DT2811_OSC_BASE 1666 /* 600 kHz = 1666.6667ns */
80 * 0 1 600 kHz 0 1
81 * 1 10 60 kHz 1 10
82 * 2 2 300 kHz 2 100
83 * 3 3 200 kHz 3 1000
84 * 4 4 150 kHz 4 10000
85 * 5 5 120 kHz 5 100000
86 * 6 6 100 kHz 6 1000000
87 * 7 12 50 kHz 7 10000000
94 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000
[all …]
/linux/Documentation/i2c/busses/
H A Di2c-ismt.rst21 Specify the bus speed in kHz.
27 80 kHz
28 100 kHz
29 400 kHz
30 1000 kHz
/linux/drivers/pwm/
H A Dpwm-argon-fan-hat.c7 * - fixed 30 kHz period
17 #define ARGON40_FAN_HAT_PERIOD_NS 33333 /* ~30 kHz */
29 *wfhw = 100; in argon_fan_hat_round_waveform_tohw()
31 *wfhw = mul_u64_u64_div_u64(wf->duty_length_ns, 100, ARGON40_FAN_HAT_PERIOD_NS); in argon_fan_hat_round_waveform_tohw()
44 wf->duty_length_ns = DIV64_U64_ROUND_UP(wf->period_length_ns * *wfhw, 100); in argon_fan_hat_round_waveform_fromhw()
H A Dpwm-sl28cpld.c14 * Let cnt[7:0] be the counter, clocked at 32kHz:
20 * | 2 | cnt[5] | cnt[4:0] | 1 kHz | 1000000 ns |
21 * | 3 | cnt[4] | cnt[3:0] | 2 kHz | 500000 ns |
25 * - The hardware cannot generate a 100% duty cycle if the prescaler is 0.
54 #define SL28CPLD_PWM_CLK 32000 /* 32 kHz */
156 * Work around the hardware limitation. See also above. Trap 100% duty in sl28cpld_pwm_apply()
/linux/drivers/nvmem/
H A Dlpc18xx_eeprom.c38 /* EEPROM device requires a ~1500 kHz clock (min 800 kHz, max 1600 kHz) */
109 /* Wait 100 us while the EEPROM wakes up */ in lpc18xx_eeprom_gather_write()
110 usleep_range(100, 200); in lpc18xx_eeprom_gather_write()
137 /* Wait 100 us while the EEPROM wakes up */ in lpc18xx_eeprom_read()
138 usleep_range(100, 200); in lpc18xx_eeprom_read()
/linux/Documentation/hwmon/
H A Dlm85.rst153 driven by a 22.5 kHz clock. This is a global mode, not per-PWM output,
154 which means that setting any PWM frequency above 11.3 kHz will switch
155 all 3 PWM outputs to a 22.5 kHz frequency. Conversely, setting any PWM
156 frequency below 11.3 kHz will switch all 3 PWM outputs to a frequency
157 between 10 and 100 Hz, which can then be tuned separately.
179 The LM96000 supports additional high frequency PWM modes (22.5 kHz, 24 kHz,
180 25.7 kHz, 27.7 kHz and 30 kHz), which can be configured on a per-PWM basis.
266 -1 PWM always 100% (full on)
H A Dmcp3021.rst36 compatible interface. Standard (100 kHz) and Fast (400 kHz) I2C modes are
H A Df71805f.rst85 in2 VIN2 VRAM 100K 100K 2.00 ~1.25 V [1]_
86 in3 VIN3 VCHIPSET 47K 100K 1.47 2.24 V [2]_
150 from 187.5 kHz (default) to 31 Hz. The best frequency depends on the
153 above the audible range, such as 25 kHz, may be a good choice; if this
155 not going below 1 kHz, as the fan tachometers get confused by lower
/linux/drivers/media/radio/si470x/
H A Dradio-si470x-common.c108 /* Spacing (kHz) */
109 /* 0: 200 kHz (USA, Australia) */
110 /* 1: 100 kHz (Europe, Japan) */
111 /* 2: 50 kHz */
114 MODULE_PARM_DESC(space, "Spacing: 0=200kHz 1=100kHz *2=50kHz*");
241 /* Spacing (kHz) */ in si470x_get_step()
243 /* 0: 200 kHz (USA, Australia) */ in si470x_get_step()
246 /* 1: 100 kHz (Europe, Japan) */ in si470x_get_step()
248 return 100 * 16; in si470x_get_step()
249 /* 2: 50 kHz */ in si470x_get_step()
[all …]
/linux/sound/soc/codecs/
H A Dwm8974.c56 static const char *wm8974_deemp[] = {"None", "32kHz", "44.1kHz", "48kHz" };
61 static const char *wm8974_eq3[] = {"650Hz", "850Hz", "1.1kHz", "1.4kHz" };
62 static const char *wm8974_eq4[] = {"1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz" };
63 static const char *wm8974_eq5[] = {"5.3kHz", "6.
[all...]
H A Dmax98373.c88 9, 10, TLV_DB_SCALE_ITEM(500, 100, 0),
91 0, 9, TLV_DB_SCALE_ITEM(800, 100, 0),
95 2, 4, TLV_DB_SCALE_ITEM(100, 100, 0),
98 0, 9, TLV_DB_SCALE_ITEM(800, 100, 0),
105 10, 13, TLV_DB_SCALE_ITEM(-500, 100, 0),
106 14, 15, TLV_DB_SCALE_ITEM(-100, 50, 0),
109 0, 15, TLV_DB_SCALE_ITEM(-1500, 100, 0),
166 "333kHz", "192kHz", "6
[all...]
H A Dmax9877.c35 24, 31, TLV_DB_SCALE_ITEM(-700, 100, 0)
51 "1176KHz",
52 "1100KHz",
53 "700KHz",
/linux/arch/arm/boot/dts/allwinner/
H A Dsun5i-reference-design-tablet.dtsi55 brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
88 * The gsl1680 is rated at 400KHz and it will not work reliable at
89 * 100KHz, this has been confirmed on multiple different q8 tablets.
90 * All other devices on this bus are also rated for 400KHz.
/linux/drivers/i2c/
H A Di2c-core-acpi.c347 * These Silead touchscreen controllers only work at 400KHz, for
348 * some reason they do not work at 100KHz. On some devices the ACPI
350 * of 100KHz, testing has shown that these other devices work fine
351 * at 400KHz (as can be expected of any recent i2c hw) so we force
352 * the speed of the bus to 400 KHz if a Silead device is present.
360 * When a 400KHz freq is used on this model of ELAN touchpad in Linux,
363 * V15 G4) ACPI tables specify a 400KHz frequency for this device and
364 * some I2C busses (e.g, Designware I2C) default to a 400KHz freq,
365 * force the speed to 100KHz as a workaround.
371 * a 400KHz frequency. The root cause of the issue is not known.
/linux/sound/firewire/motu/
H A Dmotu-protocol-v1.c36 // 0x00000004: 48.0 kHz
37 // 0x00000000: 44.1 kHz
68 // 0x00000000: force to low rate (44.1/48.0 kHz).
97 // 0x00000000: 44.1 kHz
98 // 0x00000008: 48.0 kHz
99 // 0x00000010: 88.2 kHz
100 // 0x00000018: 96.0 kHz
355 // 100 msec. in switch_fetching_mode_828()
356 msleep(100); in switch_fetching_mode_828()
/linux/drivers/i2c/busses/
H A Di2c-stm32.h19 STM32_I2C_SPEED_STANDARD, /* 100 kHz */
20 STM32_I2C_SPEED_FAST, /* 400 kHz */
/linux/drivers/gpu/drm/sprd/
H A Dmegacores_pll.c20 #define MIN_OUTPUT_FREQ (100)
32 const u32 khz = 1000; in dphy_calc_pll_param() local
34 const unsigned long long factor = 100; in dphy_calc_pll_param()
38 pll->potential_fvco = pll->freq / khz; in dphy_calc_pll_param()
39 pll->ref_clk = PHY_REF_CLK / khz; in dphy_calc_pll_param()
219 const u32 scale = 100; in dphy_timing_config()
257 - 525 * t_byteck / 100, t_byteck) - 2; in dphy_timing_config()
260 + ((tmp >> 16) & 0xffff) - 525 * t_byteck / 100, in dphy_timing_config()
273 range[L] = 100 * scale; in dphy_timing_config()
/linux/Documentation/devicetree/bindings/rtc/
H A Dingenic,rtc.yaml68 (assuming RTC clock at 32 kHz)
73 default: 100
76 (assuming RTC clock at 32 kHz)
/linux/Documentation/admin-guide/media/
H A Dvivid.rst332 configuration of your kernel, so usually 1/100, 1/250 or 1/1000 of a second),
391 ioctl will return 100% signal strength for +/- 0.25 MHz and 50% for +/- 1 MHz.
499 Aspect Ratio control setting and teletext pages 100-159, one page per frame.
526 - AM: 520 kHz - 1710 kHz
527 - SW: 2300 kHz - 26.1 MHz
529 Valid channels are emulated every 1 MHz for FM and every 100 kHz for AM and SW.
531 frequency until it becomes 0% at +/- 50 kHz (FM) or 5 kHz (AM/SW) from the
541 The RDS signal is 'detected' for +/- 12.5 kHz around the channel frequency,
544 blocks if you are +/- 12.5 kHz from the channel frequency. All four errors
562 - AM: 520 kHz - 1710 kHz
[all …]

12345678910>>...20