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/linux/Documentation/driver-api/media/drivers/ccs/
H A Dccs-regs.asc1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
2 # Copyright (C) 2019--2020 Intel Corporation
5 # - f field LSB MSB rflags
6 # - e enum value # after a field
7 # - e enum value [LSB MSB]
8 # - b bool bit
9 # - l arg name min max elsize [discontig...]
12 # 8, 16, 32 register bits (default is 8)
13 # v1.1 defined in version 1.1
20 module_revision_number_major 0x0002 8
[all …]
/linux/fs/nls/
H A Dnls_ucs2_utils.c1 // SPDX-License-Identifier: GPL-2.0-or-later
19 MODULE_DESCRIPTION("NLS UCS-2");
26 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 000-00f */
27 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 010-01f */
28 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 020-02f */
29 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 030-03f */
30 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 040-04f */
31 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 050-05f */
32 0, -32, -32, -32, -32, -32, -32, -32, -32, -32, -32,
33 -32, -32, -32, -32, -32, /* 060-06f */
[all …]
/linux/drivers/mtd/nand/raw/
H A Dnand_ids.c1 // SPDX-License-Identifier: GPL-2.0-only
29 {"TC58NVG0S3E 1G 3.3V 8-bit",
31 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
34 SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
37 SZ_4K, SZ_512, SZ_256K, 0, 8, 256, NAND_ECC_INFO(8, SZ_512) },
38 {"TC58NVG3S0F 8G 3.3V 8-bit",
40 SZ_4K, SZ_1K, SZ_256K, 0, 8, 232, NAND_ECC_INFO(4, SZ_512) },
41 {"TC58NVG5D2 32G 3.3V 8-bit",
[all …]
/linux/arch/powerpc/boot/
H A Dwii-head.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * arch/powerpc/boot/wii-head.S
6 * Copyright (C) 2008-2009 The GameCube Linux Team
14 * - if the data and instruction caches are enabled or not
15 * - if the MMU is enabled or not
16 * - if the high BATs are enabled or not
29 rlwinm 9, 9, 0, ~((1<<4)|(1<<5)) /* MSR_DR|MSR_IR */
30 bcl 20, 31, 1f
31 1:
32 mflr 8
[all …]
H A Dgamecube-head.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * arch/powerpc/boot/gamecube-head.S
6 * Copyright (C) 2004-2009 The GameCube Linux Team
14 * - if the data and instruction caches are enabled or not
15 * - if the MMU is enabled or not
28 rlwinm 9, 9, 0, ~((1<<4)|(1<<5)) /* MSR_DR|MSR_IR */
29 bcl 20, 31, 1f
30 1:
31 mflr 8
32 clrlwi 8, 8, 3 /* convert to a real address */
[all …]
/linux/Documentation/gpu/
H A Dafbc.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 It provides fine-grained random access and minimizes the amount of
21 AFBC streams can contain several components - where a component
32 * Component 1: G
37 reside in the least-significant bits of the corresponding linear
42 * Component 0: R(8)
43 * Component 1: G(8)
44 * Component 2: B(8)
45 * Component 3: A(8)
49 * Component 0: R(8)
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/linux/arch/arm64/crypto/
H A Dsha3-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha3-ce-core.S - core SHA-3 transform using v8.2 Crypto Extensions
15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
46 ld1 { v0.1d- v3.1d}, [x0]
47 ld1 { v4.1d- v7.1d}, [x8], #32
48 ld1 { v8.1d-v11.1d}, [x8], #32
49 ld1 {v12.1d-v15.1d}, [x8], #32
50 ld1 {v16.1d-v19.1d}, [x8], #32
51 ld1 {v20.1d-v23.1d}, [x8], #32
52 ld1 {v24.1d}, [x8]
[all …]
/linux/drivers/media/usb/dvb-usb/
H A Daf9005.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* Common header-file of the Linux driver for the Afatech 9005
3 * USB1.1 DVB-T receiver.
9 * see Documentation/driver-api/media/drivers/dvb-usb.rst for more information
15 #include "dvb-usb.h"
37 #define AF9005_TUNER_REG 1
62 #define reg_aagc_inverted_agc_len 1
65 #define reg_aagc_sign_only_pos 1
66 #define reg_aagc_sign_only_len 1
70 #define reg_aagc_slow_adc_en_len 1
[all …]
/linux/arch/arc/include/asm/
H A Darcregs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
16 #define ARC_REG_FP_BCR 0x6B /* ARCompact: Single-Precision FPU */
56 #define STATUS_AE_MASK (1<<STATUS_AE_BIT)
57 #define STATUS_DE_MASK (1<<STATUS_DE_BIT)
58 #define STATUS_U_MASK (1<<STATUS_U_BIT)
59 #define STATUS_Z_MASK (1<<STATUS_Z_BIT)
60 #define STATUS_L_MASK (1<<STATUS_L_BIT)
63 * ECR: Exception Cause Reg bits-n-pieces
65 * [15: 8] = Exception Cause Code
[all …]
/linux/arch/xtensa/variants/test_kc705_hifi/include/variant/
H A Dtie.h2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2014 Tensilica Inc.
36 #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
44 #define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */
45 #define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
49 #define XCHAL_CP7_SA_ALIGN 1 /* min alignment of save area */
54 #define XCHAL_CP0_SA_ALIGN 1
56 #define XCHAL_CP2_SA_ALIGN 1
58 #define XCHAL_CP3_SA_ALIGN 1
60 #define XCHAL_CP4_SA_ALIGN 1
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/linux/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/
H A Dramcfg.h1 /* SPDX-License-Identifier: MIT */
11 unsigned rammap_00_16_20:1;
12 unsigned rammap_00_16_40:1;
13 unsigned rammap_00_17_02:1;
16 unsigned rammap_10_04_02:1;
17 unsigned rammap_10_04_08:1;
20 unsigned rammap_11_08_01:1;
22 unsigned rammap_11_08_10:1;
25 unsigned rammap_11_0a_0400:1;
26 unsigned rammap_11_0a_0800:1;
[all …]
/linux/drivers/media/test-drivers/vicodec/
H A Dcodec-fwht.c1 // SPDX-License-Identifier: LGPL-2.1+
6 * 8x8 Fast Walsh Hadamard Transform in sequency order based on the paper:
8 * A Recursive Algorithm for Sequency-Ordered Fast Walsh Transforms,
15 #include "codec-fwht.h"
21 * be guaranteed that the magic 8 byte sequence (see below) can
28 #define IBLOCK 1
34 1, 8,
57 s16 block[8 * 8]; in rlc()
67 for (y = 0; y < 8; y++) { in rlc()
68 for (x = 0; x < 8; x++) { in rlc()
[all …]
/linux/drivers/pinctrl/uniphier/
H A Dpinctrl-uniphier-pxs2.c1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright (C) 2015-2017 Socionext Inc.
12 #include "pinctrl-uniphier.h"
18 UNIPHIER_PINCTRL_PIN(1, "ED1", UNIPHIER_PIN_IECTRL_NONE,
19 1, UNIPHIER_PIN_DRV_1BIT,
20 1, UNIPHIER_PIN_PULL_DOWN),
39 UNIPHIER_PINCTRL_PIN(8, "XERWE0", UNIPHIER_PIN_IECTRL_NONE,
40 8, UNIPHIER_PIN_DRV_1BIT,
41 8, UNIPHIER_PIN_PULL_DOWN),
61 -1, UNIPHIER_PIN_DRV_FIXED8,
[all …]
/linux/include/sound/
H A Dump_msg.h1 // SPDX-License-Identifier: GPL-2.0-or-later
30 UMP_CC_MODULATION = 1,
36 UMP_CC_BALANCE = 8,
135 u32 note:8;
136 u32 velocity:8;
138 u32 velocity:8;
139 u32 note:8;
154 u32 note:8;
155 u32 data:8;
157 u32 data:8;
[all …]
/linux/lib/crypto/powerpc/
H A Dcurve25519-ppc64le_asm.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 # This code is taken from CRYPTOGAMs[1] and is included here using the option
9 # [1] https://github.com/dot-asm/cryptogams/
11 # Copyright (c) 2006-2017, CRYPTOGAMS by <appro@openssl.org>
58 # - Added x25519_fe51_sqr_times, x25519_fe51_frombytes, x25519_fe51_tobytes
61 # Copyright 2024- IBM Corp.
63 # X25519 lower-level primitives for PPC64.
73 stdu 1,-144(1)
74 std 21,56(1)
75 std 22,64(1)
[all …]
/linux/drivers/gpu/drm/vmwgfx/device_include/
H A Dsvga3d_surfacedefs.h2 * Copyright 2008-2021 VMware, Inc.
3 * SPDX-License-Identifier: GPL-2.0 OR MIT
28 * svga3d_surfacedefs.h --
57 SVGA3DBLOCKDESC_BLUE = 1 << 0,
58 SVGA3DBLOCKDESC_W = 1 << 0,
59 SVGA3DBLOCKDESC_BUMP_L = 1 << 0,
61 SVGA3DBLOCKDESC_GREEN = 1 << 1,
62 SVGA3DBLOCKDESC_V = 1 << 1,
64 SVGA3DBLOCKDESC_RED = 1 << 2,
65 SVGA3DBLOCKDESC_U = 1 << 2,
[all …]
/linux/arch/arm/mach-davinci/
H A Dda850.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI DA850/OMAP-L138 chip specific setup
5 * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com/
15 #include <linux/mfd/da8xx-cfgchip.h>
19 #include <clocksource/timer-davinci.h>
61 MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false)
63 MUX_CFG(DA850, MII_TXEN, 2, 4, 15, 8, false)
64 MUX_CFG(DA850, MII_TXCLK, 2, 8, 15, 8, false)
65 MUX_CFG(DA850, MII_COL, 2, 12, 15, 8, false)
66 MUX_CFG(DA850, MII_TXD_3, 2, 16, 15, 8, false)
[all …]
/linux/arch/alpha/lib/
H A Dev6-memcpy.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-memcpy.S
4 * 21264 version by Rick Gorton <rick.gorton@alpha-processor.com>
8 * - memory accessed as aligned quadwords only
9 * - uses bcmpge to compare 8 bytes in parallel
14 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
16 * E - either cluster
17 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
18 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
21 * $1,$2, - scratch
[all …]
/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt8173.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015 MediaTek Inc.
12 #include <linux/pinctrl/pinconf-generic.h>
13 #include <dt-bindings/pinctrl/mt65xx.h>
15 #include "pinctrl-mtk-common.h"
16 #include "pinctrl-mtk-mt8173.h"
21 MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 2, 1, 0), /* KROW0 */
23 MTK_PIN_PUPD_SPEC_SR(121, 0xe00, 10, 9, 8), /* KROW2 */
24 MTK_PIN_PUPD_SPEC_SR(122, 0xe10, 2, 1, 0), /* KCOL0 */
26 MTK_PIN_PUPD_SPEC_SR(124, 0xe10, 10, 9, 8), /* KCOL2 */
[all …]
/linux/drivers/input/misc/
H A Dyealink.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 u8 size; /* 1-11, size of used data bytes. */
38 * size 1
48 * size 1
49 * offset key number [0-1f]
57 * size 1-11
58 * offset 0-23
66 * size 1
68 * data[0] 0 OFF / 1 ON
75 * size 1
[all …]
/linux/include/asm-generic/
H A Dxor.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * include/asm-generic/xor.h
5 * Generic optimized RAID-5 checksumming functions.
14 long lines = bytes / (sizeof (long)) / 8; in xor_8regs_2()
18 p1[1] ^= p2[1]; in xor_8regs_2()
25 p1 += 8; in xor_8regs_2()
26 p2 += 8; in xor_8regs_2()
27 } while (--lines > 0); in xor_8regs_2()
35 long lines = bytes / (sizeof (long)) / 8; in xor_8regs_3()
39 p1[1] ^= p2[1] ^ p3[1]; in xor_8regs_3()
[all …]
/linux/arch/mips/kernel/
H A Dmips-r2-to-r6-emul.c28 #include <asm/mips-r2-to-r6-emul.h>
55 extern const unsigned int fpucondbit[8];
63 mipsr2_emulation = 1; in mipsr2emu_enable()
65 pr_info("MIPS R2-to-R6 Emulator Enabled!"); in mipsr2emu_enable()
67 return 1; in mipsr2emu_enable()
72 * mipsr6_emul - Emulate some frequent R2/R5/R6 instructions in delay slot
83 regs->regs[MIPSInst_RT(ir)] = in mipsr6_emul()
84 (s32)regs->regs[MIPSInst_RS(ir)] + in mipsr6_emul()
92 regs->regs[MIPSInst_RT(ir)] = in mipsr6_emul()
93 (s64)regs->regs[MIPSInst_RS(ir)] + in mipsr6_emul()
[all …]
/linux/arch/alpha/kernel/
H A Dentry.S1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Kernel entry-points.
8 #include <asm/asm-offsets.h>
26 .cfi_rel_offset 64, 8
35 .size \func, . - \func
39 * This defines the normal kernel pt-regs layout.
41 * regs 9-15 preserved by C code
42 * regs 16-18 saved by PAL-code
43 * regs 29-30 saved and set up by PAL-code
44 * JRP - Save regs 16-18 in a special area of the stack, so that
[all …]
/linux/Documentation/admin-guide/media/
H A Ddvb_intro.rst1 .. SPDX-License-Identifier: GPL-2.0
12 structure of DVB-T cards are substantially similar to Analogue TV cards,
30 embedded within the modulated composite analogue signal -
38 signal encoded at a resolution of 768x576 24-bit color pixels over 25
39 frames per second - a fair amount of data is generated and must be
43 encoded and compressed form - similar to the form that is used in
46 The purpose of a simple budget digital TV card (DVB-T,C or S) is to
96 On this example, we're considering tuning into DVB-T channels in
102 Table 1. Transponder Frequencies Mount Dandenong, Vic, Aus.
115 The digital TV Scan utilities (like dvbv5-scan) have use a set of
[all …]
/linux/arch/xtensa/variants/test_kc705_be/include/variant/
H A Dtie.h2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2015 Cadence Design Systems Inc.
36 #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
44 #define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */
45 #define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
49 #define XCHAL_CP7_SA_ALIGN 1 /* min alignment of save area */
54 #define XCHAL_CP0_SA_ALIGN 1
56 #define XCHAL_CP2_SA_ALIGN 1
58 #define XCHAL_CP3_SA_ALIGN 1
60 #define XCHAL_CP4_SA_ALIGN 1
[all …]

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