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/linux/tools/testing/selftests/ia64/
H A Daliasing-test.c36 if (fnmatch("/proc/bus/pci/*", path, 0) == 0) { in map_mem()
59 return 0; in map_mem()
66 int i, n, r, rc = 0, result = 0; in scan_tree()
69 n = scandir(path, &namelist, 0, alphasort); in scan_tree()
70 if (n < 0) { in scan_tree()
75 for (i = 0; i < n; i++) { in scan_tree()
78 if (fnmatch(".", name, 0) == 0) in scan_tree()
80 if (fnmatch("..", name, 0) == 0) in scan_tree()
88 if (fnmatch(file, name, 0) == 0) { in scan_tree()
90 if (rc == 0) in scan_tree()
[all …]
/linux/drivers/clk/imx/
H A Dclk-imx8qxp-lpcg.h11 #define LSIO_PWM_0_LPCG 0x00000
12 #define LSIO_PWM_1_LPCG 0x10000
13 #define LSIO_PWM_2_LPCG 0x20000
14 #define LSIO_PWM_3_LPCG 0x30000
15 #define LSIO_PWM_4_LPCG 0x40000
16 #define LSIO_PWM_5_LPCG 0x50000
17 #define LSIO_PWM_6_LPCG 0x60000
18 #define LSIO_PWM_7_LPCG 0x70000
19 #define LSIO_GPIO_0_LPCG 0x80000
20 #define LSIO_GPIO_1_LPCG 0x90000
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dc293si-post.dtsi39 interrupts = <19 2 0 0>;
42 /* controller at 0xa000 */
48 bus-range = <0 255>;
50 interrupts = <16 2 0 0>;
52 pcie@0 {
53 reg = <0 0 0 0 0>;
58 interrupts = <16 2 0 0>;
59 interrupt-map-mask = <0xf800 0 0 7>;
61 /* IDSEL 0x0 */
62 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
[all …]
/linux/drivers/gpu/drm/vboxvideo/
H A Dvboxvideo_vbe.h9 #define VBE_DISPI_BANK_ADDRESS 0xA0000
16 #define VBE_DISPI_IOPORT_INDEX 0x01CE
17 #define VBE_DISPI_IOPORT_DATA 0x01CF
19 #define VBE_DISPI_IOPORT_DAC_WRITE_INDEX 0x03C8
20 #define VBE_DISPI_IOPORT_DAC_DATA 0x03C9
22 #define VBE_DISPI_INDEX_ID 0x0
23 #define VBE_DISPI_INDEX_XRES 0x1
24 #define VBE_DISPI_INDEX_YRES 0x2
25 #define VBE_DISPI_INDEX_BPP 0x3
26 #define VBE_DISPI_INDEX_ENABLE 0x4
[all …]
/linux/sound/soc/intel/atom/sst/
H A Dsst_acpi.c39 #define SST_BYT_IRAM_PHY_START 0xff2c0000
40 #define SST_BYT_IRAM_PHY_END 0xff2d4000
41 #define SST_BYT_DRAM_PHY_START 0xff300000
42 #define SST_BYT_DRAM_PHY_END 0xff320000
43 #define SST_BYT_IMR_VIRT_START 0xc0000000 /* virtual addr in LPE */
44 #define SST_BYT_IMR_VIRT_END 0xc01fffff
45 #define SST_BYT_SHIM_PHY_ADDR 0xff340000
46 #define SST_BYT_MBOX_PHY_ADDR 0xff344000
47 #define SST_BYT_DMA0_PHY_ADDR 0xff298000
48 #define SST_BYT_DMA1_PHY_ADDR 0xff29c00
[all...]
/linux/arch/arm/mach-orion5x/
H A Dorion5x.h36 #define ORION5X_REGS_PHYS_BASE 0xf1000000
37 #define ORION5X_REGS_VIRT_BASE IOMEM(0xfec00000)
40 #define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000
41 #define ORION5X_PCIE_IO_BUS_BASE 0x00000000
44 #define ORION5X_PCI_IO_PHYS_BASE 0xf2100000
45 #define ORION5X_PCI_IO_BUS_BASE 0x00010000
48 #define ORION5X_SRAM_PHYS_BASE (0xf2200000)
52 #define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000
53 #define ORION5X_PCIE_WA_VIRT_BASE IOMEM(0xfd000000)
56 #define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000
[all …]
/linux/arch/arm/mach-omap2/
H A Domap34xx.h17 #define L4_34XX_BASE 0x48000000
18 #define L4_WK_34XX_BASE 0x48300000
19 #define L4_PER_34XX_BASE 0x49000000
20 #define L4_EMU_34XX_BASE 0x54000000
21 #define L3_34XX_BASE 0x68000000
23 #define L4_WK_AM33XX_BASE 0x44C00000
25 #define OMAP3430_32KSYNCT_BASE 0x48320000
26 #define OMAP3430_CM_BASE 0x48004800
27 #define OMAP3430_PRM_BASE 0x48306800
28 #define OMAP343X_SMS_BASE 0x6C000000
[all …]
H A Domap24xx.h19 #define L4_24XX_BASE 0x48000000
20 #define L4_WK_243X_BASE 0x49000000
21 #define L3_24XX_BASE 0x68000000
24 #define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000)
25 #define OMAP24XX_IVA_INTC_BASE 0x40000000
28 #define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
29 #define OMAP2420_PRCM_BASE (L4_24XX_BASE + 0x8000)
30 #define OMAP2420_CM_BASE (L4_24XX_BASE + 0x8000)
32 #define OMAP2420_SDRC_BASE (L3_24XX_BASE + 0x9000)
33 #define OMAP2420_SMS_BASE 0x68008000
[all …]
/linux/arch/arm/boot/dts/microchip/
H A Dtny_a9260_common.dtsi14 reg = <0x20000000 0x4000000>;
30 timer@0 {
32 reg = <0>, <1>;
51 pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
55 reg = <0x3 0x0 0x800000>;
68 at91bootstrap@0 {
70 reg = <0x0 0x20000>;
75 reg = <0x20000 0x40000>;
80 reg = <0x60000 0x20000>;
85 reg = <0x80000 0x20000>;
[all …]
H A Dtny_a9263.dts19 reg = <0x20000000 0x4000000>;
39 timer@0 {
41 reg = <0>, <1>;
61 pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
65 reg = <0x3 0x0 0x800000>;
78 at91bootstrap@0 {
80 reg = <0x0 0x20000>;
85 reg = <0x20000 0x40000>;
90 reg = <0x60000 0x20000>;
95 reg = <0x80000 0x20000>;
[all …]
H A Dusb_a9260_common.dtsi25 reg = <0x20000000 0x4000000>;
35 timer@0 {
37 reg = <0>, <1>;
62 pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
66 reg = <0x3 0x0 0x800000>;
79 at91bootstrap@0 {
81 reg = <0x0 0x20000>;
86 reg = <0x20000 0x40000>;
91 reg = <0x60000 0x20000>;
96 reg = <0x80000 0x20000>;
[all …]
H A Dat91-wb45n.dtsi21 reg = <0x20000000 0x4000000>;
49 pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb &pinctrl_nand_oe_we>;
54 reg = <0x3 0x0 0x800000>;
69 at91bootstrap@0 {
71 reg = <0x0 0x20000>;
76 reg = <0x20000 0x80000>;
81 reg = <0xa0000 0x20000>;
86 reg = <0xc0000 0x20000>;
91 reg = <0xe0000 0x280000>;
96 reg = <0x360000 0x280000>;
[all …]
H A Dusb_a9263.dts19 reg = <0x20000000 0x4000000>;
39 timer@0 {
41 reg = <0>, <1>;
63 flash@0 {
65 reg = <0>;
81 pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
85 reg = <0x3 0x0 0x800000>;
98 at91bootstrap@0 {
100 reg = <0x0 0x20000>;
105 reg = <0x20000 0x40000>;
[all …]
H A Dat91-qil_a9260.dts18 reg = <0x20000000 0x4000000>;
34 timer@0 {
36 reg = <0>, <1>;
51 pinctrl-0 = <
57 slot@0 {
58 reg = <0>;
64 pinctrl-0 =
75 pinctrl-0 =
83 pinctrl-0 =
99 m41t94@0 {
[all …]
H A Dat91-som60.dtsi20 reg = <0x20000000 0x8000000>;
105 slot@0 {
106 reg = <0>;
113 slot@0 {
114 reg = <0>;
120 cs-gpios = <&pioD 13 0>, <0>, <0>, <0>;
127 pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts_cts>;
131 pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>;
135 pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts_cts>;
139 pinctrl-0 = <&pinctrl_usart3 &pinctrl_usart3_rts_cts>;
[all …]
H A Dat91-wb50n.dtsi21 reg = <0x20000000 0x4000000>;
51 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>;
53 slot@0 {
54 reg = <0>;
61 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
63 atheros@0 {
66 reg = <0>;
76 dmas = <0>, <0>; /* Do not use DMA for dbgu */
84 pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts_cts>;
92 pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>;
[all …]
/linux/arch/alpha/include/asm/
H A Dvga.h59 (((a) >= 0x3b0) && ((a) < 0x3e0) && \
60 ((a) != 0x3b3) && ((a) != 0x3d3))
63 (((a) >= 0xa0000) && ((a) <= 0xc0000))
68 } while(0)
73 } while(0)
76 # define pci_vga_hose 0
77 # define __is_port_vga(a) 0
78 # define __is_mem_vga(a) 0
/linux/drivers/firmware/
H A Discsi_ibft_find.c45 #define VGA_MEM 0xA0000 /* VGA buffer */
46 #define VGA_SIZE 0x20000 /* 128kB */
53 unsigned long pos, virt_pos = 0; in reserve_ibft_region()
54 unsigned int len = 0; in reserve_ibft_region()
58 ibft_phys_addr = 0; in reserve_ibft_region()
73 if (offset_in_page(pos) == 0) { in reserve_ibft_region()
80 for (i = 0; i < ARRAY_SIZE(ibft_signs); i++) { in reserve_ibft_region()
82 IBFT_SIGN_LEN) == 0) { in reserve_ibft_region()
/linux/drivers/hwtracing/intel_th/
H A Dintel_th.h16 INTEL_TH_SOURCE = 0,
61 #define INTEL_TH_CAP(_th, _cap) ((_th)->drvdata ? (_th)->drvdata->_cap : 0)
107 for (i = 0; i < thdev->num_resources; i++) in intel_th_device_get_resource()
118 GTH_NONE = 0,
135 (thdev->output.port >= 0 || in intel_th_output_assigned()
245 TH_MMIO_CONFIG = 0,
314 REG_GTH_OFFSET = 0x0000,
315 REG_GTH_LENGTH = 0x2000,
318 REG_TSCU_OFFSET = 0x2000,
319 REG_TSCU_LENGTH = 0x1000,
[all …]
/linux/arch/arm/boot/dts/nxp/mxs/
H A Dimx28-lwe.dtsi20 reg = <0x40000000 0x08000000>;
48 pinctrl-0 = <&duart_pins_a>;
54 pinctrl-0 = <&i2c0_pins_a>;
73 pinctrl-0 = <&mmc0_8bit_pins_a>;
83 pinctrl-0 = <&spi2_pins_a>;
90 pinctrl-0 = <&spi3_pins_a>;
93 flash@0 {
96 reg = <0>;
103 partition@0 {
105 reg = <0 0x80000>;
[all …]
/linux/arch/arm/mach-mv78xx0/
H A Dmv78xx0.h17 * f0800000 PCIe #0 I/O space
29 * fee00000 f0800000 64K PCIe #0 I/O space
39 #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000
40 #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000
41 #define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000)
42 #define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000
45 #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20))
48 #define MV78XX0_REGS_PHYS_BASE 0xf1000000
49 #define MV78XX0_REGS_VIRT_BASE IOMEM(0xfec00000)
52 #define MV78XX0_SRAM_PHYS_BASE (0xf2200000)
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Dkirkwood-iconnect.dts13 reg = <0x00000000 0x10000000>;
19 linux,initrd-start = <0x4500040>;
20 linux,initrd-end = <0x4800000>;
71 reg = <0x4c>;
81 pinctrl-0 = < &pmx_led_level &pmx_led_power_blue
125 pinctrl-0 = < &pmx_button_reset &pmx_button_otb >;
146 partition@0 {
148 reg = <0x0000000 0xc0000>;
153 reg = <0xa0000 0x20000>;
158 reg = <0x100000 0x300000>;
[all …]
H A Dkirkwood-linksys-viper.dts23 reg = <0x00000000 0x8000000>;
36 pinctrl-0 = < &pmx_btn_wps &pmx_btn_reset >;
54 pinctrl-0 = < &pmx_led_white_health &pmx_led_white_pulse >;
90 pinctrl-0 = <&pmx_nand>;
98 partition@0 {
100 reg = <0x0 0x80000>;
106 reg = <0x80000 0x20000>;
111 reg = <0xA0000 0x20000>;
116 reg = <0x200000 0x2A0000>;
121 reg = <0x4A0000 0x1760000>;
[all …]
/linux/arch/arm/mach-dove/
H A Ddove.h14 * e0000000 @runtime 128M PCIe-0 Memory space
18 * f2000000 fee00000 1M PCIe-0 I/O space
22 #define DOVE_CESA_PHYS_BASE 0xc8000000
23 #define DOVE_CESA_VIRT_BASE IOMEM(0xfdb00000)
26 #define DOVE_PCIE0_MEM_PHYS_BASE 0xe0000000
29 #define DOVE_PCIE1_MEM_PHYS_BASE 0xe8000000
32 #define DOVE_BOOTROM_PHYS_BASE 0xf8000000
35 #define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000
36 #define DOVE_SCRATCHPAD_VIRT_BASE IOMEM(0xfdd00000)
39 #define DOVE_SB_REGS_PHYS_BASE 0xf1000000
[all …]
/linux/Documentation/devicetree/bindings/mailbox/
H A Dnvidia,tegra186-hsp.yaml34 - bits 7..0:
51 - bits 23..0:
87 - pattern: "^shared([0-9]|1[0-5])$"
88 - pattern: "^shared([0-9]|1[0-5])$"
89 - pattern: "^shared([0-9]|1[0-5])$"
90 - pattern: "^shared([0-9]|1[0-5])$"
91 - pattern: "^shared([0-9]|1[0-5])$"
92 - pattern: "^shared([0-9]|1[0-5])$"
93 - pattern: "^shared([0-9]|1[0-5])$"
94 - pattern: "^shared([0-9]|1[0-5])$"
[all …]

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