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/freebsd/contrib/libarchive/libarchive/test/
H A Dtest_write_format_tar_sparse.c39 size_t buff2_size = 0x13000; in test_1()
74 archive_entry_set_size(ae, 0x81000); in test_1()
75 archive_entry_sparse_add_entry(ae, 0x10000, 0x1000); in test_1()
76 archive_entry_sparse_add_entry(ae, 0x80000, 0x1000); in test_1()
81 for (i = 0; i < 0x81000;) { in test_1()
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/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dqoriq-fman-0.dtsi2 * QorIQ FMan device tree stub [ controller @ offset 0x400000 ]
38 cell-index = <0>;
40 ranges = <0 0x400000 0xfe000>;
41 reg = <0x400000 0xfe000>;
42 interrupts = <96 2 0 0>, <16 2 1 1>;
43 clocks = <&clockgen 3 0>;
45 fsl,qman-channel-range = <0x40 0xc>;
48 muram@0 {
50 reg = <0x0 0x28000>;
54 cell-index = <0x1>;
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H A Dqoriq-fman-1.dtsi2 * QorIQ FMan device tree stub [ controller @ offset 0x500000 ]
40 ranges = <0 0x500000 0xfe000>;
41 reg = <0x500000 0xfe000>;
42 interrupts = <97 2 0 0>, <16 2 1 0>;
45 fsl,qman-channel-range = <0x60 0xc>;
48 muram@0 {
50 reg = <0x0 0x28000>;
54 cell-index = <0x1>;
56 reg = <0x81000 0x1000>;
60 cell-index = <0x2>;
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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dfsl,fman.yaml22 FMan block. The offset is 0xc4 from the beginning of the
23 Frame Processing Manager memory map (0xc3000 from the
38 DEVDISR[1] 1 0
43 DCFG_DEVDISR2[6] 1 0
50 DCFG_CCSR_DEVDISR2[24] 1 0
156 reg = <0x400000 0x100000>;
157 ranges = <0 0x400000 0x100000>;
165 fsl,qman-channel-range = <0x40 0xc>;
167 muram@0 {
169 reg = <0x0 0x28000>;
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H A Dfsl-fman.txt28 FMan block. The offset is 0xc4 from the beginning of the
29 Frame Processing Manager memory map (0xc3000 from the
44 DEVDISR[1] 1 0
49 DCFG_DEVDISR2[6] 1 0
56 DCFG_CCSR_DEVDISR2[24] 1 0
148 muram@0 {
150 ranges = <0 0x000000 0x28000>;
215 cell-index = <0x28>;
217 reg = <0xa8000 0x1000>;
221 cell-index = <0x8>;
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/freebsd/sys/dev/qat/qat_hw/qat_c4xxx/
H A Dadf_c4xxx_hw_data.h9 #define ADF_C4XXX_SRAM_BAR 0
13 #define ADF_C4XXX_TX_RINGS_MASK 0xF
21 #define ADF_C4XXX_SOFTSTRAPPULL0_OFFSET (0x344)
22 #define ADF_C4XXX_SOFTSTRAPPULL1_OFFSET (0x348)
23 #define ADF_C4XXX_SOFTSTRAPPULL2_OFFSET (0x34C)
26 #define ADF_C4XXX_FUSECTL0_OFFSET (0x350)
27 #define ADF_C4XXX_FUSECTL1_OFFSET (0x354)
28 #define ADF_C4XXX_FUSECTL2_OFFSET (0x358)
30 #define ADF_C4XXX_FUSE_PKE_MASK (0xFFF000)
31 #define ADF_C4XXX_FUSE_COMP_MASK (0x000FFF)
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/freebsd/sys/contrib/device-tree/src/arm/nuvoton/
H A Dnuvoton-common-npcm7xx.dtsi17 #clock-cells = <0>;
25 #clock-cells = <0>;
33 #clock-cells = <0>;
41 #clock-cells = <0>;
49 #clock-cells = <0>;
56 #clock-cells = <0>;
66 ranges = <0x0 0xf0000000 0x00900000>;
70 reg = <0x3fe00
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/freebsd/sys/dts/powerpc/
H A Dp3041si.dtsi103 #size-cells = <0>;
105 cpu0: PowerPC,e500mc@0 {
107 reg = <0>;
145 dcsr-epu@0 {
147 interrupts = <52 2 0 0
148 84 2 0 0
149 85 2 0 0>;
151 reg = <0x0 0x1000>;
155 reg = <0x1000 0x1000 0x1000000 0x8000>;
159 reg = <0x2000 0x1000>;
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H A Dp2041si.dtsi102 #size-cells = <0>;
104 cpu0: PowerPC,e500mc@0 {
106 reg = <0>;
144 dcsr-epu@0 {
146 interrupts = <52 2 0 0
147 84 2 0 0
148 85 2 0 0>;
150 reg = <0x0 0x1000>;
154 reg = <0x1000 0x1000 0x1000000 0x8000>;
158 reg = <0x2000 0x1000>;
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H A Dp5020si.dtsi109 #size-cells = <0>;
111 cpu0: PowerPC,e5500@0 {
113 reg = <0>;
135 dcsr-epu@0 {
137 interrupts = <52 2 0 0
138 84 2 0 0
139 85 2 0 0>;
141 reg = <0x0 0x1000>;
145 reg = <0x1000 0x1000 0x1000000 0x8000>;
149 reg = <0x2000 0x1000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Ddra7-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl DRA7_L4CFG_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */
13 <0x00100000 0x4a100000 0x100000>, /* segment 1 */
14 <0x00200000 0x4a200000 0x100000>; /* segment 2 */
16 segment@0 { /* 0x4a000000 */
20 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
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