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/titanic_52/usr/src/uts/sun4u/serengeti/io/
H A Dsbdp.c65 uint_t sbdp_debug = 0x0;
99 int cur_num_wnodes = 0; /* how many nodes are currently running */
142 if (e != 0) in _init()
163 if (e != 0) in _fini()
202 return (0); in sbdp_get_bd_and_wnode_num()
228 if (sbdp_get_bd_and_wnode_num(nodeid, &bd, &wnode) < 0) in sbdp_get_board_num()
238 return (&sbdp_devattr[0]); in sbdp_get_devattr()
269 if (prom_getprop(nodeid, "device_type", (caddr_t)dev_type) < 0) { in sbdp_get_unit_num()
274 for (i = 0; SBDP_CT(i) != SBD_COMP_UNKNOWN; i++) { in sbdp_get_unit_num()
275 if (strcmp(dev_type, SBDP_OTYPE(i)) != 0) in sbdp_get_unit_num()
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/titanic_52/usr/src/lib/fm/topo/modules/sun4/ioboard/
H A Dioboard.h45 #define IOB_BUSADDR1 0x600000
46 #define IOB_BUSADDR2 0x700000
/titanic_52/usr/src/uts/common/sys/nxge/
H A Dnxge_defs.h37 #define PIO 0x000000
38 #define FZC_PIO 0x080000
39 #define RESERVED_1 0x100000
40 #define FZC_MAC 0x180000
41 #define RESERVED_2 0x200000
42 #define FZC_IPP 0x280000
43 #define FFLP 0x300000
44 #define FZC_FFLP 0x380000
45 #define PIO_VADDR 0x400000
46 #define RESERVED_3 0x48000
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/titanic_52/usr/src/uts/common/io/chxge/com/
H A Delmer0.h38 #define A_ELMER0_VERSION 0x100000
39 #define A_ELMER0_PHY_CFG 0x100004
40 #define A_ELMER0_INT_ENABLE 0x100008
41 #define A_ELMER0_INT_CAUSE 0x10000c
42 #define A_ELMER0_GPI_CFG 0x100010
43 #define A_ELMER0_GPI_STAT 0x100014
44 #define A_ELMER0_GPO 0x100018
45 #define A_ELMER0_PORT0_MI1_CFG 0x400000
47 #define S_MI1_MDI_ENABLE 0
60 #define M_MI1_SOF 0x
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/titanic_52/usr/src/uts/sun/sys/
H A Dsocal_cq_defs.h61 #define CQ_TYPE_NOP 0x00
62 #define CQ_TYPE_OUTBOUND 0x01
63 #define CQ_TYPE_INBOUND 0x02
64 #define CQ_TYPE_SIMPLE 0x03
65 #define CQ_TYPE_IO_WRITE 0x04
66 #define CQ_TYPE_IO_READ 0x05
67 #define CQ_TYPE_UNSOLICITED 0x06
68 #define CQ_TYPE_BYPASS_DEV 0x06 /* supercedes unsolicited in SOC+ */
69 #define CQ_TYPE_DIAGNOSTIC 0x07
70 #define CQ_TYPE_OFFLINE 0x0
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/titanic_52/usr/src/uts/sun4u/montecarlo/io/
H A Dacebus.c48 static uint_t acebus_debug_flags = 0;
57 static uint8_t acebus_cache_line_size = 0x10; /* 64 bytes */
58 static uint8_t acebus_latency_timer = 0x40; /* 64 PCI cycles */
115 0, /* (*bus_get_eventcookie)(); */
116 0, /* (*bus_add_eventcall)(); */
117 0, /* (*bus_remove_eventcall)(); */
118 0, /* (*bus_post_event)(); */
119 0, /* (*bus_intr_ctl)(); */
132 0,
139 (struct cb_ops *)0,
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/titanic_52/usr/src/uts/common/sys/scsi/adapters/pmcs/
H A Dpmcs_reg.h36 #define PMCS_VENDOR_ID 0x11F8
37 #define PMCS_DEVICE_ID 0x8001
39 #define PMCS_PM8001_REV_A 0
77 #define PMCS_MSGU_IBDB 0x04 /* Inbound Doorbell */
78 #define PMCS_MSGU_IBDB_CLEAR 0x20 /* InBound Doorbell Clear */
79 #define PMCS_MSGU_OBDB 0x3c /* OutBound Doorbell */
80 #define PMCS_MSGU_OBDB_CLEAR 0x40 /* OutBound Doorbell Clear */
81 #define PMCS_MSGU_SCRATCH0 0x44 /* Scratchpad 0 */
82 #define PMCS_MSGU_SCRATCH1 0x4
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/titanic_52/usr/src/lib/libprtdiag_psr/sparc/cherrystone/common/
H A Dworkfile.c36 #define PD_SUCCESS 0
125 if ((strcmp(name, "pci") == 0) && (compatible != NULL) && in dev_find_node_by_compat()
126 (strcmp(compatible, compat) == 0)) { in dev_find_node_by_compat()
176 if (strcmp(name, child_name) == 0) in find_child_device()
189 if (strcmp(name, child_name) == 0) in find_child_device()
244 if (err != 0) { in fill_device_from_id()
262 int devs = 0; in fill_device_array_from_id()
277 while (picl_get_next_by_row(entry, &entry) == 0) in fill_device_array_from_id()
292 for (i = 0; i < devs; i++) { in fill_device_array_from_id()
294 if (err != 0) { in fill_device_array_from_id()
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H A Dcherrystone.c127 int ecache_size_prev = 0; in display_cpus()
149 if ((impl == NULL) || (freq == 0) || (node_failed(cpu))) in display_cpus()
181 ecache_size_prev = 0; in display_cpus()
190 log_printf("%3d,%3d ", mid_prev, *mid, 0); in display_cpus()
197 if (ecache_size == 0) in display_cpus()
227 (*mask >> 4) & 0xf, *mask & 0xf); in display_cpus()
310 (void) memset(&card, 0, sizeof (struct io_card)); in display_pci()
333 slot_name_arr[0] = (char *)value + sizeof (int); in display_pci()
397 assert(0); in display_io_cards()
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/titanic_52/usr/src/lib/libprtdiag_psr/sparc/daktari/common/
H A Dworkfile.c41 #define DAK_SAFARI_ID_MASK 0x1F /* 5 bits */
42 #define DAK_NODE_MASK 0x1F /* 5 bits */
44 #define DAK_MIN_CPU_SAFARI_ID 0 /* 0x00 */
45 #define DAK_MAX_CPU_SAFARI_ID 23 /* 0x17 */
46 #define DAK_MIN_IO_SAFARI_ID 24 /* 0x18 */
47 #define DAK_MAX_IO_SAFARI_ID 31 /* 0x1F */
153 if (strcmp("name", (char *)prop->name.val_ptr) == 0) in get_node_name()
175 if (strcmp("device_type", (char *)prop->name.val_ptr) == 0) in get_node_type()
323 if ((strcmp(name, "pci") == 0) in dev_find_node_by_compat()
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H A Ddaktari.c112 int exit_code = 0; /* init to all OK */ in error_check()
116 print_flag = 0; in error_check()
137 int exit_code = 0; in disp_fail_parts()
138 int system_failed = 0; in disp_fail_parts()
149 if (print_flag == 0) { in disp_fail_parts()
211 "module Board %d Module %d\n"), 0, in disp_fail_parts()
233 return (0); in disp_fail_parts()
327 int ecache_size_prev = 0; in display_cpus()
348 if ((impl == NULL) || (freq == 0) || (node_failed(cpu))) in display_cpus()
382 ecache_size_prev = 0; in display_cpus()
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/titanic_52/usr/src/lib/libprtdiag_psr/sparc/littleneck/common/
H A Dworkfile.c76 #define LNECK_SAFARI_ID_MASK 0x1F /* 5 bits */
77 #define LNECK_NODE_MASK 0x1F /* 5 bits */
79 #define LNECK_MIN_CPU_SAFARI_ID 0 /* 0x00 */
80 #define LNECK_MAX_CPU_SAFARI_ID 23 /* 0x17 */
81 #define LNECK_MIN_IO_SAFARI_ID 24 /* 0x18 */
82 #define LNECK_MAX_IO_SAFARI_ID 31 /* 0x1F */
204 if ((strcmp(name, "pci") == 0) && (compatible != NULL) && in dev_find_node_by_compat()
205 (strcmp(compatible, compat) == 0)) { in dev_find_node_by_compat()
255 if (strcmp(name, child_name) == 0) in find_child_device()
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H A Dlittleneck.c65 int ps_failure = 0;
71 int print_flag = 0;
107 int exit_code = 0; /* init to all OK */ in error_check()
109 print_flag = 0; in error_check()
178 if ((freq != 0) && (node_failed(cpu) == 0)) { in display_cpus()
185 case 0: in display_cpus()
202 if (ecache_size == 0) in display_cpus()
214 log_printf("%-7s ", "US-III", 0); in display_cpus()
216 log_printf("%-7s ", "US-III+", 0); in display_cpus()
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/titanic_52/usr/src/lib/libprtdiag_psr/sparc/serengeti/common/
H A Dserengeti.c63 #define ACTIVE 0
91 #define SG_SCHIZO_GOOD 0
184 int i = 0; in printfindent()
185 for (i = 0; i < indent; i ++) in printfindent()
217 int pci_bridge = 0; in display_pci()
222 int level = 0; in display_pci()
289 slot_name_arr[0] = (char *)value + sizeof (int); in display_pci()
291 D_PRINTFINDENT(0, "slot_name_arr[0] is [%s]\n", in display_pci()
292 slot_name_arr[0]); in display_pci()
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/titanic_52/usr/src/lib/libprtdiag_psr/sparc/starcat/common/
H A Dstarcat.c59 #define PORTID_TO_EXPANDER(p) (((p) >> 5) & 0x1f)
60 #define PORTID_TO_SLOT(p) (((p) >> 3) & 0x1)
61 #define PORTID_TO_INSTANCE(p) ((p) & 0x3)
119 int slot_name_offset = 0; in display_pci()
125 int pci_bridge = 0; in display_pci()
203 if (slot_name_bits > 0) in display_pci()
207 for (i = 0; i < MAX_SLOTS_PER_IO_BD; i++) { in display_pci()
232 pci_bridge = 0; in display_pci()
249 card.dev_no = (((*int_val) & 0xF800) >> 11); in display_pci()
250 card.func_no = (((*int_val) & 0x70 in display_pci()
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/titanic_52/usr/src/uts/sun4u/starcat/io/
H A Ddrmach.c120 #define DRMACH_SLICE_MASK 0x1Full
137 #define DRMACH_MC_ASI_ADDR(mp, bank) (DRMACH_MC_ADDR(mp, bank) & 0xFF)
139 #define DRMACH_EMU_ACT_STATUS_OFFSET 0x50
150 #define DRMACH_LPA_BASE_MASK (0x3Full << 3)
151 #define DRMACH_LPA_BND_MASK (0x3Full << 9)
159 (((b)->flags & DRMACH_NULL_PROC_LPA) == 0)
161 #define DRMACH_CPU_SRAM_ADDR 0x7fff0900000ull
162 #define DRMACH_CPU_SRAM_SIZE 0x20000ull
181 #define DRMACH_NULL_PROC_LPA 0x1
332 * There is a known HW bug where a Jaguar CPU in Safari port 0 (SB
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H A Dschpc.c59 int schpc_dump_save_regs = 0;
60 static uint_t schpc_debug_flags = 0;
87 #define D_IDENTIFY 0x00000001
88 #define D_ATTACH 0x00000002
89 #define D_DETACH 0x00000004
90 #define D_OPEN 0x00000008
91 #define D_GETSLOTSTATUS 0x00000010
92 #define D_SETSLOTSTATUS 0x00000020
93 #define D_IOCTL 0x00010000
94 #define D_IOC_CONNECT 0x0002000
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/titanic_52/usr/src/uts/common/io/zyd/
H A Dzyd_reg.h35 #define ZYD_CR_GPI_EN 0x9418
36 #define ZYD_CR_RADIO_PD 0x942c
37 #define ZYD_CR_RF2948_PD 0x942c
38 #define ZYD_CR_EN_PS_MANUAL_AGC 0x943c
39 #define ZYD_CR_CONFIG_PHILIPS 0x9440
40 #define ZYD_CR_I2C_WRITE 0x9444
41 #define ZYD_CR_SA2400_SER_RP 0x9448
42 #define ZYD_CR_RADIO_PE 0x9458
43 #define ZYD_CR_RST_BUS_MASTER 0x945c
44 #define ZYD_CR_RFCFG 0x946
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/titanic_52/usr/src/uts/common/io/chxge/
H A Dpe.c103 #define TID_MASK 0xffffff
113 * May be set in /etc/system to 0 to use default latency timer for 10G.
114 * See PCI register 0xc definition.
119 * May be set in /etc/system to 0 to disable hardware checksum for
153 int i = 0; in pe_init()
163 if (sa->init_counter == 0) { in pe_init()
169 if (sa->port[i].line_up == 0) { in pe_init()
262 cmdQ_ce_t *hmp = &cm[0]; /* head of cm table (may be kmem_alloed) */ in pe_start()
263 int cm_flg = 0; /* flag (1 - if kmem-alloced) */ in pe_start()
264 int nseg = 0; /* numbe in pe_start()
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