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/titanic_52/usr/src/boot/sys/boot/i386/common/
H A Ddrv.c41 v86.addr = 0x13; in drvsize()
42 v86.eax = 0x4800; in drvsize()
48 printf("error %u\n", v86.eax >> 8 & 0xff); in drvsize()
49 return (0); in drvsize()
62 static unsigned c = 0x2d5c7c2f; in drvread()
73 v86.addr = 0x13; in drvread()
74 v86.eax = 0x4200; in drvread()
90 BOOTPROG, v86.eax >> 8 & 0xff, lba); in drvread()
93 return (0); in drvread()
[all...]
/titanic_52/usr/src/data/perfmon/GLP/
H A Dgoldmontplus_matrix_v1.01.json5 "MATRIX_VALUE": "0x0001 ",
6 "MATRIX_REGISTER": "0,1",
12 "MATRIX_VALUE": "0x0002 ",
13 "MATRIX_REGISTER": "0,1",
19 "MATRIX_VALUE": "0x0004 ",
20 "MATRIX_REGISTER": "0,1",
26 "MATRIX_VALUE": "0x0008 ",
27 "MATRIX_REGISTER": "0,1",
33 "MATRIX_VALUE": "0x0010 ",
34 "MATRIX_REGISTER": "0,
2 { global() object
[all...]
/titanic_52/usr/src/data/perfmon/GLM/
H A Dgoldmont_matrix_v13.json5 "MATRIX_VALUE": "0x0001 ",
6 "MATRIX_REGISTER": "0,1",
12 "MATRIX_VALUE": "0x0002 ",
13 "MATRIX_REGISTER": "0,1",
19 "MATRIX_VALUE": "0x0004 ",
20 "MATRIX_REGISTER": "0,1",
26 "MATRIX_VALUE": "0x0008 ",
27 "MATRIX_REGISTER": "0",
33 "MATRIX_VALUE": "0x0010 ",
34 "MATRIX_REGISTER": "0,
2 { global() object
[all...]
/titanic_52/usr/src/boot/sys/boot/fdt/dts/arm/
H A Dannapurna-alpine.dts43 #size-cells = <0>;
45 cpu@0 {
48 reg = <0x0>;
51 d-cache-size = <0x8000>; // L1, 32K
52 i-cache-size = <0x8000>; // L1, 32K
53 timebase-frequency = <0>;
55 clock-frequency = <0>;
61 reg = <0x0>;
64 d-cache-size = <0x8000>; // L1, 32K
65 i-cache-size = <0x800
[all...]
/titanic_52/usr/src/uts/i86pc/os/
H A Dbiosdisk.c47 #define BIOS_RES_BUFFER_ADDR 0x7000
50 #define STARTING_DRVNUM 0x80
51 #define FP_OFF(fp) (((uintptr_t)(fp)) & 0xFFFF)
52 #define FP_SEG(fp) ((((uintptr_t)(fp)) >> 16) & 0xFFFF)
55 int biosdebug = 0;
63 biosdev_data_t biosdev_info[BIOSDEV_NUM]; /* from 0x80 to 0x87 */
78 int got_devparams = 0; in startup_bios_disk()
79 int got_first_block = 0; in startup_bios_disk()
89 if (dobiosdev == 0) in startup_bios_disk()
[all...]
/titanic_52/usr/src/grub/grub-0.97/stage2/
H A Dbios.c36 #if 0
49 return the error number. Otherwise, return 0. */ in biosdisk()
76 /* FIXME: sizeof (DAP) must be 0x10. Should assert that the compiler in biosdisk()
81 dap.reserved = 0; in biosdisk()
85 err = biosdisk_int13_extensions ((read + 0x42) << 8, drive, &dap); in biosdisk()
90 if (err == 0 && dap.blocks != nsec) in biosdisk()
123 err = biosdisk_standard (read + 0x02, drive, in biosdisk()
154 grub_memset (&cdrp, 0, sizeof (cdrp)); in get_cdinfo()
156 err = biosdisk_int13_extensions (0x4B01, drive, &cdrp); in get_cdinfo()
159 if ((cdrp.media_type & 0x0 in get_cdinfo()
[all...]
H A Dshared.h48 #define ZFS_SCRATCH_SIZE 0x400000
59 #define BOOTSIGN_ARGLEN (MAXNAMELEN + 10) /* (<sign>,0,d) */
67 #define MAXINT 0x7FFFFFFF
68 #define MAXUINT 0xFFFFFFFF
76 #define SCRATCHADDR RAW_ADDR (0x77e00)
77 #define SCRATCHSEG RAW_SEG (0x77e0)
84 #define BUFFERLEN 0x7e00
85 #define BUFFERADDR RAW_ADDR (0x70000)
86 #define BUFFERSEG RAW_SEG (0x7000)
88 #define BOOT_PART_TABLE RAW_ADDR (0x07b
[all...]
/titanic_52/usr/src/uts/sun4u/sys/
H A Dsysiosbus.h51 #define NATURAL_REG_SIZE 0x8 /* 8 Bytes is Fusion reg size */
52 #define MIN_REG_SIZE 0x4 /* Smallest Fusion reg size */
53 #define OFF_SYSIO_CTRL_REG 0x10
55 #define OFF_SBUS_CTRL_REG 0x2000
57 #define OFF_SBUS_SLOT_CONFIG 0x2020
59 #define OFF_INTR_MAPPING_REG 0x2c00
61 #define INTR_MAPPING_REG_SIZE 0x490
62 #define OFF_CLR_INTR_REG 0x3408
64 #define CLR_INTR_REG_SIZE 0x488
65 #define OFF_INTR_RETRY_REG 0x2c2
[all...]
/titanic_52/usr/src/uts/common/io/elxl/
H A Delxl.h44 #define REG_CMD_STAT 0x0e /* Write command, read status */
46 #define CMD_GLOBAL_RESET 0x0000
47 #define CMD_SELECT_WINDOW 0x0800
48 #define CMD_BNC_ENABLE 0x1000 /* enable 10BASE2 DC-DC converter */
49 #define CMD_RX_DISABLE 0x1800
50 #define CMD_RX_ENABLE 0x2000
51 #define CMD_RX_RESET 0x2800
52 #define CMD_UP_STALL 0x3000
53 #define CMD_UP_UNSTALL 0x3001
54 #define CMD_DN_STALL 0x300
[all...]
/titanic_52/usr/src/uts/common/io/fibre-channel/fca/qlc/
H A Dql_fw_2300.c53 unsigned short qlc_fw2300cs2_addr01 = 0x0800;
55 unsigned short risc_code_addr01 = 0x0800;
63 0x0470, 0x0000, 0x0000, 0xe8e8, 0x0000, 0x0003, 0x0003, 0x001
[all...]
/titanic_52/usr/src/grub/grub-0.97/netboot/
H A D3c595.h58 #define EEPROMSIZE 0x40
60 #define VX_LAST_TAG 0xd7
62 #define VX_ID_PORT 0x100
70 * Commands to read/write EEPROM trough EEPROM command register (Window 0,
71 * Offset 0xa)
73 #define EEPROM_CMD_RD 0x0080 /* Read: Address required (5 bits) */
74 #define EEPROM_CMD_WR 0x0040 /* Write: Address required (5 bits) */
75 #define EEPROM_CMD_ERASE 0x00c0 /* Erase: Address required (5 bits) */
76 #define EEPROM_CMD_EWEN 0x0030 /* Erase/Write Enable: No data required */
94 #define EEPROM_NODE_ADDR_0 0x
[all...]
H A Deepro100.c84 * 0x94000 to 0xa0000. There is just a little room between the end of
85 * this driver and the 0xa0000 address. If you compile in too many
112 SCBStatus = 0, SCBCmd = 2, /* Rx/Command Unit command and status. */
121 SCBMaskCmdDone=0x8000, SCBMaskRxDone=0x4000, SCBMaskCmdIdle=0x2000,
122 SCBMaskRxSuspend=0x1000, SCBMaskEarlyRx=0x0800, SCBMaskFlowCtl=0x040
[all...]
H A Ddavicom.c61 CSR0=0, CSR1=0x08, CSR2=0x10, CSR3=0x18, CSR4=0x20, CSR5=0x28,
62 CSR6=0x30, CSR7=0x38, CSR8=0x40, CSR9=0x4
[all...]
H A Dpci_ids.h9 #define PCI_CLASS_NOT_DEFINED 0x0000
10 #define PCI_CLASS_NOT_DEFINED_VGA 0x0001
12 #define PCI_BASE_CLASS_STORAGE 0x01
13 #define PCI_CLASS_STORAGE_SCSI 0x0100
14 #define PCI_CLASS_STORAGE_IDE 0x0101
15 #define PCI_CLASS_STORAGE_FLOPPY 0x0102
16 #define PCI_CLASS_STORAGE_IPI 0x0103
17 #define PCI_CLASS_STORAGE_RAID 0x0104
18 #define PCI_CLASS_STORAGE_OTHER 0x0180
20 #define PCI_BASE_CLASS_NETWORK 0x0
[all...]
H A Dtg3.h18 #define ADVERTISED_10baseT_Half (1 << 0)
38 #define SPEED_10 0
45 #define DUPLEX_HALF 0x00
46 #define DUPLEX_FULL 0x01
47 #define DUPLEX_INVALID 0x02
50 #define PORT_TP 0x00
51 #define PORT_AUI 0x01
52 #define PORT_MII 0x02
53 #define PORT_FIBRE 0x03
54 #define PORT_BNC 0x0
[all...]
H A Dtulip.c58 support LNE100TX v2.0 cards, which use a different controller.
115 static int tulip_debug = 2; /* 1 normal messages, 0 quiet .. 7 verbose. */
135 #define TULIP_SIZE 0x80
141 #define FULL_DUPLEX_MAGIC 0x6969
143 static const int csr0 = 0x01A00000 | 0x8000;
157 DC21040=0, DC21041=1, DC21140=2, DC21142=3, DC21143=3,
166 PCI_ADDR0=0<<4, PCI_ADDR1=1<<4, PCI_ADDR2=2<<4, PCI_ADDR3=3<<4,
167 PCI_ADDR_64BITS=0x100, PCI_NO_ACPI_WAKE=0x20
[all...]
/titanic_52/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/fw/
H A D57710_int_offsets.h34 { 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_SB_SIZE
35 { 0x40, 0x0, 0x0, 0x0, 0x
[all...]
/titanic_52/usr/src/boot/sys/boot/i386/libi386/
H A Dvidconsole.c55 #define DEFAULT_BGCOLOR 0
78 0,
109 if (vidc_started && arg == 0) in vidc_init()
110 return (0); in vidc_init()
119 memset(keybuf, 0, KEYBUFSZ); in vidc_init()
121 for (i = 0; i < 10 && vidc_ischar(cp); i++) in vidc_init()
123 return (0); /* XXX reinit? */ in vidc_init()
130 v86.ctl = 0; in vidc_biosputchar()
131 v86.addr = 0x10; in vidc_biosputchar()
132 v86.eax = 0xe0 in vidc_biosputchar()
[all...]
H A Dbiosdisk.c54 #define BIOS_NUMDRIVES 0x475
58 #define DT_ATAPI 0x10 /* disk type for ATAPI floppies */
59 #define WDMAJOR 0 /* major numbers for devices we frontend for */
81 #define BD_MODEINT13 0x0000
82 #define BD_MODEEDD1 0x0001
83 #define BD_MODEEDD3 0x0002
84 #define BD_MODEMASK 0x0003
85 #define BD_FLOPPY 0x0004
92 static int nbdinfo = 0;
129 DEBUG("looking for bios device 0 in bd_bios2unit()
[all...]
/titanic_52/usr/src/uts/common/io/bge/
H A Dbge_hw.h56 #define VENDOR_ID_BROADCOM 0x14e4
57 #define VENDOR_ID_SUN 0x108e
59 #define DEVICE_ID_5700 0x1644
60 #define DEVICE_ID_5700x 0x0003
61 #define DEVICE_ID_5701 0x1645
62 #define DEVICE_ID_5702 0x16a6
63 #define DEVICE_ID_5702fe 0x164d
64 #define DEVICE_ID_5703C 0x16a7
65 #define DEVICE_ID_5703S 0x1647
66 #define DEVICE_ID_5703 0x16c
[all...]
/titanic_52/usr/src/cmd/localedef/data/
H A Dzh_MO.UTF-8.src6948 collating-symbol <X4800>
7312 <X4800>
7752 <CJK_UNIFIED_IDEOGRAPH-4E9E> "<XE005><X4800>";<X05>;"<X05><XC0>";<CJK_UNIFIED_IDEOGRAPH-4E9E>
8212 <CJK_UNIFIED_IDEOGRAPH-5B50> "<XE01F><X4800>";<X05>;"<X05><XC0>";<CJK_UNIFIED_IDEOGRAPH-5B50>
8397 <CJK_UNIFIED_IDEOGRAPH-5FB5> "<XE028><X4800>";<X05>;"<X05><XC0>";<CJK_UNIFIED_IDEOGRAPH-5FB5>
8642 <CJK_UNIFIED_IDEOGRAPH-660E> "<XE035><X4800>";<X05>;"<X05><XC0>";<CJK_UNIFIED_IDEOGRAPH-660E>
8677 <CJK_UNIFIED_IDEOGRAPH-6708> "<XE037><X4800>";<X05>;"<X05><XC0>";<CJK_UNIFIED_IDEOGRAPH-6708>
8955 <CJK_UNIFIED_IDEOGRAPH-72C0> "<XE04F><X4800>";<X05>;"<X05><XC0>";<CJK_UNIFIED_IDEOGRAPH-72C0>
9007 <CJK_UNIFIED_IDEOGRAPH-7531> "<XE054><X4800>";<X05>;"<X05><XC0>";<CJK_UNIFIED_IDEOGRAPH-7531>
9089 <CJK_UNIFIED_IDEOGRAPH-7919> "<XE05C><X4800>";<X0
[all...]
H A Dzh_HK.UTF-8.src6948 collating-symbol <X4800>
7312 <X4800>
7752 <CJK_UNIFIED_IDEOGRAPH-4E9E> "<XE005><X4800>";<X05>;"<X05><XC0>";<CJK_UNIFIED_IDEOGRAPH-4E9E>
8212 <CJK_UNIFIED_IDEOGRAPH-5B50> "<XE01F><X4800>";<X05>;"<X05><XC0>";<CJK_UNIFIED_IDEOGRAPH-5B50>
8397 <CJK_UNIFIED_IDEOGRAPH-5FB5> "<XE028><X4800>";<X05>;"<X05><XC0>";<CJK_UNIFIED_IDEOGRAPH-5FB5>
8642 <CJK_UNIFIED_IDEOGRAPH-660E> "<XE035><X4800>";<X05>;"<X05><XC0>";<CJK_UNIFIED_IDEOGRAPH-660E>
8677 <CJK_UNIFIED_IDEOGRAPH-6708> "<XE037><X4800>";<X05>;"<X05><XC0>";<CJK_UNIFIED_IDEOGRAPH-6708>
8955 <CJK_UNIFIED_IDEOGRAPH-72C0> "<XE04F><X4800>";<X05>;"<X05><XC0>";<CJK_UNIFIED_IDEOGRAPH-72C0>
9007 <CJK_UNIFIED_IDEOGRAPH-7531> "<XE054><X4800>";<X05>;"<X05><XC0>";<CJK_UNIFIED_IDEOGRAPH-7531>
9089 <CJK_UNIFIED_IDEOGRAPH-7919> "<XE05C><X4800>";<X0
[all...]
H A Dzh_TW.UTF-8.src6948 collating-symbol <X4800>
7312 <X4800>
7752 <CJK_UNIFIED_IDEOGRAPH-4E9E> "<XE005><X4800>";<X05>;"<X05><XC0>";<CJK_UNIFIED_IDEOGRAPH-4E9E>
8212 <CJK_UNIFIED_IDEOGRAPH-5B50> "<XE01F><X4800>";<X05>;"<X05><XC0>";<CJK_UNIFIED_IDEOGRAPH-5B50>
8397 <CJK_UNIFIED_IDEOGRAPH-5FB5> "<XE028><X4800>";<X05>;"<X05><XC0>";<CJK_UNIFIED_IDEOGRAPH-5FB5>
8642 <CJK_UNIFIED_IDEOGRAPH-660E> "<XE035><X4800>";<X05>;"<X05><XC0>";<CJK_UNIFIED_IDEOGRAPH-660E>
8677 <CJK_UNIFIED_IDEOGRAPH-6708> "<XE037><X4800>";<X05>;"<X05><XC0>";<CJK_UNIFIED_IDEOGRAPH-6708>
8955 <CJK_UNIFIED_IDEOGRAPH-72C0> "<XE04F><X4800>";<X05>;"<X05><XC0>";<CJK_UNIFIED_IDEOGRAPH-72C0>
9007 <CJK_UNIFIED_IDEOGRAPH-7531> "<XE054><X4800>";<X05>;"<X05><XC0>";<CJK_UNIFIED_IDEOGRAPH-7531>
9089 <CJK_UNIFIED_IDEOGRAPH-7919> "<XE05C><X4800>";<X0
[all...]
H A Dsa_IN.UTF-8.src5257 collating-symbol <X4800>
5433 <X4800>
5652 <o> <X4800>;<X05>;<X05>;IGNORE
5653 <O> <X4800>;<X05>;<X8F>;IGNORE
5796 p_sep_by_space 0
5798 n_sep_by_space 0
5802 int_p_sep_by_space 0
5804 int_n_sep_by_space 0
/titanic_52/usr/src/lib/iconv_modules/inc/
H A Dbig5hk_unicode.h46 { 0x8840, 0xf303 },
47 { 0x8841, 0xf304 },
48 { 0x8842, 0xf305 },
49 { 0x8843, 0xf306 },
50 { 0x8844, 0xf30
[all...]

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