Searched +full:0 +full:x400a1000 (Results 1 – 6 of 6) sorted by relevance
9 - #size-cells: should be <0>18 reg = <0x400a1000 0x1000>;22 #size-cells = <0>;30 reg = <0x48>;
49 reg = <0x400a1000 0x1000>;53 #size-cells = <0>;
16 dcr-parent = <&{/cpus/cpu@0}>;25 #size-cells = <0>;27 cpu@0 {30 reg = <0x00000000>;44 reg = <0x00000000 0x20000000>; /* Filled in by U-Boot */50 cell-index = <0>;51 dcr-reg = <0x0c0 0x010>;52 #address-cells = <0>;53 #size-cells = <0>;61 dcr-reg = <0x0d0 0x010>;[all …]
56 bus-frequency = <0>;60 reg = <0x4006E000 0x100>;65 reg = <0x40001000 0x1000>;70 reg = <0x40003000 0x1000>, /* Distributor Registers */71 <0x40002100 0x100>; /* CPU Interface Registers */78 reg = <0x40050000 0x300>;83 reg = <0x4006b000 0x1000>;91 #size-cells = <0>;92 reg = < 0x40002200 0x100 >, /* Global Timer Registers */93 < 0x40002600 0x100 >; /* Private Timer Registers */[all …]
19 #define LPC_PIN(port, pin) (0x##port * 32 + pin)28 #size-cells = <0>;30 cpu@0 {33 reg = <0x0>;41 #clock-cells = <0>;47 #clock-cells = <0>;53 #clock-cells = <0>;54 clock-frequency = <0>;60 #clock-cells = <0>;61 clock-frequency = <0>;[all...]
33 #clock-cells = <0>;39 #clock-cells = <0>;46 offset = <0x0>;47 mask = <0x1000>;66 reg = <0x40000000 0x00070000>;71 reg = <0x40001000 0x800>;76 reg = <0x40001800 0x40[all...]