Searched +full:0 +full:x324b (Results 1 – 10 of 10) sorted by relevance
31 // base address: 0x032 …DPCSSYS_CR0_SUP_DIG_IDCODE_LO 0x000033 …DPCSSYS_CR0_SUP_DIG_IDCODE_HI 0x000134 …DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN 0x000235 …DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN 0x000336 …DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x000437 …DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN 0x000538 …DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x000639 …DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0 0x000740 …DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1 0x0008[all …]
27 // base address: 0x028 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x293430 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x293535 // base address: 0x36036 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c38 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d43 // base address: 0x6c044 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae446 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae551 // base address: 0xa20[all …]
14 // base address: 0x015 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x293417 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x293522 // base address: 0x36023 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c25 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d30 // base address: 0x6c031 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae433 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae538 // base address: 0xa20[all …]
31 // base address: 0x032 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x293434 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x293539 // base address: 0x36040 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c42 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d47 // base address: 0x6c048 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae450 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae555 // base address: 0xa20[all …]
27 #define mmCB_BLEND_RED 0xa10528 #define mmCB_BLEND_GREEN 0xa10629 #define mmCB_BLEND_BLUE 0xa10730 #define mmCB_BLEND_ALPHA 0xa10831 #define mmCB_COLOR_CONTROL 0xa20232 #define mmCB_BLEND0_CONTROL 0xa1e033 #define mmCB_BLEND1_CONTROL 0xa1e134 #define mmCB_BLEND2_CONTROL 0xa1e235 #define mmCB_BLEND3_CONTROL 0xa1e336 #define mmCB_BLEND4_CONTROL 0xa1e4[all …]
27 #define mmCB_BLEND_RED 0xa10528 #define mmCB_BLEND_GREEN 0xa10629 #define mmCB_BLEND_BLUE 0xa10730 #define mmCB_BLEND_ALPHA 0xa10831 #define mmCB_DCC_CONTROL 0xa10932 #define mmCB_COLOR_CONTROL 0xa20233 #define mmCB_BLEND0_CONTROL 0xa1e034 #define mmCB_BLEND1_CONTROL 0xa1e135 #define mmCB_BLEND2_CONTROL 0xa1e236 #define mmCB_BLEND3_CONTROL 0xa1e3[all …]
27 // base address: 0x4828 …VGA_MEM_WRITE_PAGE_ADDR 0x000029 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 030 …VGA_MEM_READ_PAGE_ADDR 0x000131 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 035 // base address: 0x3b436 …CRTC8_IDX 0x002d38 …CRTC8_DATA 0x002d40 …GENFC_WT 0x002e42 …GENS1 0x002e[all …]
27 // base address: 0x028 …VGA_MEM_WRITE_PAGE_ADDR 0x000029 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 030 …VGA_MEM_READ_PAGE_ADDR 0x000131 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 032 …VGA_RENDER_CONTROL 0x000034 …VGA_SEQUENCER_RESET_CONTROL 0x000136 …VGA_MODE_CONTROL 0x000238 …VGA_SURFACE_PITCH_SELECT 0x000340 …VGA_MEMORY_BASE_ADDRESS 0x0004[all …]