Searched +full:0 +full:x30b00000 (Results 1 – 6 of 6) sorted by relevance
12 reg = <0x0 0x70000000 0x0 0x200000>;15 ranges = <0x0 0x0 0x70000000 0x200000>;17 atf-sram@0 {18 reg = <0x0 0x20000>;22 reg = <0xf0000 0x10000>;26 reg = <0x100000 0x100000>;37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */38 <0x00 0x01880000 0x00 0x90000>, /* GICR */39 <0x00 0x6f000000 0x00 0x2000>, /* GICC */40 <0x00 0x6f010000 0x00 0x1000>, /* GICH */[all …]
10 #clock-cells = <0>;18 reg = <0x00 0x70000000 0x00 0x100000>;21 ranges = <0x00 0x00 0x70000000 0x100000>;23 atf-sram@0 {24 reg = <0x00 0x20000>;30 reg = <0x00 0x00100000 0x00 0x1c000>;33 ranges = <0x00 0x00 0x00100000 0x1c000>;37 reg = <0x4080 0x20>;39 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */40 <0x8 0x3>, <0xc 0x3>; /* SERDES0 lane2/3 select */[all …]
13 #clock-cells = <0>;15 clock-frequency = <0>;22 reg = <0x0 0x70000000 0x0 0x400000>;25 ranges = <0x0 0x0 0x70000000 0x400000>;27 atf-sram@0 {28 reg = <0x0 0x20000>;32 reg = <0x1f0000 0x10000>;36 reg = <0x200000 0x200000>;42 reg = <0x00 0x00104000 0x00 0x18000>;45 ranges = <0x00 0x00 0x00104000 0x18000>;[all …]
15 #clock-cells = <0>;17 clock-frequency = <0>;21 #clock-cells = <0>;23 clock-frequency = <0>;30 reg = <0x0 0x70000000 0x0 0x800000>;33 ranges = <0x0 0x0 0x70000000 0x800000>;35 atf-sram@0 {36 reg = <0x0 0x20000>;42 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */45 ranges = <0x0 0x0 0x00100000 0x1c000>;[all …]
16 #clock-cells = <0>;26 reg = <0x00 0x70000000 0x00 0x800000>;29 ranges = <0x00 0x00 0x70000000 0x800000>;31 atf-sram@0 {32 reg = <0x00 0x20000>;36 reg = <0x1f0000 0x10000>;40 reg = <0x200000 0x200000>;46 reg = <0x00 0x00100000 0x00 0x1c000>;49 ranges = <0x00 0x00 0x00100000 0x1c000>;53 reg = <0x4034 0x4>;[all …]
1 0x00 = 0x000000002 0x01 = 0x010000003 0x02 = 0x020000004 0x03 = 0x030000005 0x04 = 0x040000006 0x05 = 0x050000007 0x06 = 0x060000008 0x07 = 0x070000009 0x08 = 0x0800000010 0x09 = 0x09000000[all …]