Searched +full:0 +full:x1e60000 (Results 1 – 4 of 4) sorted by relevance
18 pattern: "^syscon@[0-9a-f]+$"47 reg = <0x1e60000 0x10000>;52 offset = <0>;53 mask = <0x02>;
27 #size-cells = <0>;30 cpu0: cpu@0 {33 reg = <0x0>;34 clocks = <&clockgen QORIQ_CLK_CMUX 0>;42 reg = <0x1>;43 clocks = <&clockgen QORIQ_CLK_CMUX 0>;51 reg = <0x2>;52 clocks = <&clockgen QORIQ_CLK_CMUX 0>;60 reg = <0x3>;61 clocks = <&clockgen QORIQ_CLK_CMUX 0>;[all …]
33 #size-cells = <0>;38 reg = <0x00000000 0x80000000 0 0x80000000>;44 #clock-cells = <0>;51 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */52 <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */53 <0x0 0x0c0c0000 0 0x2000>, /* GICC */54 <0x0 0x0c0d0000 0 0x1000>, /* GICH */55 <0x0 0x0c0e0000 0 0x20000>; /* GICV */67 reg = <0x0 0x6020000 0 0x20000>;73 reg = <0x0 0x1e60000 0x0 0x4>;[all …]
23 #size-cells = <0>;25 cpu0: cpu@0 {28 reg = <0x0>;30 clocks = <&clockgen QORIQ_CLK_CMUX 0>;31 i-cache-size = <0xc000>;34 d-cache-size = <0x8000>;45 reg = <0x1>;47 clocks = <&clockgen QORIQ_CLK_CMUX 0>;48 i-cache-size = <0xc000>;51 d-cache-size = <0x8000>;[all …]