Searched +full:0 +full:x1d96 (Results 1 – 11 of 11) sorted by relevance
10 #define MT6358_SWCID 0xa11 #define MT6358_TOPSTATUS 0x2812 #define MT6358_TOP_RST_MISC 0x14c13 #define MT6358_MISC_TOP_INT_CON0 0x18814 #define MT6358_MISC_TOP_INT_STATUS0 0x19415 #define MT6358_TOP_INT_STATUS0 0x19e16 #define MT6358_SCK_TOP_INT_CON0 0x52e17 #define MT6358_SCK_TOP_INT_STATUS0 0x53a18 #define MT6358_EOSC_CALI_CON0 0x54019 #define MT6358_EOSC_CALI_CON1 0x542[all …]
18 #define VPP2_DUMMY_DATA 0x190019 #define VPP2_LINE_IN_LENGTH 0x190120 #define VPP2_PIC_IN_HEIGHT 0x190221 #define VPP2_SCALE_COEF_IDX 0x190322 #define VPP2_SCALE_COEF 0x190423 #define VPP2_VSC_REGION12_STARTP 0x190524 #define VPP2_VSC_REGION34_STARTP 0x190625 #define VPP2_VSC_REGION4_ENDP 0x190726 #define VPP2_VSC_START_PHASE_STEP 0x190827 #define VPP2_VSC_REGION0_PHASE_SLOPE 0x1909[all …]
26 #define ixATTR00 0x000027 #define ixATTR01 0x000128 #define ixATTR02 0x000229 #define ixATTR03 0x000330 #define ixATTR04 0x000431 #define ixATTR05 0x000532 #define ixATTR06 0x000633 #define ixATTR07 0x000734 #define ixATTR08 0x000835 #define ixATTR09 0x0009[all …]
27 #define mmPIPE0_PG_CONFIG 0x176028 #define mmPIPE0_PG_ENABLE 0x176129 #define mmPIPE0_PG_STATUS 0x176230 #define mmPIPE1_PG_CONFIG 0x176431 #define mmPIPE1_PG_ENABLE 0x176532 #define mmPIPE1_PG_STATUS 0x176633 #define mmPIPE2_PG_CONFIG 0x176834 #define mmPIPE2_PG_ENABLE 0x176935 #define mmPIPE2_PG_STATUS 0x176a36 #define mmPIPE3_PG_CONFIG 0x176c[all …]
27 #define mmPIPE0_PG_CONFIG 0x2c028 #define mmPIPE0_PG_ENABLE 0x2c129 #define mmPIPE0_PG_STATUS 0x2c230 #define mmPIPE1_PG_CONFIG 0x2c331 #define mmPIPE1_PG_ENABLE 0x2c432 #define mmPIPE1_PG_STATUS 0x2c533 #define mmPIPE2_PG_CONFIG 0x2c634 #define mmPIPE2_PG_ENABLE 0x2c735 #define mmPIPE2_PG_STATUS 0x2c836 #define mmDCFEV0_PG_CONFIG 0x2db[all …]
27 #define mmPIPE0_PG_CONFIG 0x2c028 #define mmPIPE0_PG_ENABLE 0x2c129 #define mmPIPE0_PG_STATUS 0x2c230 #define mmPIPE1_PG_CONFIG 0x2c331 #define mmPIPE1_PG_ENABLE 0x2c432 #define mmPIPE1_PG_STATUS 0x2c533 #define mmPIPE2_PG_CONFIG 0x2c634 #define mmPIPE2_PG_ENABLE 0x2c735 #define mmPIPE2_PG_STATUS 0x2c836 #define mmPIPE3_PG_CONFIG 0x2c9[all …]
27 // base address: 0x4828 …dispdec_VGA_MEM_WRITE_PAGE_ADDR 0x001229 …ne mmdispdec_VGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 033 // base address: 0x4c34 …dispdec_VGA_MEM_READ_PAGE_ADDR 0x001435 …ne mmdispdec_VGA_MEM_READ_PAGE_ADDR_BASE_IDX 039 // base address: 0x040 …DC_PERFMON0_PERFCOUNTER_CNTL 0x002042 …DC_PERFMON0_PERFCOUNTER_CNTL2 0x002144 …DC_PERFMON0_PERFCOUNTER_STATE 0x0022[all …]
27 // base address: 0x4828 …VGA_MEM_WRITE_PAGE_ADDR 0x000029 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 030 …VGA_MEM_READ_PAGE_ADDR 0x000131 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 035 // base address: 0x3b436 …CRTC8_IDX 0x002d38 …CRTC8_DATA 0x002d40 …GENFC_WT 0x002e42 …GENS1 0x002e[all …]
27 // base address: 0x130000031 // base address: 0x130000035 // base address: 0x130000039 // base address: 0x130000043 // base address: 0x130000047 // base address: 0x130002051 // base address: 0x130004055 // base address: 0x130006059 // base address: 0x130008063 // base address: 0x13000a0[all …]
27 // base address: 0x028 …VGA_MEM_WRITE_PAGE_ADDR 0x000029 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 030 …VGA_MEM_READ_PAGE_ADDR 0x000131 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 032 …VGA_RENDER_CONTROL 0x000034 …VGA_SEQUENCER_RESET_CONTROL 0x000136 …VGA_MODE_CONTROL 0x000238 …VGA_SURFACE_PITCH_SELECT 0x000340 …VGA_MEMORY_BASE_ADDRESS 0x0004[all …]