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/linux/Documentation/devicetree/bindings/clock/
H A Dhisilicon,hi3559av100-clock.yaml56 reg = <0x0 0x12010000 0x0 0x10000>;
H A Dhisi-crg.txt39 reg = <0x12010000 0x10000>;
47 reg = <0x12110000 0x1000>;
49 resets = <&CRG 0xe4 0>;
/linux/Documentation/devicetree/bindings/arm/hisilicon/controller/
H A Dsysctrl.yaml58 cpu 2, reg + 0x4;
59 cpu 3, reg + 0x8;
116 ranges = <0 0x802000 0x1000>;
117 reg = <0x802000 0x1000>;
119 smp-offset = <0x31c>;
120 resume-offset = <0x308>;
121 reboot-offset = <0x4>;
123 clock: clock@0 {
125 reg = <0 0x10000>;
133 reg = <0x10000000 0x1000>;
[all …]
/linux/arch/arm/boot/dts/hisilicon/
H A Dhi3519.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
28 reg = <0x10301000 0x1000>, <0x10302000 0x1000>;
33 #clock-cells = <0>;
41 reg = <0x12010000 0x10000>;
53 reg = <0x12100000 0x1000>;
62 reg = <0x12101000 0x1000>;
71 reg = <0x12102000 0x1000>;
80 reg = <0x12103000 0x1000>;
[all …]
/linux/arch/riscv/boot/dts/starfive/
H A Djh7110.dtsi20 #size-cells = <0>;
22 S7_0: cpu@0 {
24 reg = <0>;
200 cpu_opp: opp-table-0 {
260 #clock-cells = <0>;
265 #clock-cells = <0>;
271 #clock-cells = <0>;
277 #clock-cells = <0>;
283 #clock-cells = <0>;
289 #clock-cells = <0>;
[all …]