Home
last modified time | relevance | path

Searched +full:0 +full:x101c0000 (Results 1 – 10 of 10) sorted by relevance

/linux/arch/mips/boot/dts/ralink/
H A Drt3050.dtsi8 cpu@0 {
14 #address-cells = <0>;
22 reg = <0x10000000 0x200000>;
23 ranges = <0x0 0x10000000 0x1FFFFF>;
28 sysc@0 {
30 reg = <0x0 0x100>;
35 reg = <0x200 0x100>;
46 reg = <0x300 0x100>;
51 reg = <0xc00 0x100>;
62 reg = <0x101c0000 40000>;
H A Dmt7628a.dtsi10 #size-cells = <0>;
12 cpu@0 {
15 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10000000 0x200000>;
34 ranges = <0x0 0x10000000 0x1FFFFF>;
39 sysc: system-controller@0 {
41 reg = <0x0 0x60>;
46 reg = <0x60 0x8>;
48 #size-cells = <0>;
[all …]
/linux/arch/mips/include/asm/mach-ralink/
H A Drt3883.h15 #define RT3883_SDRAM_BASE 0x00000000
16 #define RT3883_SYSC_BASE IOMEM(0x10000000)
17 #define RT3883_TIMER_BASE 0x10000100
18 #define RT3883_INTC_BASE 0x10000200
19 #define RT3883_MEMC_BASE 0x10000300
20 #define RT3883_UART0_BASE 0x10000500
21 #define RT3883_PIO_BASE 0x10000600
22 #define RT3883_FSCC_BASE 0x10000700
23 #define RT3883_NANDC_BASE 0x10000810
24 #define RT3883_I2C_BASE 0x10000900
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos54xx.dtsi42 <7 0>,
60 reg = <0x02020000 0x54000>;
63 ranges = <0 0x02020000 0x54000>;
65 smp-sram@0 {
67 reg = <0x0 0x1000>;
72 reg = <0x53000 0x1000>;
79 reg = <0x101c0000 0xb00>;
96 reg = <0x101d0000 0x100>;
102 reg = <0x12d10000 0x100>;
111 reg = <0x12ca0000 0x1000>;
[all …]
H A Dexynos5250.dtsi47 #size-cells = <0>;
60 cpu0: cpu@0 {
63 reg = <0>;
80 cpu0_opp_table: opp-table-0 {
176 reg = <0x02020000 0x30000>;
179 ranges = <0 0x02020000 0x30000>;
181 smp-sram@0 {
183 reg = <0x0 0x1000>;
188 reg = <0x2f000 0x1000>;
194 reg = <0x10044000 0x20>;
[all …]
/linux/Documentation/devicetree/bindings/timer/
H A Dsamsung,exynos4210-mct.yaml68 0: Global Timer Interrupt 0
72 4: Local Timer Interrupt 0
166 reg = <0x10050000 0x800>;
186 reg = <0x101C0000 0x800>;
207 reg = <0x10050000 0x800>;
227 reg = <0x10050000 0x800>;
/linux/arch/arm/boot/dts/rockchip/
H A Drk3xxx.dtsi39 #clock-cells = <0>;
45 reg = <0x10090000 0x10000>;
56 reg = <0x10104000 0x800>;
68 reg = <0x10138000 0x1000>;
75 reg = <0x1013c000 0x100>;
80 reg = <0x1013c200 0x20>;
94 reg = <0x1013c600 0x20>;
103 reg = <0x1013d000 0x1000>,
104 <0x1013c100 0x0100>;
109 reg = <0x10124000 0x400>;
[all …]
H A Drk3036.dtsi37 #size-cells = <0>;
43 reg = <0xf00>;
56 reg = <0xf01>;
87 #clock-cells = <0>;
92 reg = <0x10080000 0x2000>;
95 ranges = <0 0x10080000 0x2000>;
97 smp-sram@0 {
99 reg = <0x00 0x10>;
105 reg = <0x10090000 0x10000>;
125 reg = <0x10108000 0x800>;
[all …]
H A Drk3128.dtsi44 #size-cells = <0>;
50 reg = <0xf00>;
61 reg = <0xf01>;
69 reg = <0xf02>;
77 reg = <0xf03>;
83 cpu_opp_table: opp-table-0 {
159 #clock-cells = <0>;
164 reg = <0x10080000 0x2000>;
167 ranges = <0 0x10080000 0x2000>;
169 smp-sram@0 {
[all …]
/linux/arch/arm64/boot/dts/exynos/
H A Dexynos5433.dtsi48 #clock-cells = <0>;
53 #size-cells = <0>;
91 reg = <0x100>;
96 i-cache-size = <0x8000>;
99 d-cache-size = <0x8000>;
109 reg = <0x101>;
112 i-cache-size = <0x8000>;
115 d-cache-size = <0x8000>;
125 reg = <0x102>;
128 i-cache-size = <0x8000>;
[all …]