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/linux/drivers/gpu/drm/msm/adreno/
H A Da4xx_gpu.c30 for (i = 0; i < submit->nr_cmds; i++) { in a4xx_submit()
61 OUT_RING(ring, 0x00000000); in a4xx_submit()
80 for (i = 0; i < 4; i++) in a4xx_enable_hwcg()
81 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_TP(i), 0x02222202); in a4xx_enable_hwcg()
82 for (i = 0; i < 4; i++) in a4xx_enable_hwcg()
83 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_TP(i), 0x00002222); in a4xx_enable_hwcg()
84 for (i = 0; i < 4; i++) in a4xx_enable_hwcg()
85 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_TP(i), 0x0E739CE7); in a4xx_enable_hwcg()
86 for (i = 0; i < 4; i++) in a4xx_enable_hwcg()
87 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_TP(i), 0x00111111); in a4xx_enable_hwcg()
[all …]
H A Da3xx_gpu.c36 for (i = 0; i < submit->nr_cmds; i++) { in a3xx_submit()
67 OUT_RING(ring, 0x00000000); in a3xx_submit()
75 #if 0 in a3xx_submit()
79 OUT_RING(ring, 0x00000000); in a3xx_submit()
87 struct msm_ringbuffer *ring = gpu->rb[0]; in a3xx_me_init()
90 OUT_RING(ring, 0x000003f7); in a3xx_me_init()
91 OUT_RING(ring, 0x00000000); in a3xx_me_init()
92 OUT_RING(ring, 0x00000000); in a3xx_me_init()
93 OUT_RING(ring, 0x00000000); in a3xx_me_init()
94 OUT_RING(ring, 0x00000080); in a3xx_me_init()
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/linux/drivers/video/fbdev/kyro/
H A DSTG4000Reg.h54 NO_LUT = 0, RESERVED, GRAPHICS, OVERLAY
59 _8BPP = 0, _15BPP, _16BPP, _24BPP, _32BPP
64 GRAPHICS_MODE = 0, COLOR_KEY, PER_PIXEL_ALPHA, GLOBAL_ALPHA,
75 /* 0h */
76 volatile u32 Thread0Enable; /* 0x0000 */
77 volatile u32 Thread1Enable; /* 0x0004 */
78 volatile u32 Thread0Recover; /* 0x0008 */
79 volatile u32 Thread1Recover; /* 0x000C */
80 volatile u32 Thread0Step; /* 0x0010 */
81 volatile u32 Thread1Step; /* 0x0014 */
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/linux/lib/crc/
H A Dcrc16.c11 /** CRC table for the CRC-16. The poly is 0x8005 (x^16 + x^15 + x^2 + 1) */
13 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
14 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
15 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
16 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
17 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
18 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
19 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
20 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
21 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
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/linux/include/linux/bcma/
H A Dbcma_driver_pcie2.h5 #define BCMA_CORE_PCIE2_CLK_CONTROL 0x0000
6 #define PCIE2_CLKC_RST_OE 0x0001 /* When set, drives PCI_RESET out to pin */
7 #define PCIE2_CLKC_RST 0x0002 /* Value driven out to pin */
8 #define PCIE2_CLKC_SPERST 0x0004 /* SurvivePeRst */
9 #define PCIE2_CLKC_DISABLE_L1CLK_GATING 0x0010
10 #define PCIE2_CLKC_DLYPERST 0x0100 /* Delay PeRst to CoE Core */
11 #define PCIE2_CLKC_DISSPROMLD 0x0200 /* DisableSpromLoadOnPerst */
12 #define PCIE2_CLKC_WAKE_MODE_L2 0x1000 /* Wake on L2 */
13 #define BCMA_CORE_PCIE2_RC_PM_CONTROL 0x0004
14 #define BCMA_CORE_PCIE2_RC_PM_STATUS 0x0008
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H A Dbcma_driver_chipcommon.h10 #define BCMA_CC_ID 0x0000
11 #define BCMA_CC_ID_ID 0x0000FFFF
12 #define BCMA_CC_ID_ID_SHIFT 0
13 #define BCMA_CC_ID_REV 0x000F0000
15 #define BCMA_CC_ID_PKG 0x00F00000
17 #define BCMA_CC_ID_NRCORES 0x0F000000
19 #define BCMA_CC_ID_TYPE 0xF0000000
21 #define BCMA_CC_CAP 0x0004 /* Capabilities */
22 #define BCMA_CC_CAP_NRUART 0x00000003 /* # of UARTs */
23 #define BCMA_CC_CAP_MIPSEB 0x00000004 /* MIPS in BigEndian Mode */
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/linux/drivers/media/platform/st/sti/bdisp/
H A Dbdisp-reg.h8 /* 0 - General */
87 #define BLT_CTL 0x0A00
88 #define BLT_ITS 0x0A04
89 #define BLT_STA1 0x0A08
90 #define BLT_AQ1_CTL 0x0A60
91 #define BLT_AQ1_IP 0x0A64
92 #define BLT_AQ1_LNA 0x0A68
93 #define BLT_AQ1_STA 0x0A6C
94 #define BLT_ITM0 0x0AD0
96 #define BLT_PLUGS1_OP2 0x0B04
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/linux/drivers/media/pci/smipcie/
H A Dsmipcie.h31 #define MSI_CONTROL_REG_BASE 0x0800
32 #define SYSTEM_CONTROL_REG_BASE 0x0880
33 #define PCIE_EP_DEBUG_REG_BASE 0x08C0
34 #define IR_CONTROL_REG_BASE 0x0900
35 #define I2C_A_CONTROL_REG_BASE 0x0940
36 #define I2C_B_CONTROL_REG_BASE 0x0980
37 #define ATV_PORTA_CONTROL_REG_BASE 0x09C0
38 #define DTV_PORTA_CONTROL_REG_BASE 0x0A00
39 #define AES_PORTA_CONTROL_REG_BASE 0x0A80
40 #define DMA_PORTA_CONTROL_REG_BASE 0x0AC0
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/linux/include/linux/mfd/mt6328/
H A Dregisters.h10 #define MT6328_STRUP_CON0 0x0000
11 #define MT6328_STRUP_CON2 0x0002
12 #define MT6328_STRUP_CON3 0x0004
13 #define MT6328_STRUP_CON4 0x0006
14 #define MT6328_STRUP_CON5 0x0008
15 #define MT6328_STRUP_CON6 0x000a
16 #define MT6328_STRUP_CON7 0x000c
17 #define MT6328_STRUP_CON8 0x000e
18 #define MT6328_STRUP_CON9 0x0010
19 #define MT6328_STRUP_CON10 0x0012
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/linux/arch/arm/mach-orion5x/
H A Ddns323-setup.c65 DNS323_REV_A1, /* 0 */
104 return 0; in dns323_pci_init()
113 * 0x00000000-0x00010000 : "MTD1"
114 * 0x00010000-0x00020000 : "MTD2"
115 * 0x00020000-0x001a0000 : "Linux Kernel"
116 * 0x001a0000-0x007d0000 : "File System"
117 * 0x007d0000-0x00800000 : "u-boot"
120 #define DNS323_NOR_BOOT_BASE 0xf4000000
126 .size = 0x00010000,
127 .offset = 0,
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/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_6_0_d.h26 #define ixMC_IO_DEBUG_ACMD_CLKSEL_D0 0x00CE
27 #define ixMC_IO_DEBUG_ACMD_CLKSEL_D1 0x00DE
28 #define ixMC_IO_DEBUG_ACMD_MISC_D0 0x00AE
29 #define ixMC_IO_DEBUG_ACMD_MISC_D1 0x00BE
30 #define ixMC_IO_DEBUG_ACMD_OFSCAL_D0 0x00EE
31 #define ixMC_IO_DEBUG_ACMD_OFSCAL_D1 0x00FE
32 #define ixMC_IO_DEBUG_ACMD_RXPHASE_D0 0x010E
33 #define ixMC_IO_DEBUG_ACMD_RXPHASE_D1 0x011E
34 #define ixMC_IO_DEBUG_ACMD_TXBST_PD_D0 0x018E
35 #define ixMC_IO_DEBUG_ACMD_TXBST_PD_D1 0x019E
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/linux/drivers/phy/xilinx/
H A Dphy-zynqmp.c34 #define L0_TX_ANA_TM_18 0x0048
35 #define L0_TX_ANA_TM_118 0x01d8
36 #define L0_TX_ANA_TM_118_FORCE_17_0 BIT(0)
39 #define L0_TXPMA_ST_3 0x0b0c
40 #define L0_DN_CALIB_CODE 0x3f
43 #define L0_TXPMD_TM_45 0x0cb4
44 #define L0_TXPMD_TM_48 0x0cc0
45 #define L0_TXPMD_TM_45_OVER_DP_MAIN BIT(0)
53 #define L0_TM_DIG_6 0x106c
54 #define L0_TM_DIS_DESCRAMBLE_DECODER 0x0f
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/linux/sound/soc/mediatek/mt8365/
H A Dmt8365-reg.h15 #define AUDIO_TOP_CON0 (0x0000)
16 #define AUDIO_TOP_CON1 (0x0004)
17 #define AUDIO_TOP_CON2 (0x0008)
18 #define AUDIO_TOP_CON3 (0x000c)
20 #define AFE_DAC_CON0 (0x0010)
21 #define AFE_DAC_CON1 (0x0014)
22 #define AFE_I2S_CON (0x0018)
23 #define AFE_CONN0 (0x0020)
24 #define AFE_CONN1 (0x0024)
25 #define AFE_CONN2 (0x0028)
[all …]
/linux/drivers/net/ethernet/sis/
H A Dsis190.c40 #define PHY_ID_ANY 0x1f
41 #define MII_REG_ANY 0x1f
55 #define RX_BUF_MASK 0xfff8
57 #define SIS190_REGS_SIZE 0x80
65 #define EhnMIIread 0x0000
66 #define EhnMIIwrite 0x0020
70 #define EhnMIIreq 0x0010
71 #define EhnMIInotDone 0x0010
84 TxControl = 0x00,
85 TxDescStartAddr = 0x04,
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_1_8_0_offset.h29 // base address: 0x60000
30 …DAGB0_RDCLI0 0x0000
31 …e regDAGB0_RDCLI0_BASE_IDX 0
32 …DAGB0_RDCLI1 0x0001
33 …e regDAGB0_RDCLI1_BASE_IDX 0
34 …DAGB0_RDCLI2 0x0002
35 …e regDAGB0_RDCLI2_BASE_IDX 0
36 …DAGB0_RDCLI3 0x0003
37 …e regDAGB0_RDCLI3_BASE_IDX 0
38 …DAGB0_RDCLI4 0x0004
[all …]
H A Dmmhub_1_7_offset.h29 // base address: 0x68000
30 …DAGB0_RDCLI0 0x0000
31 …e regDAGB0_RDCLI0_BASE_IDX 0
32 …DAGB0_RDCLI1 0x0001
33 …e regDAGB0_RDCLI1_BASE_IDX 0
34 …DAGB0_RDCLI2 0x0002
35 …e regDAGB0_RDCLI2_BASE_IDX 0
36 …DAGB0_RDCLI3 0x0003
37 …e regDAGB0_RDCLI3_BASE_IDX 0
38 …DAGB0_RDCLI4 0x0004
[all …]
/linux/drivers/gpu/drm/msm/registers/adreno/
H A Da3xx.xml10 <value name="LINEAR" value="0"/>
28 <value name="VFMT_32_FLOAT" value="0x0"/>
29 <value name="VFMT_32_32_FLOAT" value="0x1"/>
30 <value name="VFMT_32_32_32_FLOAT" value="0x2"/>
31 <value name="VFMT_32_32_32_32_FLOAT" value="0x3"/>
33 <value name="VFMT_16_FLOAT" value="0x4"/>
34 <value name="VFMT_16_16_FLOAT" value="0x5"/>
35 <value name="VFMT_16_16_16_FLOAT" value="0x6"/>
36 <value name="VFMT_16_16_16_16_FLOAT" value="0x7"/>
38 <value name="VFMT_32_FIXED" value="0x8"/>
[all …]
H A Da4xx.xml10 <value name="RB4_A8_UNORM" value="0x01"/>
11 <value name="RB4_R8_UNORM" value="0x02"/>
12 <value name="RB4_R8_SNORM" value="0x03"/>
13 <value name="RB4_R8_UINT" value="0x04"/>
14 <value name="RB4_R8_SINT" value="0x05"/>
16 <value name="RB4_R4G4B4A4_UNORM" value="0x08"/>
17 <value name="RB4_R5G5B5A1_UNORM" value="0x0a"/>
18 <value name="RB4_R5G6B5_UNORM" value="0x0e"/>
19 <value name="RB4_R8G8_UNORM" value="0x0f"/>
20 <value name="RB4_R8G8_SNORM" value="0x10"/>
[all …]
/linux/fs/hfsplus/
H A Dtables.c24 // High-byte indices ( == 0 iff no case mapping and no ignorables )
27 /* 0 */ 0x0100, 0x0200, 0x0000, 0x0300, 0x0400, 0x0500, 0x0000, 0x0000,
28 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
29 /* 1 */ 0x0600, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
30 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
31 /* 2 */ 0x0700, 0x0800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
32 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
33 /* 3 */ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
34 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
35 /* 4 */ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
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/linux/drivers/clk/qcom/
H A Dgcc-apq8084.c39 .l_reg = 0x0004,
40 .m_reg = 0x0008,
41 .n_reg = 0x000c,
42 .config_reg = 0x0014,
43 .mode_reg = 0x0000,
44 .status_reg = 0x001c,
57 .enable_reg = 0x1480,
58 .enable_mask = BIT(0),
70 .l_reg = 0x0044,
71 .m_reg = 0x0048,
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_offset.h27 // base address: 0x1300000
31 // base address: 0x1300000
35 // base address: 0x1300000
39 // base address: 0x1300000
43 // base address: 0x1300000
47 // base address: 0x1300020
51 // base address: 0x1300040
55 // base address: 0x1300060
59 // base address: 0x1300080
63 // base address: 0x13000a0
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/linux/sound/hda/codecs/realtek/
H A Dalc269.c52 static const hda_nid_t alc269_ignore[] = { 0x1d, 0 }; in alc269_parse_auto_config()
53 static const hda_nid_t alc269_ssids[] = { 0, 0x1b, 0x14, 0x21 }; in alc269_parse_auto_config()
54 static const hda_nid_t alc269va_ssids[] = { 0x15, 0x1b, 0x14, 0 }; in alc269_parse_auto_config()
104 int report = 0; in alc_headset_btn_callback()
131 case 0x10ec0215: in alc_disable_headset_jack_key()
132 case 0x10ec0225: in alc_disable_headset_jack_key()
133 case 0x10ec0285: in alc_disable_headset_jack_key()
134 case 0x10ec0287: in alc_disable_headset_jack_key()
135 case 0x10ec0295: in alc_disable_headset_jack_key()
136 case 0x10ec0289: in alc_disable_headset_jack_key()
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