Home
last modified time | relevance | path

Searched +full:0 +full:b11 (Results 1 – 25 of 56) sorted by relevance

123

/linux/net/dsa/
H A Dtag_ar9331.c23 * According to the AR8216 doc it should 0b10. On AR9331 it is 0b11 on RX path
24 * and should be set to 0b11 to make it work.
27 #define AR9331_HDR_PORT_NUM_MASK GENMASK(3, 0)
40 /* 0b10 for AR8216 and 0b11 for AR9331 */ in ar9331_tag_xmit()
43 phdr[0] = cpu_to_le16(hdr); in ar9331_tag_xmit()
61 netdev_warn_once(ndev, "%s:%i wrong header version 0x%2x\n", in ar9331_tag_rcv()
67 netdev_warn_once(ndev, "%s:%i packet should not be from cpu 0x%2x\n", in ar9331_tag_rcv()
77 skb->dev = dsa_conduit_find_user(ndev, 0, port); in ar9331_tag_rcv()
/linux/arch/powerpc/platforms/83xx/
H A Dkm83xx.c39 #define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */
59 ret = of_address_to_resource(np_par, 0, &res); in quirk_mpc8360e_qe_enet10()
73 * write 0b01 to UCC1 bits 18:19 in quirk_mpc8360e_qe_enet10()
74 * write 0b01 to UCC2 option 1 bits 4:5 in quirk_mpc8360e_qe_enet10()
75 * write 0b01 to UCC2 option 2 bits 16:17 in quirk_mpc8360e_qe_enet10()
77 clrsetbits_be32((base + 0xa8), 0x0c00f000, 0x04005000); in quirk_mpc8360e_qe_enet10()
83 * write 0b01 to UCC2 option 2 bits 16:17 in quirk_mpc8360e_qe_enet10()
84 * write 0b0101 to UCC1 bits 20:23 in quirk_mpc8360e_qe_enet10()
85 * write 0b0101 to UCC2 option 1 bits 24:27 in quirk_mpc8360e_qe_enet10()
87 clrsetbits_be32((base + 0xac), 0x0000cff0, 0x00004550); in quirk_mpc8360e_qe_enet10()
[all …]
/linux/include/linux/usb/
H A Dr8a66597.h13 #define R8A66597_PLATDATA_XTAL_12MHZ 0x01
14 #define R8A66597_PLATDATA_XTAL_24MHZ 0x02
15 #define R8A66597_PLATDATA_XTAL_48MHZ 0x03
44 #define SYSCFG0 0x00
45 #define SYSCFG1 0x02
46 #define SYSSTS0 0x04
47 #define SYSSTS1 0x06
48 #define DVSTCTR0 0x08
49 #define DVSTCTR1 0x0A
50 #define TESTMODE 0x0C
[all …]
H A Daudio-v2.h8 * in http://www.usb.org/developers/devclass_docs/Audio2.0_final.zip
16 /* v1.0 and v2.0 of this standard have many things in common. For the rest
22 * From the USB Audio spec v2.0:
27 * present then the bit pair must be set to 0b00.
29 * set to 0b01. If a Control is also Host programmable, the bit
30 * pair must be set to 0b11. The value 0b10 is not allowed.
36 return (bmControls >> ((control - 1) * 2)) & 0x1; in uac_v2v3_control_is_readable()
41 return (bmControls >> ((control - 1) * 2)) & 0x2; in uac_v2v3_control_is_writeable()
49 __le16 bcdADC; /* 0x0200 */
79 #define UAC_CLOCK_SOURCE_TYPE_EXT 0x0
[all …]
/linux/drivers/iio/adc/
H A Dad7606.h13 #define AD7616_CONFIGURATION_REGISTER 0x02
17 #define AD7616_RANGE_CH_A_ADDR_OFF 0x04
18 #define AD7616_RANGE_CH_B_ADDR_OFF 0x06
21 * 0, 1, 2, 3 in a register followed by 4, 5, 6, 7 in second register.
27 #define AD7616_RANGE_CH_MSK(ch) (0b11 << (((ch) & 0b11) * 2))
28 #define AD7616_RANGE_CH_MODE(ch, mode) ((mode) << ((((ch) & 0b11)) * 2))
30 #define AD7606_CONFIGURATION_REGISTER 0x02
31 #define AD7606_SINGLE_DOUT 0x00
34 * Range for AD7606B channels are stored in registers starting with address 0x3.
37 #define AD7606_RANGE_CH_MSK(ch) (GENMASK(3, 0) << (4 * ((ch) & 0x1)))
[all …]
H A Dad7091r8.c19 #define AD7091R8_REG_DATA_MSK GENMASK(9, 0)
33 return 0; in ad7091r8_set_mode()
68 AD7091R_CHANNEL(0, 12, NULL, 0),
69 AD7091R_CHANNEL(1, 12, NULL, 0),
73 AD7091R_CHANNEL(0, 12, NULL, 0),
74 AD7091R_CHANNEL(1, 12, NULL, 0),
75 AD7091R_CHANNEL(2, 12, NULL, 0),
76 AD7091R_CHANNEL(3, 12, NULL, 0),
80 AD7091R_CHANNEL(0, 12, ad7091r_events, ARRAY_SIZE(ad7091r_events)),
87 AD7091R_CHANNEL(0, 12, NULL, 0),
[all …]
/linux/Documentation/admin-guide/perf/
H A Dhisi-pcie-pmu.rst42 $# perf stat -e hisi_pcie0_core0/rx_mwr_latency,port=0xffff/
43 $# perf stat -e hisi_pcie0_core0/rx_mwr_cnt,port=0xffff/
52 b) By event type, such as "event=0xXXXX, event=0x1XXXX".
56 …$# perf stat -e "{hisi_pcie0_core0/rx_mwr_latency,port=0xffff/,hisi_pcie0_core0/rx_mwr_cnt,port=0x…
73 "bdf" filter will be in effect, because "bdf=0" meaning 0000:000:00.0.
83 bitmap should be set, port=0x1; if target Root Port is 0000:00:04.0 (x4
84 lanes), bit8 is set, port=0x100; if these two Root Ports are both
85 monitored, port=0x101.
89 $# perf stat -e hisi_pcie0_core0/rx_mwr_latency,port=0x1/ sleep 5
97 For example, "bdf=0x3900" means BDF of target Endpoint is 0000:39:00.0.
[all …]
H A Dhisi-pmu.rst13 two HHAs (0 - 1) and four DDRCs (0 - 3), respectively.
32 e.g. hisi_sccl3_l3c0/rd_hit_cpipe is READ_HIT_CPIPE event of L3C index #0 in
35 e.g. hisi_sccl1_hha0/rx_operations is RX_OPERATIONS event of HHA index #0 in
57 $# perf stat -a -e hisi_sccl3_l3c0/config=0x02/ sleep 5
59 For HiSilicon uncore PMU v2 whose identifier is 0x30, the topology is the same
65 $# perf stat -a -e hisi_sccl3_l3c0/config=0x02,tt_core=0x3/ sleep 5
67 This will only count the operations from core/thread 0 and 1 in this cluster.
79 $# perf stat -a -e hisi_sccl3_l3c0/config=0x02,tt_req=0x4/ sleep 5
97 $# perf stat -a -e hisi_sccl3_l3c0/config=0xb9,datasrc_cfg=0xE/,
98 hisi_sccl3_l3c0/config=0xb9,datasrc_cfg=0xF/ sleep 5
[all …]
/linux/drivers/usb/gadget/udc/
H A Dm66592-udc.h16 #define M66592_SYSCFG 0x00
17 #define M66592_XTAL 0xC000 /* b15-14: Crystal selection */
18 #define M66592_XTAL48 0x8000 /* 48MHz */
19 #define M66592_XTAL24 0x4000 /* 24MHz */
20 #define M66592_XTAL12 0x0000 /* 12MHz */
21 #define M66592_XCKE 0x2000 /* b13: External clock enable */
22 #define M66592_RCKE 0x1000 /* b12: Register clock enable */
23 #define M66592_PLLC 0x0800 /* b11: PLL control */
24 #define M66592_SCKE 0x0400 /* b10: USB clock enable */
25 #define M66592_ATCKM 0x0100 /* b8: Automatic clock supply */
[all …]
/linux/arch/loongarch/include/asm/
H A Dhw_breakpoint.h13 #define LOONGARCH_BREAKPOINT_EXECUTE (0 << 0)
16 #define LOONGARCH_BREAKPOINT_LOAD (1 << 0)
32 #define LOONGARCH_BREAKPOINT_LEN_1 0b11
33 #define LOONGARCH_BREAKPOINT_LEN_2 0b10
34 #define LOONGARCH_BREAKPOINT_LEN_4 0b01
35 #define LOONGARCH_BREAKPOINT_LEN_8 0b00
45 #define CSR_CFG_ADDR 0
59 if (T == 0) \
63 } while (0)
67 if (T == 0) \
[all …]
/linux/drivers/usb/host/
H A Docteon-hcd.h53 #define CVMX_USBCXBASE 0x00016F0010000000ull
56 ((bid) & 1) * 0x100000000000ull)
59 (((off) & 7) + ((bid) & 1) * 0x8000000000ull) * 32)
61 #define CVMX_USBCX_GAHBCFG(bid) CVMX_USBCXREG1(0x008, bid)
62 #define CVMX_USBCX_GHWCFG3(bid) CVMX_USBCXREG1(0x04c, bid)
63 #define CVMX_USBCX_GINTMSK(bid) CVMX_USBCXREG1(0x018, bid)
64 #define CVMX_USBCX_GINTSTS(bid) CVMX_USBCXREG1(0x014, bid)
65 #define CVMX_USBCX_GNPTXFSIZ(bid) CVMX_USBCXREG1(0x028, bid)
66 #define CVMX_USBCX_GNPTXSTS(bid) CVMX_USBCXREG1(0x02c, bid)
67 #define CVMX_USBCX_GOTGCTL(bid) CVMX_USBCXREG1(0x000, bid)
[all …]
/linux/lib/zstd/common/
H A Dentropy_common.c54 unsigned charnum = 0; in FSE_readNCount_body()
56 int previous0 = 0; in FSE_readNCount_body()
60 char buffer[8] = {0}; in FSE_readNCount_body()
71 …t(normalizedCounter, 0, (*maxSVPtr+1) * sizeof(normalizedCounter[0])); /* all symbols not presen… in FSE_readNCount_body()
73 nbBits = (bitStream & 0xF) + FSE_MIN_TABLELOG; /* extract tableLog */ in FSE_readNCount_body()
85 * 2-bit repeat code is 0b11 there is another in FSE_readNCount_body()
89 int repeats = ZSTD_countTrailingZeros32(~bitStream | 0x80000000) >> 1; in FSE_readNCount_body()
100 repeats = ZSTD_countTrailingZeros32(~bitStream | 0x80000000) >> 1; in FSE_readNCount_body()
106 /* Add the final repeat which isn't 0b11. */ in FSE_readNCount_body()
117 /* We don't need to set the normalized count to 0 in FSE_readNCount_body()
[all …]
/linux/drivers/net/mdio/
H A Dmdio-aspeed.c17 #define ASPEED_MDIO_CTRL 0x0
20 #define ASPEED_MDIO_CTRL_ST_C45 0
23 #define MDIO_C22_OP_WRITE 0b01
24 #define MDIO_C22_OP_READ 0b10
25 #define MDIO_C45_OP_ADDR 0b00
26 #define MDIO_C45_OP_WRITE 0b01
27 #define MDIO_C45_OP_PREAD 0b10
28 #define MDIO_C45_OP_READ 0b11
31 #define ASPEED_MDIO_CTRL_MIIWDATA GENMASK(15, 0)
33 #define ASPEED_MDIO_DATA 0x4
[all …]
/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_link.h43 #define SPEED_AUTO_NEG 0
46 #define I2C_DEV_ADDR_A0 0xa0
47 #define I2C_DEV_ADDR_A2 0xa2
50 #define SFP_EEPROM_VENDOR_NAME_ADDR 0x14
52 #define SFP_EEPROM_VENDOR_OUI_ADDR 0x25
54 #define SFP_EEPROM_PART_NO_ADDR 0x28
56 #define SFP_EEPROM_REVISION_ADDR 0x38
58 #define SFP_EEPROM_SERIAL_ADDR 0x44
60 #define SFP_EEPROM_DATE_ADDR 0x54 /* ASCII YYMMDD */
62 #define SFP_EEPROM_DIAG_TYPE_ADDR 0x5c
[all …]
/linux/drivers/net/wireless/ath/wil6210/
H A Dtxrx_edma.h19 #define WIL_DEFAULT_RX_STATUS_RING_ID 0
20 #define WIL_RX_DESC_RING_ID 0
21 #define WIL_RX_STATUS_IRQ_IDX 0
24 #define WIL_EDMA_AGG_WATERMARK (0xffff)
37 #define WIL_RX_EDMA_ERROR_L3_ERR (BIT(0) | BIT(1))
38 #define WIL_RX_EDMA_ERROR_L4_ERR (BIT(0) | BIT(1))
41 #define WIL_RX_EDMA_DLPF_LU_MISS_CID_TID_MASK 0x7
42 #define WIL_RX_EDMA_DLPF_LU_HIT_CID_TID_MASK 0xf
54 #define WIL_EDMA_DESC_TX_CFG_EOP_POS 0
76 * [dword 0] : Reserved
[all …]
H A Dtxrx.c36 return rx_align_2 ? 6 : 0; in wil_rx_snaplen()
113 size_t sz = vring->size * sizeof(vring->va[0]); in wil_vring_alloc()
118 BUILD_BUG_ON(sizeof(vring->va[0]) != 32); in wil_vring_alloc()
120 vring->swhead = 0; in wil_vring_alloc()
121 vring->swtail = 0; in wil_vring_alloc()
122 vring->ctx = kzalloc_objs(vring->ctx[0], vring->size); in wil_vring_alloc()
158 for (i = 0; i < vring->size; i++) { in wil_vring_alloc()
165 wil_dbg_misc(wil, "vring[%d] 0x%p:%pad 0x%p\n", vring->size, in wil_vring_alloc()
168 return 0; in wil_vring_alloc()
193 size_t sz = vring->size * sizeof(vring->va[0]); in wil_vring_free()
[all …]
/linux/drivers/mfd/
H A Docelot-spi.c30 #define REG_DEV_CPUORG_IF_CTRL 0x0000
31 #define REG_DEV_CPUORG_IF_CFGSTAT 0x0004
33 #define CFGSTAT_IF_NUM_VCORE (0 << 24)
38 #define VSC7512_DEVCPU_ORG_RES_START 0x71000000
39 #define VSC7512_DEVCPU_ORG_RES_SIZE 0x38
41 #define VSC7512_CHIP_REGS_RES_START 0x71070000
42 #define VSC7512_CHIP_REGS_RES_SIZE 0x14
64 * our CPU. These are two bits (0 and 1) but they're repeated such that in ocelot_spi_initialize()
68 * 0b00: little-endian, MSB first in ocelot_spi_initialize()
72 * 0b01: big-endian, MSB first in ocelot_spi_initialize()
[all …]
/linux/drivers/net/ethernet/aquantia/atlantic/macsec/
H A Dmacsec_struct.h21 /*! The match mask is per-nibble. 0 means don't care, i.e. every value
26 /*! 0: No compare, i.e. This entry is not used
36 /*! 0: Bypass the remaining modules if matched.
58 /*! The 8 bit value used to compare with extracted value for byte 0. */
82 /*! 0~63: byte location used extracted by packets comparator, which
84 * This byte location counted from MAC' DA address. i.e. set to 0
85 * will point to byte 0 of DA address.
88 /*! 0: don't care
92 /*! 0~63: byte location used extracted by packets comparator, which
94 * This byte location counted from MAC' DA address. i.e. set to 0
[all …]
/linux/arch/arm64/include/asm/
H A Dkvm_nested.h26 ((tcr & TCR_EL2_DS) ? TCR_DS : 0) | in translate_tcr_el2_to_tcr_el1()
27 ((tcr & TCR_EL2_TBI) ? TCR_TBI0 : 0) | in translate_tcr_el2_to_tcr_el1()
135 xn &= 0b10; in kvm_s2_trans_exec_el0()
138 case 0b00: in kvm_s2_trans_exec_el0()
139 case 0b01: in kvm_s2_trans_exec_el0()
151 xn &= 0b10; in kvm_s2_trans_exec_el1()
154 case 0b00: in kvm_s2_trans_exec_el1()
155 case 0b11: in kvm_s2_trans_exec_el1()
238 *elr = 0xbad9acc0debadbad; in kvm_auth_eretax()
253 u8 shift = 0; \
[all …]
/linux/include/linux/irqchip/
H A Darm-gic-v5.h19 #define GICV5_HWIRQ_ID GENMASK(23, 0)
21 #define GICV5_HWIRQ_INTID GENMASK_ULL(31, 0)
23 #define GICV5_HWIRQ_TYPE_PPI UL(0x1)
24 #define GICV5_HWIRQ_TYPE_LPI UL(0x2)
25 #define GICV5_HWIRQ_TYPE_SPI UL(0x3)
30 #define GICV5_ARCH_PPI_S_DB_PPI 0x0
31 #define GICV5_ARCH_PPI_RL_DB_PPI 0x1
32 #define GICV5_ARCH_PPI_NS_DB_PPI 0x2
33 #define GICV5_ARCH_PPI_SW_PPI 0x3
34 #define GICV5_ARCH_PPI_HACDBSIRQ 0xf
[all …]
/linux/drivers/net/usb/
H A Dcdc_eem.c52 urb = usb_alloc_urb(0, GFP_ATOMIC); in eem_linkcmd()
71 int status = 0; in eem_bind()
74 if (status < 0) in eem_bind()
82 return 0; in eem_bind()
94 u32 crc = 0; in eem_tx_fixup()
95 int padlen = 0; in eem_tx_fixup()
134 crc = crc32_le(~0, skb->data, skb->len); in eem_tx_fixup()
142 * b15: bmType (0 == data) in eem_tx_fixup()
149 put_unaligned_le16(0, skb_put(skb, 2)); in eem_tx_fixup()
170 u16 len = 0; in eem_rx_fixup()
[all …]
/linux/arch/powerpc/include/asm/
H A Dmpic.h14 #define MPIC_GREG_BASE 0x01000
16 #define MPIC_GREG_FEATURE_0 0x00000
17 #define MPIC_GREG_FEATURE_LAST_SRC_MASK 0x07ff0000
19 #define MPIC_GREG_FEATURE_LAST_CPU_MASK 0x00001f00
21 #define MPIC_GREG_FEATURE_VERSION_MASK 0xff
22 #define MPIC_GREG_FEATURE_1 0x00010
23 #define MPIC_GREG_GLOBAL_CONF_0 0x00020
24 #define MPIC_GREG_GCONF_RESET 0x80000000
27 * 0b00 = pass through (interrupts routed to IRQ0)
28 * 0b01 = Mixed mode
[all …]
/linux/arch/powerpc/include/asm/book3s/64/
H A Dradix.h26 #define RADIX_PMD_VAL_BITS (0x8000000000000000UL | RADIX_PTE_INDEX_SIZE)
27 #define RADIX_PUD_VAL_BITS (0x8000000000000000UL | RADIX_PMD_INDEX_SIZE)
28 #define RADIX_PGD_VAL_BITS (0x8000000000000000UL | RADIX_PUD_INDEX_SIZE)
31 #define RADIX_PMD_BAD_BITS 0x60000000000000e0UL
32 #define RADIX_PUD_BAD_BITS 0x60000000000000e0UL
33 #define RADIX_P4D_BAD_BITS 0x60000000000000e0UL
56 * +------------------+ Kernel virtual map (0xc008000000000000)
60 * 0b11......+------------------+ Kernel linear map (0xc....)
64 * 0b10......+------------------+
68 * 0b01......+------------------+
[all …]
/linux/arch/m68k/fpsp040/
H A Dsetox.S80 | 2.1 Set AdjFlag := 0 (indicates the branch 1.3 -> 2 was taken)
82 | 2.3 Calculate J = N mod 64; so J = 0,1,2,..., or 63.
154 | 6.1 If AdjFlag = 0, go to 6.3
158 | Notes: If AdjFlag = 0, we have X = Mlog2 + Jlog2/64 + R,
189 | 8.3 Calculate J = N mod 64, J = 0,1,...,63
197 | 9.1 If X < 0, go to 9.3
212 | Step 1. Set ans := 0
234 | 2.2 Calculate J = N mod 64; so J = 0,1,2,..., or 63.
317 | [ S*S*(B3 + S*(B5 + ... + S*B11)) ]
343 L2: .long 0x3FDC0000,0x82E30865,0x4361C4C6,0x00000000
[all …]
/linux/drivers/phy/rockchip/
H A Dphy-rockchip-usbdp.c29 #define UDPHY_PCS 0x4000
30 #define UDPHY_PMA 0x8000
38 #define DP_LANE_SEL_ALL GENMASK(7, 0)
41 #define CMN_LANE_MUX_AND_EN_OFFSET 0x0288 /* cmn_reg00A2 */
45 #define CMN_DP_LANE_EN_ALL GENMASK(3, 0)
47 #define CMN_DP_LINK_OFFSET 0x28c /* cmn_reg00A3 */
51 #define CMN_SSC_EN_OFFSET 0x2d0 /* cmn_reg00B4 */
53 #define CMN_LCPLL_SSC_EN BIT(0)
55 #define CMN_ANA_LCPLL_DONE_OFFSET 0x0350 /* cmn_reg00D4 */
59 #define CMN_ANA_ROPLL_DONE_OFFSET 0x0354 /* cmn_reg00D5 */
[all …]

123