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Searched +full:0 +full:b001 (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/meson/
H A Dmeson_dw_hdmi.h18 * Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset.
21 * 0=Release from reset.
23 * Bit 2 RW sw_reset_mem: KSV/REVOC mem. 1=Apply reset; 0=Release from reset.
26 * 0=Release from reset. Default 1.
27 * Bit 0 RW sw_reset_core: connects to IP's ~irstz. 1=Apply reset;
28 * 0=Release from reset. Default 1.
30 #define HDMITX_TOP_SW_RESET (0x000)
33 * Bit 31 RW free_clk_en: 0=Enable clock gating for power saving; 1= Disable
34 * Bit 12 RW i2s_ws_inv:1=Invert i2s_ws; 0=No invert. Default 0.
35 * Bit 11 RW i2s_clk_inv: 1=Invert i2s_clk; 0=No invert. Default 0.
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/linux/include/linux/irqchip/
H A Darm-gic-v5.h19 #define GICV5_HWIRQ_ID GENMASK(23, 0)
21 #define GICV5_HWIRQ_INTID GENMASK_ULL(31, 0)
23 #define GICV5_HWIRQ_TYPE_PPI UL(0x1)
24 #define GICV5_HWIRQ_TYPE_LPI UL(0x2)
25 #define GICV5_HWIRQ_TYPE_SPI UL(0x3)
30 #define GICV5_ARCH_PPI_S_DB_PPI 0x0
31 #define GICV5_ARCH_PPI_RL_DB_PPI 0x1
32 #define GICV5_ARCH_PPI_NS_DB_PPI 0x2
33 #define GICV5_ARCH_PPI_SW_PPI 0x3
34 #define GICV5_ARCH_PPI_HACDBSIRQ 0xf
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/linux/Documentation/arch/arm/pxa/
H A Dmfp.rst52 which can be routed to external through one or more MFPs (e.g. GPIO<0>
160 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
175 (0) or by PULL{UP,DOWN}_EN bits (1)
177 Bit 0 - 2: AF_SEL - alternate function selection, 8 possibilities, from 0-7
179 0b000 - fast 1mA
180 0b001 - fast 2mA
181 0b002 - fast 3mA
182 0b003 - fast 4mA
183 0b004 - slow 6mA
184 0b005 - fast 6mA
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/linux/drivers/iio/addac/
H A Dad74413r.c31 #define AD74413R_CRC_POLYNOMIAL 0x7
96 #define AD74413R_REG_NOP 0x00
98 #define AD74413R_REG_CH_FUNC_SETUP_X(x) (0x01 + (x))
99 #define AD74413R_CH_FUNC_SETUP_MASK GENMASK(3, 0)
101 #define AD74413R_REG_ADC_CONFIG_X(x) (0x05 + (x))
105 #define AD74413R_ADC_RANGE_10V 0b000
106 #define AD74413R_ADC_RANGE_2P5V_EXT_POW 0b001
107 #define AD74413R_ADC_RANGE_2P5V_INT_POW 0b010
108 #define AD74413R_ADC_RANGE_5V_BI_DIR 0b011
109 #define AD74413R_ADC_REJECTION_50_60 0b00
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/linux/arch/powerpc/platforms/powernv/
H A Docxl.c8 #define PNV_OCXL_TL_P9_RECV_CAP 0x000000000000000Full
15 #define AFU_INDEX_MASK 0x3F000000
17 #define ACTAG_MASK 0xFFF
87 return 0; in find_dvsec_from_pos()
92 int vsec = 0; in find_dvsec_afu_ctrl()
102 return 0; in find_dvsec_afu_ctrl()
120 return 0; in get_max_afu_index()
135 return 0; in get_actag_count()
194 link->fn_desired_actags[PCI_FUNC(dev->devfn)] = 0; in pnv_ocxl_fixup_actag()
195 for (i = 0; i <= afu_idx; i++) { in pnv_ocxl_fixup_actag()
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/linux/drivers/net/ethernet/synopsys/
H A Ddwc-xlgmac.h30 #define XLGMAC_DRV_VERSION "1.0.0"
47 #define XLGMAC_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1))
53 * 3'b000: 64 bytes, 3'b001: 128 bytes
64 #define XLGMAC_DMA_INTERRUPT_MASK 0x31c7
71 #define XLGMAC_MAX_DMA_RIWT 0xff
72 #define XLGMAC_MIN_DMA_RIWT 0x01
86 #define XLGMAC_RSS_LOOKUP_TABLE_TYPE 0
658 #define XLGMAC_PR(x...) do { } while (0)
/linux/drivers/clk/aspeed/
H A Dclk-ast2600.c24 #define ASPEED_G6_SILICON_REV 0x014
27 #define ASPEED_G6_RESET_CTRL 0x040
28 #define ASPEED_G6_RESET_CTRL2 0x050
30 #define ASPEED_G6_CLK_STOP_CTRL 0x080
31 #define ASPEED_G6_CLK_STOP_CTRL2 0x090
33 #define ASPEED_G6_MISC_CTRL 0x0C0
36 #define ASPEED_G6_CLK_SELECTION1 0x300
37 #define ASPEED_G6_CLK_SELECTION2 0x304
38 #define ASPEED_G6_CLK_SELECTION4 0x310
39 #define ASPEED_G6_CLK_SELECTION5 0x314
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/linux/drivers/gpu/drm/tests/
H A Ddrm_format_helper_test.c21 #define TEST_USE_DEFAULT_PITCH 0
129 .clip = DRM_RECT_INIT(0, 0, 1, 1),
130 .xrgb8888 = { 0x01FF0000 },
133 .expected = { 0x4C },
137 .expected = { 0xE0 },
141 .expected = { 0xF800 },
142 .expected_swab = { 0x00F8 },
146 .expected = { 0x7C00 },
150 .expected = { 0xFC00 },
154 .expected = { 0xF801 },
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/linux/drivers/pinctrl/bcm/
H A Dpinctrl-bcm281xx.c24 #define BCM281XX_PIN_REG_F_SEL_MASK 0x0700
28 #define BCM281XX_STD_PIN_REG_DRV_STR_MASK 0x0007
29 #define BCM281XX_STD_PIN_REG_DRV_STR_SHIFT 0
30 #define BCM281XX_STD_PIN_REG_INPUT_DIS_MASK 0x0008
32 #define BCM281XX_STD_PIN_REG_SLEW_MASK 0x0010
34 #define BCM281XX_STD_PIN_REG_PULL_UP_MASK 0x0020
36 #define BCM281XX_STD_PIN_REG_PULL_DN_MASK 0x0040
38 #define BCM281XX_STD_PIN_REG_HYST_MASK 0x0080
42 #define BCM281XX_I2C_PIN_REG_INPUT_DIS_MASK 0x0004
44 #define BCM281XX_I2C_PIN_REG_SLEW_MASK 0x0008
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/linux/arch/arm64/include/asm/
H A Dsysreg.h30 #define Op0_mask 0x3
32 #define Op1_mask 0x7
34 #define CRn_mask 0xf
36 #define CRm_mask 0xf
38 #define Op2_mask 0x7
68 #define __INSTR_BSWAP(x) ((((x) << 24) & 0xff000000) | \
69 (((x) << 8) & 0x00ff0000) | \
70 (((x) >> 8) & 0x0000ff00) | \
71 (((x) >> 24) & 0x000000ff))
84 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
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/linux/drivers/usb/host/
H A Docteon-hcd.h53 #define CVMX_USBCXBASE 0x00016F0010000000ull
56 ((bid) & 1) * 0x100000000000ull)
59 (((off) & 7) + ((bid) & 1) * 0x8000000000ull) * 32)
61 #define CVMX_USBCX_GAHBCFG(bid) CVMX_USBCXREG1(0x008, bid)
62 #define CVMX_USBCX_GHWCFG3(bid) CVMX_USBCXREG1(0x04c, bid)
63 #define CVMX_USBCX_GINTMSK(bid) CVMX_USBCXREG1(0x018, bid)
64 #define CVMX_USBCX_GINTSTS(bid) CVMX_USBCXREG1(0x014, bid)
65 #define CVMX_USBCX_GNPTXFSIZ(bid) CVMX_USBCXREG1(0x028, bid)
66 #define CVMX_USBCX_GNPTXSTS(bid) CVMX_USBCXREG1(0x02c, bid)
67 #define CVMX_USBCX_GOTGCTL(bid) CVMX_USBCXREG1(0x000, bid)
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