| /linux/arch/arm64/kvm/hyp/ |
| H A D | exception.c | 69 * This performs the exception entry at a given EL (@target_mode), stashing PC
71 * The EL passed to this function *must* be a non-secure, privileged mode with
79 * For the SPSR_ELx layout for AArch64, see ARM DDI 0487E.a page C5-429.
80 * For the SPSR_ELx layout for AArch32, see ARM DDI 0487E.a page C5-426.
134 // See ARM DDI 0487E.a, page D5-2579. in enter_exception64()
138 // See ARM DDI 0487E.a, page D5-2578. in enter_exception64()
144 // See ARM DDI 0487E.a, page D2-2452. in enter_exception64()
147 // See ARM DDI 0487E.a, page D1-2306. in enter_exception64()
150 // See ARM DDI 0487E.a, page D13-3258 in enter_exception64()
155 // See ARM DDI 0487E.a, pages D1-2293 to D1-2294. in enter_exception64()
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| /linux/Documentation/trace/coresight/ |
| H A D | coresight-cpu-debug.rst | 11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
12 (ARM DDI 0487A.k) Chapter 'Part H: External debug', the CPU can integrate
43 - The driver supports a CPU running in either AArch64 or AArch32 mode. The
44 registers naming convention is a bit different between them, AArch64 uses
45 'ED' for register prefix (ARM DDI 0487A.k, chapter H9.1) and AArch32 uses
46 'DBG' as prefix (ARM DDI 0487A.k, chapter G5.1). The driver is unified to
49 - ARMv8-a (ARM DDI 0487A.k) and ARMv7-a (ARM DDI 0406C.b) have different
52 If PCSROffset=0b0000, on ARMv8-a the feature of EDPCSR is not implemented;
53 but ARMv7-a defines "PCSR samples are offset by a value that depends on the
54 instruction set state". For ARMv7-a, the driver checks furthermore if CPU
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| /linux/tools/testing/selftests/arm64/signal/ |
| H A D | sve_helpers.c | 37 * terminating, bail out here when we find a higher VL than in sve_fill_vls()
39 * See the ARM ARM, DDI 0487K.a, B1.4.2: I_QQRNR and I_NWYBP. in sve_fill_vls()
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| /linux/Documentation/arch/arm64/ |
| H A D | hugetlbpage.rst | 18 These are regular hugepages where a pmd or a pud page table entry points to a
26 The architecture provides a contiguous bit in the translation table entries
27 (D4.5.3, ARM DDI 0487C.a) that hints to the MMU to indicate that it is one of a
28 contiguous set of entries that can be cached in a single TLB entry.
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| /linux/Documentation/translations/zh_CN/arch/arm64/ |
| H A D | hugetlbpage.rst | 29 架构中转换页表条目(D4.5.3, ARM DDI 0487C.a)中提供一个连续
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| H A D | booting.txt | 4 original document maintainer directly. However, if you have a problem
7 or if there is a problem with the translation.
175 ARM DDI 0487A
233 ARM DEN 0022A：用于 ARM 上的电源状态协调接口系统软件）中描述的
236 *译者注: ARM DEN 0022A 已更新到 ARM DEN 0022C。
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| /linux/Documentation/translations/zh_TW/arch/arm64/ |
| H A D | hugetlbpage.rst | 32 架構中轉換頁表條目(D4.5.3, ARM DDI 0487C.a)中提供一個連續
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| H A D | booting.txt | 6 original document maintainer directly. However, if you have a problem
9 or if there is a problem with the translation.
179 ARM DDI 0487A
237 ARM DEN 0022A：用於 ARM 上的電源狀態協調接口系統軟件）中描述的
240 *譯者注: ARM DEN 0022A 已更新到 ARM DEN 0022C。
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| /linux/Documentation/devicetree/bindings/arm/ |
| H A D | arm,coresight-cpu-debug.yaml | 17 reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The
53 A phandle to the cpu this debug component is bound to.
59 A phandle to the debug power domain if the debug logic has its own
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| /linux/arch/arm64/include/asm/ |
| H A D | daifflags.h | 34 /* Don't really care for a dsb here, we don't intend to enable IRQs */ in local_daif_mask()
98 * From the ARM ARM DDI 0487D.a, section D1.7.1 in local_daif_restore()
109 * interrupts with a lower priority than PMR is signaled in local_daif_restore()
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| H A D | kvm_emulate.h | 163 * vcpu_get_reg and vcpu_set_reg should always be passed a register number
164 * coming from a read of ESR_EL2. Otherwise, it may give the wrong result on
240 * We are in a hypervisor context if the vcpu mode is EL2 or in is_hyp_ctxt()
245 * rest of the KVM code, and will result in a misbehaving guest. in is_hyp_ctxt()
274 * In ARM DDI 0487E.a see:
484 * Only a permission fault on a S1PTW should be in kvm_is_write_fault()
485 * considered as a write. Otherwise, page tables baked in kvm_is_write_fault()
486 * in a read-only memslot will result in an exception in kvm_is_write_fault()
490 * guest is using any of HW AF/DB: a translation fault in kvm_is_write_fault()
492 * first), then a permission fault to allow the flags in kvm_is_write_fault()
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| H A D | tlbflush.h | 28 * on whether a particular TLBI operation takes an argument or
49 /* This macro creates a properly formatted VA operand for the TLBI */
90 * a non-hinted invalidation. Any provided level outside the hint range
120 * This macro creates a properly formatted VA operand for the TLB RANGE. The
133 * 0487J.a section C5.5.60 "TLBI VAE1IS, TLBI VAE1ISNXS, TLB Invalidate by VA,
165 * significant for a maximum of MAX_TLBI_RANGE_PAGES pages. If
239 * kernel mappings rather than a particular user address space.
244 * Invalidate a single user mapping for address 'addr' in the
246 * operation only invalidates a single, last-level page-table
257 * Invalidate a single kernel mapping for address 'addr' on all
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| H A D | sysreg.h | 22 * C5.2, version:ARM DDI 0487A.f)
84 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
85 * barriers and CLREX, and PSTATE access", ARM DDI 0487 C.a, system instructions
941 * KASAN always uses a whole byte for its tags. With CONFIG_KASAN_HW_TAGS it
1169 * The "Z" constraint normally means a zero immediate, but when combined with
1195 * to force XZR generation if (v) is a constant 0 value but LLVM does not
1196 * yet understand that modifier/constraint combo so a conditional is required
1197 * to nudge the compiler into using XZR as a source for a 0 constant value.
1209 * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the
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| /linux/arch/arm64/mm/ |
| H A D | contpte.c | 35 * PTEs that map consecutive pages of the same large folio within a in contpte_align_addr_ptep()
36 * single VMA and a single page table. in contpte_align_addr_ptep()
102 * - When unfolding a contiguous block into N smaller non-contiguous ptes. in contpte_convert()
135 * contiguous TLB entry, which is a micro-optimisation opportunity, in contpte_convert()
139 * This means a few things, but notably other PEs will still "see" any in contpte_convert()
140 * stale cached TLB entries. This could lead to a "contiguous bit in contpte_convert()
158 * are present, and a write is made to this address, do we fault or in contpte_convert()
161 * The relevant Arm ARM DDI 0487L.a requirements are RNGLXZ and RJQQTC, in contpte_convert()
163 * a TLB conflict abort is raised (which we expressly forbid), or will in contpte_convert()
167 * That is to say, will either raise a TLB conflict, or produce one of in contpte_convert()
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| /linux/arch/arm64/kernel/ |
| H A D | mte.c | 127 * Note: If in future KASAN acquires a runtime switching in mte_enable_kernel_async()
145 * Note: If in future KASAN acquires a runtime switching in mte_enable_kernel_asymm()
189 * (per ARM DDI 0487F.c table D13-1). in mte_check_tfsr_el1()
312 * lead to the wrong memory type being used for a brief window during in mte_cpu_setup()
315 * CnP is not a boot feature so MTE gets enabled before CnP, but let's in mte_cpu_setup()
388 * Userspace could see a mix of both sync and async anyway due in set_mte_ctrl()
643 * A read is sufficient for mte, the caller should have probed in mte_probe_user_range()
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| H A D | ptrace.c | 99 * @name: the name of a register
101 * regs_query_register_offset() returns the offset of a register in struct
169 * Handle hitting a HW-breakpoint.
626 * Ensure target->thread.uw.fpsimd_state is up to date, so that a in __fpr_set()
916 * a VL of 0 to allow exiting streaming mode, otherwise a VL in sve_set_common()
922 * configure a SVE VL. in sve_set_common()
937 /* If the system supports SVE we require a VL. */ in sve_set_common()
1005 * If setting a different VL from the requested VL and there is in sve_set_common()
1187 * If setting a different VL from the requested VL and there is in za_set()
1703 * ZA is a single register but it's variably sized and
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| H A D | cpufeature.c | 7 * A note for the weary kernel hacker: the code here is confusing and hard to
8 * follow! That's partly because it's solving a nasty problem, but also because
9 * there's a little bit of over-abstraction that tends to obscure what's going
10 * on behind a maze of helper functions and macros.
14 * user-visible instructions are available only on a subset of the available
17 * CPU when bringing them up. If there is a mismatch, then we update the
20 * "sanitised" value of a feature register.
25 * things like alternative patching and static keys. While a feature mismatch
26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch
27 * may prevent a CPU from being onlined at all.
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| /linux/drivers/perf/ |
| H A D | arm_brbe.c | 23 * purpose but BRBCR_ELx.TS needs to have a valid value from all
32 * entries each. An individual branch record in a given bank could
268 * Arm ARM (DDI 0487K.a) D.18.4 rule PPBZP requires explicit sync in select_brbe_bank()
291 * fail silently. PERF_SAMPLE_BRANCH_HV is a special case that is selectively
325 * either individually or as a group i.e ORing multiple filters
410 * a given exception level, then addresses which falls in branch_type_to_brbcr()
500 * Discard existing records to avoid a discontinuity, e.g. records in brbe_enable()
542 * ensures ordering and in the interrupt handler this is a NOP as in brbe_disable()
721 /* We can only have a half record if permissions have not been expanded */ in filter_branch_privilege()
726 * If record is within a single exception level, just need to either in filter_branch_privilege()
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| H A D | arm_spe_pmu.c | 102 /* Convert a free-running index from perf into an SPE buffer offset */
394 * The PMSIDR_EL1.Interval field (stored in spe_pmu->min_period) is a in arm_spe_event_sanitise_period()
395 * recommendation for the minimum interval, not a hardware limitation. in arm_spe_event_sanitise_period()
397 * According to the Arm ARM (DDI 0487 L.a), section D24.7.12 PMSIRR_EL1, in arm_spe_event_sanitise_period()
399 * states: "Software must set this to a nonzero value". Use 1 as the in arm_spe_event_sanitise_period()
504 * so that the worst case is half a buffer of records, as in arm_spe_pmu_next_snapshot_off()
505 * opposed to a single record. in arm_spe_pmu_next_snapshot_off()
535 * a record when generating a buffer management event. in __arm_spe_pmu_next_off()
576 * If there's a wakeup before we wrap, arrange to be woken up by in __arm_spe_pmu_next_off()
624 /* Start a new aux session */ in arm_spe_perf_aux_output_begin()
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| /linux/tools/perf/util/ |
| H A D | cs-etm.c | 55 * happen in cases like between a fork and an exec.
61 * everything in a buffer comes from the same process regardless of
121 * Same as traceid_list, but traceid_list may be a reference to another
122 * queue's which has a matching sink ID.
141 * A struct auxtrace_heap_item only has a queue_nr and a timestamp to
243 /* Disallow re-mapping a different traceID to metadata pair. */ in cs_etm__insert_trace_id_node()
445 * Get a metadata index for a specific cpu from an array.
462 * Get a metadata for a specific cpu from an array.
477 * but a CPU / Trace ID association changing during a session is an error.
535 * When a timestamp packet is encountered the backend code in cs_etm__etmq_set_traceid_queue_timestamp()
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| /linux/drivers/clocksource/ |
| H A D | arm_arch_timer.c | 38 * The minimum amount of time a generic counter is guaranteed to not roll over
75 * Makes an educated guess at a valid counter width based on the Generic Timer
78 * 2) a roll-over time of not less than 40 years
80 * See 'ARM DDI 0487G.a D11.1.2 ("The system counter")' for more details.
135 * if we don't have the cp15 accessors we won't have a problem.
447 /* Iterate over the ACPI OEM info array, looking for a match */ in arch_timer_check_acpi_oem_erratum()
497 * late in the game (with a per-CPU erratum, for example), so in arch_timer_enable_workaround()
559 #define arch_timer_check_ool_workaround(t,a) do { } while(0) argument
719 /* ECV is likely to require a large divider. Use the EVNTIS flag. */ in arch_timer_evtstrm_enable()
861 * probed has a clock-frequency property, this overrides the HW register.
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| /linux/arch/arm64/kvm/ |
| H A D | arm.c | 198 * kvm_arch_init_vm - initializes a VM data structure
322 * - both Address and Generic auth are implemented for a given in kvm_has_full_ptr_auth()
324 * - only a single algorithm is implemented. in kvm_has_full_ptr_auth()
645 * Ensure a VMID is allocated for the MMU before programming VTTBR_EL2, in kvm_arch_vcpu_load()
649 * time of rollover, so KVM might need to grab a new VMID for the MMU if in kvm_arch_vcpu_load()
656 * vcpu. If detecting that a vcpu from the same VM has in kvm_arch_vcpu_load()
844 * A significant bit can be either 0 or 1, and will only appear in in kvm_init_mpidr_data()
851 * Don't let userspace fool us. If we need more than a single page in kvm_init_mpidr_data()
879 * performed each time we get a new thread dealing with this vcpu.
899 * Map the VGIC hardware resources before running a vcpu the in kvm_arch_vcpu_run_pid_change()
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| /linux/drivers/scsi/lpfc/ |
| H A D | lpfc_init.c | 17 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
20 * more details, a copy of which can be found in the file COPYING *
68 /* Used when mapping IRQ vectors in a driver centric manner */
256 /* dump mem may return a zero when finished or we got a in lpfc_config_port_prep()
307 * into a human readable string and store it in OptionROMVersion.
328 /* Decode the Option rom version word to a readable string */ in lpfc_dump_wakeup_param_cmpl()
356 * If the name is empty or there exists a soft name in lpfc_update_vport_wwn()
730 * structure for use as a delayed link up mechanism with the
751 * structure for use as a delayed link up mechanism with the
1185 * this timer fires, a HBA timeout event shall be posted to the lpfc driver
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