1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2011 NetApp, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/param.h>
30 #include <sys/pcpu.h>
31 #include <sys/systm.h>
32 #include <sys/sysctl.h>
33
34 #include <machine/clock.h>
35 #include <machine/cpufunc.h>
36 #include <machine/md_var.h>
37 #include <machine/segments.h>
38 #include <machine/specialreg.h>
39 #include <machine/vmm.h>
40 #include <x86/bhyve.h>
41
42 #include <dev/vmm/vmm_ktr.h>
43 #include <dev/vmm/vmm_vm.h>
44
45 #include "vmm_host.h"
46 #include "vmm_util.h"
47 #include "x86.h"
48
49 SYSCTL_DECL(_hw_vmm);
50 static SYSCTL_NODE(_hw_vmm, OID_AUTO, topology, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
51 NULL);
52
53 #define CPUID_VM_SIGNATURE 0x40000000
54 #define CPUID_VM_HIGH CPUID_BHYVE_FEATURES
55
56 static const char bhyve_id[12] = "bhyve bhyve ";
57
58 static uint64_t bhyve_xcpuids;
59 SYSCTL_ULONG(_hw_vmm, OID_AUTO, bhyve_xcpuids, CTLFLAG_RW, &bhyve_xcpuids, 0,
60 "Number of times an unknown cpuid leaf was accessed");
61
62 static int cpuid_leaf_b = 1;
63 SYSCTL_INT(_hw_vmm_topology, OID_AUTO, cpuid_leaf_b, CTLFLAG_RDTUN,
64 &cpuid_leaf_b, 0, NULL);
65
66 /*
67 * Compute ceil(log2(x)). Returns -1 if x is zero.
68 */
69 static __inline int
log2(u_int x)70 log2(u_int x)
71 {
72
73 return (x == 0 ? -1 : order_base_2(x));
74 }
75
76 int
x86_emulate_cpuid(struct vcpu * vcpu,uint64_t * rax,uint64_t * rbx,uint64_t * rcx,uint64_t * rdx)77 x86_emulate_cpuid(struct vcpu *vcpu, uint64_t *rax, uint64_t *rbx,
78 uint64_t *rcx, uint64_t *rdx)
79 {
80 struct vm *vm = vcpu_vm(vcpu);
81 int vcpu_id = vcpu_vcpuid(vcpu);
82 const struct xsave_limits *limits;
83 uint64_t cr4;
84 int error, enable_invpcid, enable_rdpid, enable_rdtscp, level,
85 width, x2apic_id;
86 unsigned int func, regs[4], logical_cpus, param;
87 enum x2apic_state x2apic_state;
88 uint16_t cores, maxcpus, sockets, threads;
89
90 /*
91 * The function of CPUID is controlled through the provided value of
92 * %eax (and secondarily %ecx, for certain leaf data).
93 */
94 func = (uint32_t)*rax;
95 param = (uint32_t)*rcx;
96
97 VCPU_CTR2(vm, vcpu_id, "cpuid %#x,%#x", func, param);
98
99 /*
100 * Requests for invalid CPUID levels should map to the highest
101 * available level instead.
102 */
103 if (cpu_exthigh != 0 && func >= 0x80000000) {
104 if (func > cpu_exthigh)
105 func = cpu_exthigh;
106 } else if (func >= CPUID_VM_SIGNATURE) {
107 if (func > CPUID_VM_HIGH)
108 func = CPUID_VM_HIGH;
109 } else if (func > cpu_high) {
110 func = cpu_high;
111 }
112
113 /*
114 * In general the approach used for CPU topology is to
115 * advertise a flat topology where all CPUs are packages with
116 * no multi-core or SMT.
117 */
118 switch (func) {
119 /*
120 * Pass these through to the guest
121 */
122 case CPUID_0000_0000:
123 case CPUID_0000_0002:
124 case CPUID_0000_0003:
125 case CPUID_8000_0000:
126 case CPUID_8000_0002:
127 case CPUID_8000_0003:
128 case CPUID_8000_0004:
129 case CPUID_8000_0006:
130 cpuid_count(func, param, regs);
131 break;
132 case CPUID_8000_0008:
133 cpuid_count(func, param, regs);
134 if (vmm_is_svm()) {
135 /*
136 * As on Intel (0000_0007:0, EDX), mask out
137 * unsupported or unsafe AMD extended features
138 * (8000_0008 EBX).
139 */
140 regs[1] &= (AMDFEID_CLZERO | AMDFEID_IRPERF |
141 AMDFEID_XSAVEERPTR);
142
143 vm_get_topology(vm, &sockets, &cores, &threads,
144 &maxcpus);
145 /*
146 * Here, width is ApicIdCoreIdSize, present on
147 * at least Family 15h and newer. It
148 * represents the "number of bits in the
149 * initial apicid that indicate thread id
150 * within a package."
151 *
152 * Our topo_probe_amd() uses it for
153 * pkg_id_shift and other OSes may rely on it.
154 */
155 width = MIN(0xF, log2(threads * cores));
156 logical_cpus = MIN(0xFF, threads * cores - 1);
157 regs[2] = (width << AMDID_COREID_SIZE_SHIFT) | logical_cpus;
158 }
159 break;
160
161 case CPUID_8000_0001:
162 cpuid_count(func, param, regs);
163
164 /*
165 * Hide SVM from guest.
166 */
167 regs[2] &= ~AMDID2_SVM;
168
169 /*
170 * Don't advertise extended performance counter MSRs
171 * to the guest.
172 */
173 regs[2] &= ~AMDID2_PCXC;
174 regs[2] &= ~AMDID2_PNXC;
175 regs[2] &= ~AMDID2_PTSCEL2I;
176
177 /*
178 * Don't advertise Instruction Based Sampling feature.
179 */
180 regs[2] &= ~AMDID2_IBS;
181
182 /* NodeID MSR not available */
183 regs[2] &= ~AMDID2_NODE_ID;
184
185 /* Don't advertise the OS visible workaround feature */
186 regs[2] &= ~AMDID2_OSVW;
187
188 /* Hide mwaitx/monitorx capability from the guest */
189 regs[2] &= ~AMDID2_MWAITX;
190
191 /* Advertise RDTSCP if it is enabled. */
192 error = vm_get_capability(vcpu,
193 VM_CAP_RDTSCP, &enable_rdtscp);
194 if (error == 0 && enable_rdtscp)
195 regs[3] |= AMDID_RDTSCP;
196 else
197 regs[3] &= ~AMDID_RDTSCP;
198 break;
199
200 case CPUID_8000_0007:
201 /*
202 * AMD uses this leaf to advertise the processor's
203 * power monitoring and RAS capabilities. These
204 * features are hardware-specific and exposing
205 * them to a guest doesn't make a lot of sense.
206 *
207 * Intel uses this leaf only to advertise the
208 * "Invariant TSC" feature with all other bits
209 * being reserved (set to zero).
210 */
211 regs[0] = 0;
212 regs[1] = 0;
213 regs[2] = 0;
214 regs[3] = 0;
215
216 /*
217 * "Invariant TSC" can be advertised to the guest if:
218 * - host TSC frequency is invariant
219 * - host TSCs are synchronized across physical cpus
220 *
221 * XXX This still falls short because the vcpu
222 * can observe the TSC moving backwards as it
223 * migrates across physical cpus. But at least
224 * it should discourage the guest from using the
225 * TSC to keep track of time.
226 */
227 if (tsc_is_invariant && smp_tsc)
228 regs[3] |= AMDPM_TSC_INVARIANT;
229 break;
230
231 case CPUID_8000_001D:
232 /* AMD Cache topology, like 0000_0004 for Intel. */
233 if (!vmm_is_svm())
234 goto default_leaf;
235
236 /*
237 * Similar to Intel, generate a fictitious cache
238 * topology for the guest with L3 shared by the
239 * package, and L1 and L2 local to a core.
240 */
241 vm_get_topology(vm, &sockets, &cores, &threads,
242 &maxcpus);
243 switch (param) {
244 case 0:
245 logical_cpus = threads;
246 level = 1;
247 func = 1; /* data cache */
248 break;
249 case 1:
250 logical_cpus = threads;
251 level = 2;
252 func = 3; /* unified cache */
253 break;
254 case 2:
255 logical_cpus = threads * cores;
256 level = 3;
257 func = 3; /* unified cache */
258 break;
259 default:
260 logical_cpus = sockets * threads * cores;
261 level = 0;
262 func = 0;
263 break;
264 }
265
266 logical_cpus = MIN(0xfff, logical_cpus - 1);
267 regs[0] = (logical_cpus << 14) | (1 << 8) |
268 (level << 5) | func;
269 regs[1] = (func > 0) ? (CACHE_LINE_SIZE - 1) : 0;
270
271 /*
272 * ecx: Number of cache ways for non-fully
273 * associative cache, minus 1. Reported value
274 * of zero means there is one way.
275 */
276 regs[2] = 0;
277
278 regs[3] = 0;
279 break;
280
281 case CPUID_8000_001E:
282 /*
283 * AMD Family 16h+ and Hygon Family 18h additional
284 * identifiers.
285 */
286 if (!vmm_is_svm() || CPUID_TO_FAMILY(cpu_id) < 0x16)
287 goto default_leaf;
288
289 vm_get_topology(vm, &sockets, &cores, &threads,
290 &maxcpus);
291 regs[0] = vcpu_id;
292 threads = MIN(0xFF, threads - 1);
293 regs[1] = (threads << 8) |
294 (vcpu_id >> log2(threads + 1));
295 /*
296 * XXX Bhyve topology cannot yet represent >1 node per
297 * processor.
298 */
299 regs[2] = 0;
300 regs[3] = 0;
301 break;
302
303 case CPUID_0000_0001:
304 do_cpuid(1, regs);
305
306 error = vm_get_x2apic_state(vcpu, &x2apic_state);
307 if (error) {
308 panic("x86_emulate_cpuid: error %d "
309 "fetching x2apic state", error);
310 }
311
312 /*
313 * Override the APIC ID only in ebx
314 */
315 regs[1] &= ~(CPUID_LOCAL_APIC_ID);
316 regs[1] |= (vcpu_id << CPUID_0000_0001_APICID_SHIFT);
317
318 /*
319 * Don't expose VMX, SpeedStep, TME or SMX capability.
320 * Advertise x2APIC capability and Hypervisor guest.
321 */
322 regs[2] &= ~(CPUID2_VMX | CPUID2_EST | CPUID2_TM2);
323 regs[2] &= ~(CPUID2_SMX);
324
325 regs[2] |= CPUID2_HV;
326
327 if (x2apic_state != X2APIC_DISABLED)
328 regs[2] |= CPUID2_X2APIC;
329 else
330 regs[2] &= ~CPUID2_X2APIC;
331
332 /*
333 * Only advertise CPUID2_XSAVE in the guest if
334 * the host is using XSAVE.
335 */
336 if (!(regs[2] & CPUID2_OSXSAVE))
337 regs[2] &= ~CPUID2_XSAVE;
338
339 /*
340 * If CPUID2_XSAVE is being advertised and the
341 * guest has set CR4_XSAVE, set
342 * CPUID2_OSXSAVE.
343 */
344 regs[2] &= ~CPUID2_OSXSAVE;
345 if (regs[2] & CPUID2_XSAVE) {
346 error = vm_get_register(vcpu,
347 VM_REG_GUEST_CR4, &cr4);
348 if (error)
349 panic("x86_emulate_cpuid: error %d "
350 "fetching %%cr4", error);
351 if (cr4 & CR4_XSAVE)
352 regs[2] |= CPUID2_OSXSAVE;
353 }
354
355 /*
356 * Hide monitor/mwait until we know how to deal with
357 * these instructions.
358 */
359 regs[2] &= ~CPUID2_MON;
360
361 /*
362 * Hide the performance and debug features.
363 */
364 regs[2] &= ~CPUID2_PDCM;
365
366 /*
367 * No TSC deadline support in the APIC yet
368 */
369 regs[2] &= ~CPUID2_TSCDLT;
370
371 /*
372 * Hide thermal monitoring
373 */
374 regs[3] &= ~(CPUID_ACPI | CPUID_TM);
375
376 /*
377 * Hide the debug store capability.
378 */
379 regs[3] &= ~CPUID_DS;
380
381 /*
382 * Advertise the Machine Check and MTRR capability.
383 *
384 * Some guest OSes (e.g. Windows) will not boot if
385 * these features are absent.
386 */
387 regs[3] |= (CPUID_MCA | CPUID_MCE | CPUID_MTRR);
388
389 vm_get_topology(vm, &sockets, &cores, &threads,
390 &maxcpus);
391 logical_cpus = threads * cores;
392 regs[1] &= ~CPUID_HTT_CORES;
393 regs[1] |= (logical_cpus & 0xff) << 16;
394 regs[3] |= CPUID_HTT;
395 break;
396
397 case CPUID_0000_0004:
398 cpuid_count(func, param, regs);
399
400 if (regs[0] || regs[1] || regs[2] || regs[3]) {
401 vm_get_topology(vm, &sockets, &cores, &threads,
402 &maxcpus);
403 regs[0] &= 0x3ff;
404 regs[0] |= (cores - 1) << 26;
405 /*
406 * Cache topology:
407 * - L1 and L2 are shared only by the logical
408 * processors in a single core.
409 * - L3 and above are shared by all logical
410 * processors in the package.
411 */
412 logical_cpus = threads;
413 level = (regs[0] >> 5) & 0x7;
414 if (level >= 3)
415 logical_cpus *= cores;
416 regs[0] |= (logical_cpus - 1) << 14;
417 }
418 break;
419
420 case CPUID_0000_0007:
421 regs[0] = 0;
422 regs[1] = 0;
423 regs[2] = 0;
424 regs[3] = 0;
425
426 /* leaf 0 */
427 if (param == 0) {
428 cpuid_count(func, param, regs);
429
430 /* Only leaf 0 is supported */
431 regs[0] = 0;
432
433 /*
434 * Expose known-safe features.
435 */
436 regs[1] &= CPUID_STDEXT_FSGSBASE |
437 CPUID_STDEXT_BMI1 | CPUID_STDEXT_HLE |
438 CPUID_STDEXT_AVX2 | CPUID_STDEXT_SMEP |
439 CPUID_STDEXT_BMI2 |
440 CPUID_STDEXT_ERMS | CPUID_STDEXT_RTM |
441 CPUID_STDEXT_AVX512F |
442 CPUID_STDEXT_AVX512DQ |
443 CPUID_STDEXT_RDSEED |
444 CPUID_STDEXT_SMAP |
445 CPUID_STDEXT_AVX512PF |
446 CPUID_STDEXT_AVX512ER |
447 CPUID_STDEXT_AVX512CD | CPUID_STDEXT_SHA |
448 CPUID_STDEXT_AVX512BW |
449 CPUID_STDEXT_AVX512VL |
450 CPUID_STDEXT_AVX512IFMA;
451 regs[2] &= CPUID_STDEXT2_VAES |
452 CPUID_STDEXT2_VPCLMULQDQ |
453 CPUID_STDEXT2_AVX512VBMI |
454 CPUID_STDEXT2_AVX512VBMI2 |
455 CPUID_STDEXT2_AVX512VNNI |
456 CPUID_STDEXT2_AVX512BITALG |
457 CPUID_STDEXT2_AVX512VPOPCNTDQ;
458 regs[3] &= CPUID_STDEXT3_MD_CLEAR |
459 CPUID_STDEXT3_AVX5124VNNIW |
460 CPUID_STDEXT3_AVX5124FMAPS |
461 CPUID_STDEXT3_AVX512VP2INTERSECT;
462
463 /* Advertise RDPID if it is enabled. */
464 error = vm_get_capability(vcpu, VM_CAP_RDPID,
465 &enable_rdpid);
466 if (error == 0 && enable_rdpid)
467 regs[2] |= CPUID_STDEXT2_RDPID;
468
469 /* Advertise INVPCID if it is enabled. */
470 error = vm_get_capability(vcpu,
471 VM_CAP_ENABLE_INVPCID, &enable_invpcid);
472 if (error == 0 && enable_invpcid)
473 regs[1] |= CPUID_STDEXT_INVPCID;
474 }
475 break;
476
477 case CPUID_0000_0006:
478 regs[0] = CPUTPM1_ARAT;
479 regs[1] = 0;
480 regs[2] = 0;
481 regs[3] = 0;
482 break;
483
484 case CPUID_0000_000A:
485 /*
486 * Handle the access, but report 0 for
487 * all options
488 */
489 regs[0] = 0;
490 regs[1] = 0;
491 regs[2] = 0;
492 regs[3] = 0;
493 break;
494
495 case CPUID_0000_000B:
496 /*
497 * Intel processor topology enumeration
498 */
499 if (vmm_is_intel()) {
500 vm_get_topology(vm, &sockets, &cores, &threads,
501 &maxcpus);
502 if (param == 0) {
503 logical_cpus = threads;
504 width = log2(logical_cpus);
505 level = CPUID_TYPE_SMT;
506 x2apic_id = vcpu_id;
507 }
508
509 if (param == 1) {
510 logical_cpus = threads * cores;
511 width = log2(logical_cpus);
512 level = CPUID_TYPE_CORE;
513 x2apic_id = vcpu_id;
514 }
515
516 if (!cpuid_leaf_b || param >= 2) {
517 width = 0;
518 logical_cpus = 0;
519 level = 0;
520 x2apic_id = 0;
521 }
522
523 regs[0] = width & 0x1f;
524 regs[1] = logical_cpus & 0xffff;
525 regs[2] = (level << 8) | (param & 0xff);
526 regs[3] = x2apic_id;
527 } else {
528 regs[0] = 0;
529 regs[1] = 0;
530 regs[2] = 0;
531 regs[3] = 0;
532 }
533 break;
534
535 case CPUID_0000_000D:
536 limits = vmm_get_xsave_limits();
537 if (!limits->xsave_enabled) {
538 regs[0] = 0;
539 regs[1] = 0;
540 regs[2] = 0;
541 regs[3] = 0;
542 break;
543 }
544
545 cpuid_count(func, param, regs);
546 switch (param) {
547 case 0:
548 /*
549 * Only permit the guest to use bits
550 * that are active in the host in
551 * %xcr0. Also, claim that the
552 * maximum save area size is
553 * equivalent to the host's current
554 * save area size. Since this runs
555 * "inside" of vmrun(), it runs with
556 * the guest's xcr0, so the current
557 * save area size is correct as-is.
558 */
559 regs[0] &= limits->xcr0_allowed;
560 regs[2] = limits->xsave_max_size;
561 regs[3] &= (limits->xcr0_allowed >> 32);
562 break;
563 case 1:
564 /* Only permit XSAVEOPT. */
565 regs[0] &= CPUID_EXTSTATE_XSAVEOPT;
566 regs[1] = 0;
567 regs[2] = 0;
568 regs[3] = 0;
569 break;
570 default:
571 /*
572 * If the leaf is for a permitted feature,
573 * pass through as-is, otherwise return
574 * all zeroes.
575 */
576 if (!(limits->xcr0_allowed & (1ul << param))) {
577 regs[0] = 0;
578 regs[1] = 0;
579 regs[2] = 0;
580 regs[3] = 0;
581 }
582 break;
583 }
584 break;
585
586 case CPUID_0000_000F:
587 case CPUID_0000_0010:
588 /*
589 * Do not report any Resource Director Technology
590 * capabilities. Exposing control of cache or memory
591 * controller resource partitioning to the guest is not
592 * at all sensible.
593 *
594 * This is already hidden at a high level by masking of
595 * leaf 0x7. Even still, a guest may look here for
596 * detailed capability information.
597 */
598 regs[0] = 0;
599 regs[1] = 0;
600 regs[2] = 0;
601 regs[3] = 0;
602 break;
603
604 case CPUID_0000_0015:
605 /*
606 * Don't report CPU TSC/Crystal ratio and clock
607 * values since guests may use these to derive the
608 * local APIC frequency..
609 */
610 regs[0] = 0;
611 regs[1] = 0;
612 regs[2] = 0;
613 regs[3] = 0;
614 break;
615
616 case CPUID_VM_SIGNATURE:
617 regs[0] = CPUID_VM_HIGH;
618 bcopy(bhyve_id, ®s[1], 4);
619 bcopy(bhyve_id + 4, ®s[2], 4);
620 bcopy(bhyve_id + 8, ®s[3], 4);
621 break;
622
623 case CPUID_BHYVE_FEATURES:
624 regs[0] = CPUID_BHYVE_FEAT_EXT_DEST_ID;
625 regs[1] = 0;
626 regs[2] = 0;
627 regs[3] = 0;
628 break;
629
630 default:
631 default_leaf:
632 /*
633 * The leaf value has already been clamped so
634 * simply pass this through, keeping count of
635 * how many unhandled leaf values have been seen.
636 */
637 atomic_add_long(&bhyve_xcpuids, 1);
638 cpuid_count(func, param, regs);
639 break;
640 }
641
642 /*
643 * CPUID clears the upper 32-bits of the long-mode registers.
644 */
645 *rax = regs[0];
646 *rbx = regs[1];
647 *rcx = regs[2];
648 *rdx = regs[3];
649
650 return (1);
651 }
652
653 bool
vm_cpuid_capability(struct vcpu * vcpu,enum vm_cpuid_capability cap)654 vm_cpuid_capability(struct vcpu *vcpu, enum vm_cpuid_capability cap)
655 {
656 bool rv;
657
658 KASSERT(cap > 0 && cap < VCC_LAST, ("%s: invalid vm_cpu_capability %d",
659 __func__, cap));
660
661 /*
662 * Simply passthrough the capabilities of the host cpu for now.
663 */
664 rv = false;
665 switch (cap) {
666 case VCC_NO_EXECUTE:
667 if (amd_feature & AMDID_NX)
668 rv = true;
669 break;
670 case VCC_FFXSR:
671 if (amd_feature & AMDID_FFXSR)
672 rv = true;
673 break;
674 case VCC_TCE:
675 if (amd_feature2 & AMDID2_TCE)
676 rv = true;
677 break;
678 default:
679 panic("%s: unknown vm_cpu_capability %d", __func__, cap);
680 }
681 return (rv);
682 }
683
684 int
vm_rdmtrr(struct vm_mtrr * mtrr,u_int num,uint64_t * val)685 vm_rdmtrr(struct vm_mtrr *mtrr, u_int num, uint64_t *val)
686 {
687 switch (num) {
688 case MSR_MTRRcap:
689 *val = MTRR_CAP_WC | MTRR_CAP_FIXED | VMM_MTRR_VAR_MAX;
690 break;
691 case MSR_MTRRdefType:
692 *val = mtrr->def_type;
693 break;
694 case MSR_MTRR4kBase ... MSR_MTRR4kBase + 7:
695 *val = mtrr->fixed4k[num - MSR_MTRR4kBase];
696 break;
697 case MSR_MTRR16kBase ... MSR_MTRR16kBase + 1:
698 *val = mtrr->fixed16k[num - MSR_MTRR16kBase];
699 break;
700 case MSR_MTRR64kBase:
701 *val = mtrr->fixed64k;
702 break;
703 case MSR_MTRRVarBase ... MSR_MTRRVarBase + (VMM_MTRR_VAR_MAX * 2) - 1: {
704 u_int offset = num - MSR_MTRRVarBase;
705 if (offset % 2 == 0) {
706 *val = mtrr->var[offset / 2].base;
707 } else {
708 *val = mtrr->var[offset / 2].mask;
709 }
710 break;
711 }
712 default:
713 return (-1);
714 }
715
716 return (0);
717 }
718
719 int
vm_wrmtrr(struct vm_mtrr * mtrr,u_int num,uint64_t val)720 vm_wrmtrr(struct vm_mtrr *mtrr, u_int num, uint64_t val)
721 {
722 switch (num) {
723 case MSR_MTRRcap:
724 /* MTRRCAP is read only */
725 return (-1);
726 case MSR_MTRRdefType:
727 if (val & ~VMM_MTRR_DEF_MASK) {
728 /* generate #GP on writes to reserved fields */
729 return (-1);
730 }
731 mtrr->def_type = val;
732 break;
733 case MSR_MTRR4kBase ... MSR_MTRR4kBase + 7:
734 mtrr->fixed4k[num - MSR_MTRR4kBase] = val;
735 break;
736 case MSR_MTRR16kBase ... MSR_MTRR16kBase + 1:
737 mtrr->fixed16k[num - MSR_MTRR16kBase] = val;
738 break;
739 case MSR_MTRR64kBase:
740 mtrr->fixed64k = val;
741 break;
742 case MSR_MTRRVarBase ... MSR_MTRRVarBase + (VMM_MTRR_VAR_MAX * 2) - 1: {
743 u_int offset = num - MSR_MTRRVarBase;
744 if (offset % 2 == 0) {
745 if (val & ~VMM_MTRR_PHYSBASE_MASK) {
746 /* generate #GP on writes to reserved fields */
747 return (-1);
748 }
749 mtrr->var[offset / 2].base = val;
750 } else {
751 if (val & ~VMM_MTRR_PHYSMASK_MASK) {
752 /* generate #GP on writes to reserved fields */
753 return (-1);
754 }
755 mtrr->var[offset / 2].mask = val;
756 }
757 break;
758 }
759 default:
760 return (-1);
761 }
762
763 return (0);
764 }
765