1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // es8323.c -- es8323 ALSA SoC audio driver
4 //
5 // Copyright 2024 Rockchip Electronics Co. Ltd.
6 // Copyright 2024 Everest Semiconductor Co.,Ltd.
7 // Copyright 2024 Loongson Technology Co.,Ltd.
8 //
9 // Author: Mark Brown <broonie@kernel.org>
10 // Jianqun Xu <jay.xu@rock-chips.com>
11 // Nickey Yang <nickey.yang@rock-chips.com>
12 // Further cleanup and restructuring by:
13 // Binbin Zhou <zhoubinbin@loongson.cn>
14
15 #include <linux/bitfield.h>
16 #include <linux/module.h>
17 #include <linux/acpi.h>
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/i2c.h>
21 #include <linux/regmap.h>
22 #include <sound/pcm.h>
23 #include <sound/pcm_params.h>
24 #include <sound/soc.h>
25 #include <sound/soc-dapm.h>
26 #include <sound/tlv.h>
27
28 #include "es8323.h"
29
30 struct es8323_priv {
31 unsigned int sysclk;
32 struct clk *mclk;
33 struct regmap *regmap;
34 struct snd_pcm_hw_constraint_list *sysclk_constraints;
35 };
36
37 /* es8323 register cache */
38 static const struct reg_default es8323_reg_defaults[] = {
39 { ES8323_CONTROL1, 0x06 },
40 { ES8323_CONTROL2, 0x1c },
41 { ES8323_CHIPPOWER, 0xc3 },
42 { ES8323_ADCPOWER, 0xfc },
43 { ES8323_DACPOWER, 0xc0 },
44 { ES8323_CHIPLOPOW1, 0x00 },
45 { ES8323_CHIPLOPOW2, 0x00 },
46 { ES8323_ANAVOLMANAG, 0x7c },
47 { ES8323_MASTERMODE, 0x80 },
48 { ES8323_ADCCONTROL1, 0x00 },
49 { ES8323_ADCCONTROL2, 0x00 },
50 { ES8323_ADCCONTROL3, 0x06 },
51 { ES8323_ADCCONTROL4, 0x00 },
52 { ES8323_ADCCONTROL5, 0x06 },
53 { ES8323_ADCCONTROL6, 0x30 },
54 { ES8323_ADCCONTROL7, 0x30 },
55 { ES8323_LADC_VOL, 0xc0 },
56 { ES8323_RADC_VOL, 0xc0 },
57 { ES8323_ADCCONTROL10, 0x38 },
58 { ES8323_ADCCONTROL11, 0xb0 },
59 { ES8323_ADCCONTROL12, 0x32 },
60 { ES8323_ADCCONTROL13, 0x06 },
61 { ES8323_ADCCONTROL14, 0x00 },
62 { ES8323_DACCONTROL1, 0x00 },
63 { ES8323_DACCONTROL2, 0x06 },
64 { ES8323_DACCONTROL3, 0x30 },
65 { ES8323_LDAC_VOL, 0xc0 },
66 { ES8323_RDAC_VOL, 0xc0 },
67 { ES8323_DACCONTROL6, 0x08 },
68 { ES8323_DACCONTROL7, 0x06 },
69 { ES8323_DACCONTROL8, 0x1f },
70 { ES8323_DACCONTROL9, 0xf7 },
71 { ES8323_DACCONTROL10, 0xfd },
72 { ES8323_DACCONTROL11, 0xff },
73 { ES8323_DACCONTROL12, 0x1f },
74 { ES8323_DACCONTROL13, 0xf7 },
75 { ES8323_DACCONTROL14, 0xfd },
76 { ES8323_DACCONTROL15, 0xff },
77 { ES8323_DACCONTROL16, 0x00 },
78 { ES8323_DACCONTROL17, 0x38 },
79 { ES8323_DACCONTROL18, 0x38 },
80 { ES8323_DACCONTROL19, 0x38 },
81 { ES8323_DACCONTROL20, 0x38 },
82 { ES8323_DACCONTROL21, 0x38 },
83 { ES8323_DACCONTROL22, 0x38 },
84 { ES8323_DACCONTROL23, 0x00 },
85 { ES8323_LOUT1_VOL, 0x00 },
86 { ES8323_ROUT1_VOL, 0x00 },
87 };
88
89 static const char *const es8323_stereo_3d_texts[] = { "No 3D ", "Level 1", "Level 2", "Level 3",
90 "Level 4", "Level 5", "Level 6", "Level 7" };
91 static SOC_ENUM_SINGLE_DECL(es8323_stereo_3d_enum, ES8323_DACCONTROL7, 2, es8323_stereo_3d_texts);
92
93 static const char *const es8323_alc_func_texts[] = { "Off", "Right", "Left", "Stereo" };
94 static SOC_ENUM_SINGLE_DECL(es8323_alc_function_enum,
95 ES8323_ADCCONTROL10, 6, es8323_alc_func_texts);
96
97 static const char *const es8323_ng_type_texts[] = { "Constant PGA Gain", "Mute ADC Output" };
98 static SOC_ENUM_SINGLE_DECL(es8323_alc_ng_type_enum, ES8323_ADCCONTROL14, 1, es8323_ng_type_texts);
99
100 static const char *const es8323_deemph_texts[] = { "None", "32Khz", "44.1Khz", "48Khz" };
101 static SOC_ENUM_SINGLE_DECL(es8323_playback_deemphasis_enum,
102 ES8323_DACCONTROL6, 6, es8323_deemph_texts);
103
104 static const char *const es8323_adcpol_texts[] = { "Normal", "L Invert",
105 "R Invert", "L + R Invert" };
106 static SOC_ENUM_SINGLE_DECL(es8323_capture_polarity_enum,
107 ES8323_ADCCONTROL6, 6, es8323_adcpol_texts);
108
109 static const DECLARE_TLV_DB_SCALE(es8323_adc_tlv, -9600, 50, 1);
110 static const DECLARE_TLV_DB_SCALE(es8323_dac_tlv, -9600, 50, 1);
111 static const DECLARE_TLV_DB_SCALE(es8323_out_tlv, -4500, 150, 0);
112 static const DECLARE_TLV_DB_SCALE(es8323_bypass_tlv, 0, 300, 0);
113 static const DECLARE_TLV_DB_SCALE(es8323_bypass_tlv2, -15, 300, 0);
114
115 static const struct snd_kcontrol_new es8323_snd_controls[] = {
116 SOC_ENUM("3D Mode", es8323_stereo_3d_enum),
117 SOC_ENUM("ALC Capture Function", es8323_alc_function_enum),
118 SOC_ENUM("ALC Capture NG Type", es8323_alc_ng_type_enum),
119 SOC_ENUM("Playback De-emphasis", es8323_playback_deemphasis_enum),
120 SOC_ENUM("Capture Polarity", es8323_capture_polarity_enum),
121
122 SOC_SINGLE("ALC Capture ZC Switch", ES8323_ADCCONTROL13,
123 ES8323_ADCCONTROL13_ALCZC_OFF, 1, 0),
124 SOC_SINGLE("ALC Capture Decay Time", ES8323_ADCCONTROL12,
125 ES8323_ADCCONTROL12_ALCDCY_OFF, 15, 0),
126 SOC_SINGLE("ALC Capture Attack Time", ES8323_ADCCONTROL12,
127 ES8323_ADCCONTROL12_ALCATK_OFF, 15, 0),
128 SOC_SINGLE("ALC Capture NG Threshold", ES8323_ADCCONTROL14,
129 ES8323_ADCCONTROL14_NGTH_OFF, 31, 0),
130 SOC_SINGLE("ALC Capture NG Switch", ES8323_ADCCONTROL14,
131 ES8323_ADCCONTROL14_NGAT_OFF, 1, 0),
132 SOC_SINGLE("ZC Timeout Switch", ES8323_ADCCONTROL13,
133 ES8323_ADCCONTROL13_TIMEOUT_OFF, 1, 0),
134 SOC_SINGLE("Capture Mute Switch", ES8323_ADCCONTROL7,
135 ES8323_ADCCONTROL7_ADCMUTE_OFF, 1, 0),
136
137 SOC_SINGLE_TLV("Left Channel Capture Volume", ES8323_ADCCONTROL1,
138 ES8323_ADCCONTROL1_MICAMPL_OFF, 8, 0, es8323_bypass_tlv),
139 SOC_SINGLE_TLV("Right Channel Capture Volume", ES8323_ADCCONTROL1,
140 ES8323_ADCCONTROL1_MICAMPR_OFF, 8, 0, es8323_bypass_tlv),
141 SOC_SINGLE_TLV("Left Mixer Left Bypass Volume", ES8323_DACCONTROL17,
142 ES8323_DACCONTROL17_LI2LOVOL_OFF, 7, 1, es8323_bypass_tlv2),
143 SOC_SINGLE_TLV("Right Mixer Right Bypass Volume", ES8323_DACCONTROL20,
144 ES8323_DACCONTROL20_RI2ROVOL_OFF, 7, 1, es8323_bypass_tlv2),
145
146 SOC_DOUBLE_R_TLV("PCM Volume",
147 ES8323_LDAC_VOL, ES8323_RDAC_VOL,
148 0, 192, 1, es8323_dac_tlv),
149 SOC_DOUBLE_R_TLV("Capture Digital Volume",
150 ES8323_LADC_VOL, ES8323_RADC_VOL,
151 0, 192, 1, es8323_adc_tlv),
152 SOC_DOUBLE_R_TLV("Output 1 Playback Volume",
153 ES8323_LOUT1_VOL, ES8323_ROUT1_VOL,
154 0, 33, 0, es8323_out_tlv),
155 SOC_DOUBLE_R_TLV("Output 2 Playback Volume",
156 ES8323_LOUT2_VOL, ES8323_ROUT2_VOL,
157 0, 33, 0, es8323_out_tlv),
158 };
159
160 /* Left DAC Route */
161 static const char *const es8323_pga_sell[] = { "Line 1L", "Line 2L", "NC", "DifferentialL" };
162 static SOC_ENUM_SINGLE_DECL(es8323_left_dac_enum, ES8323_ADCCONTROL2, 6, es8323_pga_sell);
163 static const struct snd_kcontrol_new es8323_left_dac_mux_controls =
164 SOC_DAPM_ENUM("Left DAC Route", es8323_left_dac_enum);
165
166 /* Right DAC Route */
167 static const char *const es8323_pga_selr[] = { "Line 1R", "Line 2R", "NC", "DifferentialR" };
168 static SOC_ENUM_SINGLE_DECL(es8323_right_dac_enum, ES8323_ADCCONTROL2, 4, es8323_pga_selr);
169 static const struct snd_kcontrol_new es8323_right_dac_mux_controls =
170 SOC_DAPM_ENUM("Right DAC Route", es8323_right_dac_enum);
171
172 /* Left Line Mux */
173 static const char *const es8323_lin_sell[] = { "Line 1L", "Line 2L", "NC", "MicL" };
174 static SOC_ENUM_SINGLE_DECL(es8323_llin_enum, ES8323_DACCONTROL16, 3, es8323_lin_sell);
175 static const struct snd_kcontrol_new es8323_left_line_controls =
176 SOC_DAPM_ENUM("LLIN Mux", es8323_llin_enum);
177
178 /* Right Line Mux */
179 static const char *const es8323_lin_selr[] = { "Line 1R", "Line 2R", "NC", "MicR" };
180 static SOC_ENUM_SINGLE_DECL(es8323_rlin_enum, ES8323_DACCONTROL16, 0, es8323_lin_selr);
181 static const struct snd_kcontrol_new es8323_right_line_controls =
182 SOC_DAPM_ENUM("RLIN Mux", es8323_rlin_enum);
183
184 /* Differential Mux */
185 static const char *const es8323_diffmux_sel[] = { "Line 1", "Line 2" };
186 static SOC_ENUM_SINGLE_DECL(es8323_diffmux_enum, ES8323_ADCCONTROL3, 7, es8323_diffmux_sel);
187 static const struct snd_kcontrol_new es8323_diffmux_controls =
188 SOC_DAPM_ENUM("Route2", es8323_diffmux_enum);
189
190 /* Mono ADC Mux */
191 static const char *const es8323_mono_adc_mux[] = { "Stereo", "Mono (Left)", "Mono (Right)" };
192 static SOC_ENUM_SINGLE_DECL(es8323_mono_adc_mux_enum, ES8323_ADCCONTROL3, 3, es8323_mono_adc_mux);
193 static const struct snd_kcontrol_new es8323_mono_adc_mux_controls =
194 SOC_DAPM_ENUM("Mono Mux", es8323_mono_adc_mux_enum);
195
196 /* Left Mixer */
197 static const struct snd_kcontrol_new es8323_left_mixer_controls[] = {
198 SOC_DAPM_SINGLE("Left Playback Switch", ES8323_DACCONTROL17, 7, 1, 0),
199 SOC_DAPM_SINGLE("Left Bypass Switch", ES8323_DACCONTROL17, 6, 1, 0),
200 };
201
202 /* Right Mixer */
203 static const struct snd_kcontrol_new es8323_right_mixer_controls[] = {
204 SOC_DAPM_SINGLE("Right Playback Switch", ES8323_DACCONTROL20, 7, 1, 0),
205 SOC_DAPM_SINGLE("Right Bypass Switch", ES8323_DACCONTROL20, 6, 1, 0),
206 };
207
208 static const struct snd_soc_dapm_widget es8323_dapm_widgets[] = {
209 SND_SOC_DAPM_INPUT("LINPUT1"),
210 SND_SOC_DAPM_INPUT("LINPUT2"),
211 SND_SOC_DAPM_INPUT("RINPUT1"),
212 SND_SOC_DAPM_INPUT("RINPUT2"),
213
214 SND_SOC_DAPM_SUPPLY("Mic Bias", ES8323_ADCPOWER,
215 ES8323_ADCPOWER_PDNMICB_OFF, 1, NULL, 0),
216 SND_SOC_DAPM_SUPPLY("Mic Bias Gen", ES8323_ADCPOWER,
217 ES8323_ADCPOWER_PDNADCBIS_OFF, 1, NULL, 0),
218
219 SND_SOC_DAPM_SUPPLY("DAC STM", ES8323_CHIPPOWER,
220 ES8323_CHIPPOWER_DACSTM_RESET, 1, NULL, 0),
221 SND_SOC_DAPM_SUPPLY("ADC STM", ES8323_CHIPPOWER,
222 ES8323_CHIPPOWER_ADCSTM_RESET, 1, NULL, 0),
223 SND_SOC_DAPM_SUPPLY("DAC DIG", ES8323_CHIPPOWER,
224 ES8323_CHIPPOWER_DACDIG_OFF, 1, NULL, 0),
225 SND_SOC_DAPM_SUPPLY("ADC DIG", ES8323_CHIPPOWER,
226 ES8323_CHIPPOWER_ADCDIG_OFF, 1, NULL, 0),
227 SND_SOC_DAPM_SUPPLY("DAC DLL", ES8323_CHIPPOWER,
228 ES8323_CHIPPOWER_DACDLL_OFF, 1, NULL, 0),
229 SND_SOC_DAPM_SUPPLY("ADC DLL", ES8323_CHIPPOWER,
230 ES8323_CHIPPOWER_ADCDLL_OFF, 1, NULL, 0),
231 SND_SOC_DAPM_SUPPLY("ADC Vref", ES8323_CHIPPOWER,
232 ES8323_CHIPPOWER_ADCVREF_OFF, 1, NULL, 0),
233 SND_SOC_DAPM_SUPPLY("DAC Vref", ES8323_CHIPPOWER,
234 ES8323_CHIPPOWER_DACVREF_OFF, 1, NULL, 0),
235
236 /* Muxes */
237 SND_SOC_DAPM_MUX("Left PGA Mux", ES8323_ADCPOWER,
238 ES8323_ADCPOWER_PDNAINL_OFF, 1, &es8323_left_dac_mux_controls),
239 SND_SOC_DAPM_MUX("Right PGA Mux", ES8323_ADCPOWER,
240 ES8323_ADCPOWER_PDNAINR_OFF, 1, &es8323_right_dac_mux_controls),
241
242 SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0, &es8323_diffmux_controls),
243
244 SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0, &es8323_mono_adc_mux_controls),
245 SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0, &es8323_mono_adc_mux_controls),
246
247 SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0, &es8323_left_line_controls),
248 SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0, &es8323_right_line_controls),
249
250 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
251 ES8323_ADCPOWER, ES8323_ADCPOWER_PDNADCR_OFF, 1),
252 SND_SOC_DAPM_ADC("Left ADC", "Left Capture",
253 ES8323_ADCPOWER, ES8323_ADCPOWER_PDNADCL_OFF, 1),
254 SND_SOC_DAPM_DAC("Right DAC", "Right Playback",
255 ES8323_DACPOWER, ES8323_DACPOWER_PDNDACR_OFF, 1),
256 SND_SOC_DAPM_DAC("Left DAC", "Left Playback",
257 ES8323_DACPOWER, ES8323_DACPOWER_PDNDACL_OFF, 1),
258
259 SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
260 &es8323_left_mixer_controls[0],
261 ARRAY_SIZE(es8323_left_mixer_controls)),
262 SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
263 &es8323_right_mixer_controls[0],
264 ARRAY_SIZE(es8323_right_mixer_controls)),
265
266 SND_SOC_DAPM_PGA("Right Out 2", ES8323_DACPOWER, ES8323_DACPOWER_ROUT2_OFF, 0, NULL, 0),
267 SND_SOC_DAPM_PGA("Left Out 2", ES8323_DACPOWER, ES8323_DACPOWER_LOUT2_OFF, 0, NULL, 0),
268 SND_SOC_DAPM_PGA("Right Out 1", ES8323_DACPOWER, ES8323_DACPOWER_ROUT1_OFF, 0, NULL, 0),
269 SND_SOC_DAPM_PGA("Left Out 1", ES8323_DACPOWER, ES8323_DACPOWER_LOUT1_OFF, 0, NULL, 0),
270 SND_SOC_DAPM_PGA("LAMP", ES8323_ADCCONTROL1, ES8323_ADCCONTROL1_MICAMPL_OFF, 0, NULL, 0),
271 SND_SOC_DAPM_PGA("RAMP", ES8323_ADCCONTROL1, ES8323_ADCCONTROL1_MICAMPR_OFF, 0, NULL, 0),
272
273 SND_SOC_DAPM_OUTPUT("LOUT1"),
274 SND_SOC_DAPM_OUTPUT("ROUT1"),
275 SND_SOC_DAPM_OUTPUT("LOUT2"),
276 SND_SOC_DAPM_OUTPUT("ROUT2"),
277 SND_SOC_DAPM_OUTPUT("VREF"),
278 };
279
280 static const struct snd_soc_dapm_route es8323_dapm_routes[] = {
281 /*12.22*/
282 {"Left PGA Mux", "Line 1L", "LINPUT1"},
283 {"Left PGA Mux", "Line 2L", "LINPUT2"},
284 {"Left PGA Mux", "DifferentialL", "Differential Mux"},
285
286 {"Right PGA Mux", "Line 1R", "RINPUT1"},
287 {"Right PGA Mux", "Line 2R", "RINPUT2"},
288 {"Right PGA Mux", "DifferentialR", "Differential Mux"},
289
290 {"Differential Mux", "Line 1", "LINPUT1"},
291 {"Differential Mux", "Line 1", "RINPUT1"},
292 {"Differential Mux", "Line 2", "LINPUT2"},
293 {"Differential Mux", "Line 2", "RINPUT2"},
294
295 {"Left ADC Mux", "Stereo", "Left PGA Mux"},
296 {"Left ADC Mux", "Mono (Left)", "Left PGA Mux"},
297
298 {"Right ADC Mux", "Stereo", "Right PGA Mux"},
299 {"Right ADC Mux", "Mono (Right)", "Right PGA Mux"},
300
301 {"Left ADC", NULL, "Left ADC Mux"},
302 {"Right ADC", NULL, "Right ADC Mux"},
303
304 { "Mic Bias", NULL, "Mic Bias Gen" },
305
306 { "ADC DIG", NULL, "ADC STM" },
307 { "ADC DIG", NULL, "ADC Vref" },
308 { "ADC DIG", NULL, "ADC DLL" },
309
310 { "Left ADC", NULL, "ADC DIG" },
311 { "Right ADC", NULL, "ADC DIG" },
312
313 { "DAC DIG", NULL, "DAC STM" },
314 { "DAC DIG", NULL, "DAC Vref" },
315 { "DAC DIG", NULL, "DAC DLL" },
316
317 { "Left DAC", NULL, "DAC DIG" },
318 { "Right DAC", NULL, "DAC DIG" },
319
320 {"Left Line Mux", "Line 1L", "LINPUT1"},
321 {"Left Line Mux", "Line 2L", "LINPUT2"},
322 {"Left Line Mux", "MicL", "Left PGA Mux"},
323
324 {"Right Line Mux", "Line 1R", "RINPUT1"},
325 {"Right Line Mux", "Line 2R", "RINPUT2"},
326 {"Right Line Mux", "MicR", "Right PGA Mux"},
327
328 {"Left Mixer", "Left Playback Switch", "Left DAC"},
329 {"Left Mixer", "Left Bypass Switch", "Left Line Mux"},
330
331 {"Right Mixer", "Right Playback Switch", "Right DAC"},
332 {"Right Mixer", "Right Bypass Switch", "Right Line Mux"},
333
334 {"Left Out 1", NULL, "Left Mixer"},
335 {"LOUT1", NULL, "Left Out 1"},
336 {"Right Out 1", NULL, "Right Mixer"},
337 {"ROUT1", NULL, "Right Out 1"},
338
339 {"Left Out 2", NULL, "Left Mixer"},
340 {"LOUT2", NULL, "Left Out 2"},
341 {"Right Out 2", NULL, "Right Mixer"},
342 {"ROUT2", NULL, "Right Out 2"},
343 };
344
345 struct coeff_div {
346 u32 mclk;
347 u32 rate;
348 u16 fs;
349 u8 sr:4;
350 u8 usb:1;
351 };
352
353 /* codec hifi mclk clock divider coefficients */
354 static const struct coeff_div es8323_coeff_div[] = {
355 /* 8k */
356 {12288000, 8000, 1536, 0xa, 0x0},
357 {11289600, 8000, 1408, 0x9, 0x0},
358 {18432000, 8000, 2304, 0xc, 0x0},
359 {16934400, 8000, 2112, 0xb, 0x0},
360 {12000000, 8000, 1500, 0xb, 0x1},
361
362 /* 11.025k */
363 {11289600, 11025, 1024, 0x7, 0x0},
364 {16934400, 11025, 1536, 0xa, 0x0},
365 {12000000, 11025, 1088, 0x9, 0x1},
366
367 /* 16k */
368 {12288000, 16000, 768, 0x6, 0x0},
369 {18432000, 16000, 1152, 0x8, 0x0},
370 {12000000, 16000, 750, 0x7, 0x1},
371
372 /* 22.05k */
373 {11289600, 22050, 512, 0x4, 0x0},
374 {16934400, 22050, 768, 0x6, 0x0},
375 {12000000, 22050, 544, 0x6, 0x1},
376
377 /* 32k */
378 {12288000, 32000, 384, 0x3, 0x0},
379 {18432000, 32000, 576, 0x5, 0x0},
380 {12000000, 32000, 375, 0x4, 0x1},
381
382 /* 44.1k */
383 {11289600, 44100, 256, 0x2, 0x0},
384 {16934400, 44100, 384, 0x3, 0x0},
385 {12000000, 44100, 272, 0x3, 0x1},
386
387 /* 48k */
388 {12288000, 48000, 256, 0x2, 0x0},
389 {18432000, 48000, 384, 0x3, 0x0},
390 {12000000, 48000, 250, 0x2, 0x1},
391
392 /* 88.2k */
393 {11289600, 88200, 128, 0x0, 0x0},
394 {16934400, 88200, 192, 0x1, 0x0},
395 {12000000, 88200, 136, 0x1, 0x1},
396
397 /* 96k */
398 {12288000, 96000, 128, 0x0, 0x0},
399 {18432000, 96000, 192, 0x1, 0x0},
400 {12000000, 96000, 125, 0x0, 0x1},
401 };
402
403 static unsigned int rates_12288[] = {
404 8000, 12000, 16000, 24000, 24000, 32000, 48000, 96000,
405 };
406
407 static struct snd_pcm_hw_constraint_list constraints_12288 = {
408 .count = ARRAY_SIZE(rates_12288),
409 .list = rates_12288,
410 };
411
412 static unsigned int rates_112896[] = {
413 8000, 11025, 22050, 44100,
414 };
415
416 static struct snd_pcm_hw_constraint_list constraints_112896 = {
417 .count = ARRAY_SIZE(rates_112896),
418 .list = rates_112896,
419 };
420
421 static unsigned int rates_12[] = {
422 8000, 11025, 12000, 16000, 22050, 24000,
423 32000, 44100, 48000, 48000, 88235, 96000,
424 };
425
426 static struct snd_pcm_hw_constraint_list constraints_12 = {
427 .count = ARRAY_SIZE(rates_12),
428 .list = rates_12,
429 };
430
get_coeff(int mclk,int rate)431 static inline int get_coeff(int mclk, int rate)
432 {
433 int i;
434
435 for (i = 0; i < ARRAY_SIZE(es8323_coeff_div); i++) {
436 if (es8323_coeff_div[i].rate == rate &&
437 es8323_coeff_div[i].mclk == mclk)
438 return i;
439 }
440
441 return -EINVAL;
442 }
443
es8323_set_dai_sysclk(struct snd_soc_dai * codec_dai,int clk_id,unsigned int freq,int dir)444 static int es8323_set_dai_sysclk(struct snd_soc_dai *codec_dai,
445 int clk_id, unsigned int freq, int dir)
446 {
447 struct snd_soc_component *component = codec_dai->component;
448 struct es8323_priv *es8323 = snd_soc_component_get_drvdata(component);
449
450 switch (freq) {
451 case 11289600:
452 case 18432000:
453 case 22579200:
454 case 36864000:
455 es8323->sysclk_constraints = &constraints_112896;
456 break;
457 case 12288000:
458 case 16934400:
459 case 24576000:
460 case 33868800:
461 es8323->sysclk_constraints = &constraints_12288;
462 break;
463 case 12000000:
464 case 24000000:
465 es8323->sysclk_constraints = &constraints_12;
466 break;
467 default:
468 return -EINVAL;
469 }
470
471 es8323->sysclk = freq;
472 return 0;
473 }
474
es8323_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)475 static int es8323_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
476 {
477 struct snd_soc_component *component = codec_dai->component;
478 u8 format_mode, inv_mode;
479
480 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
481 case SND_SOC_DAIFMT_BC_FP:
482 /* Master serial port mode */
483 snd_soc_component_update_bits(component, ES8323_MASTERMODE,
484 ES8323_MASTERMODE_MSC, ES8323_MASTERMODE_MSC);
485 break;
486 case SND_SOC_DAIFMT_BC_FC:
487 /* Slave serial port mode */
488 snd_soc_component_update_bits(component, ES8323_MASTERMODE,
489 ES8323_MASTERMODE_MSC, 0);
490 break;
491 default:
492 return -EINVAL;
493 }
494
495 /* interface format */
496 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
497 case SND_SOC_DAIFMT_I2S:
498 format_mode = ES8323_FMT_I2S;
499 break;
500 case SND_SOC_DAIFMT_LEFT_J:
501 format_mode = ES8323_FMT_LEFT_J;
502 break;
503 case SND_SOC_DAIFMT_RIGHT_J:
504 format_mode = ES8323_FMT_RIGHT_J;
505 break;
506 case SND_SOC_DAIFMT_DSP_A:
507 case SND_SOC_DAIFMT_DSP_B:
508 format_mode = ES8323_FMT_DSP;
509 break;
510 default:
511 return -EINVAL;
512 }
513
514 snd_soc_component_write_field(component, ES8323_ADCCONTROL4,
515 ES8323_ADCCONTROL4_ADCFORMAT, format_mode);
516 snd_soc_component_write_field(component, ES8323_DACCONTROL1,
517 ES8323_DACCONTROL1_DACFORMAT, format_mode);
518
519 /* clock inversion */
520 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
521 case SND_SOC_DAIFMT_NB_NF:
522 case SND_SOC_DAIFMT_IB_NF:
523 inv_mode = 0;
524 break;
525 case SND_SOC_DAIFMT_IB_IF:
526 case SND_SOC_DAIFMT_NB_IF:
527 inv_mode = 1;
528 break;
529 default:
530 return -EINVAL;
531 }
532
533 snd_soc_component_update_bits(component, ES8323_MASTERMODE,
534 ES8323_MASTERMODE_BCLKINV, inv_mode);
535 snd_soc_component_update_bits(component, ES8323_ADCCONTROL4,
536 ES8323_ADCCONTROL4_ADCLRP, inv_mode);
537 snd_soc_component_update_bits(component, ES8323_DACCONTROL1,
538 ES8323_DACCONTROL1_DACLRP, inv_mode);
539
540 return 0;
541 }
542
es8323_pcm_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)543 static int es8323_pcm_startup(struct snd_pcm_substream *substream,
544 struct snd_soc_dai *dai)
545 {
546 struct snd_soc_component *component = dai->component;
547 struct es8323_priv *es8323 = snd_soc_component_get_drvdata(component);
548
549 if (es8323->sysclk) {
550 snd_pcm_hw_constraint_list(substream->runtime, 0,
551 SNDRV_PCM_HW_PARAM_RATE,
552 es8323->sysclk_constraints);
553 }
554
555 return 0;
556 }
557
es8323_pcm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)558 static int es8323_pcm_hw_params(struct snd_pcm_substream *substream,
559 struct snd_pcm_hw_params *params,
560 struct snd_soc_dai *dai)
561 {
562 struct snd_soc_component *component = dai->component;
563 struct es8323_priv *es8323 = snd_soc_component_get_drvdata(component);
564 u8 wl_mode, fs;
565 int coeff;
566
567 coeff = get_coeff(es8323->sysclk, params_rate(params));
568 if (coeff < 0) {
569 coeff = get_coeff(es8323->sysclk / 2, params_rate(params));
570 if (coeff < 0) {
571 dev_err(component->dev,
572 "Unable to configure sample rate %dHz with %dHz MCLK\n",
573 params_rate(params), es8323->sysclk);
574 return coeff;
575 }
576
577 snd_soc_component_update_bits(component, ES8323_MASTERMODE,
578 ES8323_MASTERMODE_MCLKDIV2,
579 ES8323_MASTERMODE_MCLKDIV2);
580 }
581
582 fs = FIELD_PREP(ES8323_DACCONTROL2_DACFSMODE, es8323_coeff_div[coeff].usb)
583 | FIELD_PREP(ES8323_DACCONTROL2_DACFSRATIO, es8323_coeff_div[coeff].sr);
584
585 snd_soc_component_write_field(component, ES8323_ADCCONTROL5,
586 ES8323_ADCCONTROL5_ADCFS_MASK, fs);
587
588 snd_soc_component_write_field(component, ES8323_DACCONTROL2,
589 ES8323_DACCONTROL2_DACFS_MASK, fs);
590
591 /* serial audio data word length */
592 switch (params_format(params)) {
593 case SNDRV_PCM_FORMAT_S16_LE:
594 wl_mode = ES8323_S16_LE;
595 break;
596 case SNDRV_PCM_FORMAT_S20_3LE:
597 wl_mode = ES8323_S20_LE;
598 break;
599 case SNDRV_PCM_FORMAT_S24_LE:
600 wl_mode = ES8323_S24_LE;
601 break;
602 case SNDRV_PCM_FORMAT_S32_LE:
603 wl_mode = ES8323_S32_LE;
604 break;
605 default:
606 return -EINVAL;
607 }
608
609 snd_soc_component_write_field(component, ES8323_ADCCONTROL4,
610 ES8323_ADCCONTROL4_ADCWL, wl_mode);
611
612 snd_soc_component_write_field(component, ES8323_DACCONTROL1,
613 ES8323_DACCONTROL1_DACWL, wl_mode);
614
615 return 0;
616 }
617
es8323_mute_stream(struct snd_soc_dai * dai,int mute,int stream)618 static int es8323_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
619 {
620 return snd_soc_component_update_bits(dai->component, ES8323_DACCONTROL3,
621 ES8323_DACCONTROL3_DACMUTE,
622 mute ? ES8323_DACCONTROL3_DACMUTE : 0);
623 }
624
625 static const struct snd_soc_dai_ops es8323_ops = {
626 .startup = es8323_pcm_startup,
627 .hw_params = es8323_pcm_hw_params,
628 .set_fmt = es8323_set_dai_fmt,
629 .set_sysclk = es8323_set_dai_sysclk,
630 .mute_stream = es8323_mute_stream,
631 };
632
633 #define ES8323_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
634 SNDRV_PCM_FMTBIT_S24_LE)
635
636 static struct snd_soc_dai_driver es8323_dai = {
637 .name = "ES8323 HiFi",
638 .playback = {
639 .stream_name = "Playback",
640 .channels_min = 1,
641 .channels_max = 2,
642 .rates = SNDRV_PCM_RATE_8000_96000,
643 .formats = ES8323_FORMATS,
644 },
645 .capture = {
646 .stream_name = "Capture",
647 .channels_min = 1,
648 .channels_max = 2,
649 .rates = SNDRV_PCM_RATE_8000_96000,
650 .formats = ES8323_FORMATS,
651 },
652 .ops = &es8323_ops,
653 .symmetric_rate = 1,
654 };
655
es8323_probe(struct snd_soc_component * component)656 static int es8323_probe(struct snd_soc_component *component)
657 {
658 struct es8323_priv *es8323 = snd_soc_component_get_drvdata(component);
659 int ret;
660
661 es8323->mclk = devm_clk_get_optional(component->dev, "mclk");
662 if (IS_ERR(es8323->mclk)) {
663 dev_err(component->dev, "unable to get mclk\n");
664 return PTR_ERR(es8323->mclk);
665 }
666
667 if (!es8323->mclk)
668 dev_warn(component->dev, "assuming static mclk\n");
669
670 ret = clk_prepare_enable(es8323->mclk);
671 if (ret) {
672 dev_err(component->dev, "unable to enable mclk\n");
673 return ret;
674 }
675
676 snd_soc_component_write(component, ES8323_CONTROL2, 0x60);
677 snd_soc_component_write(component, ES8323_DACCONTROL21, 0x80);
678
679 return 0;
680 }
681
es8323_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)682 static int es8323_set_bias_level(struct snd_soc_component *component,
683 enum snd_soc_bias_level level)
684 {
685 struct es8323_priv *es8323 = snd_soc_component_get_drvdata(component);
686 int ret;
687
688 switch (level) {
689 case SND_SOC_BIAS_ON:
690 break;
691 case SND_SOC_BIAS_PREPARE:
692 ret = clk_prepare_enable(es8323->mclk);
693 if (ret)
694 return ret;
695
696 snd_soc_component_write(component, ES8323_CHIPLOPOW1, 0x00);
697 snd_soc_component_write(component, ES8323_CHIPLOPOW2, 0x00);
698 snd_soc_component_update_bits(component, ES8323_ADCPOWER,
699 ES8323_ADCPOWER_PDNADCBIS, 0);
700 break;
701 case SND_SOC_BIAS_STANDBY:
702 break;
703 case SND_SOC_BIAS_OFF:
704 snd_soc_component_write(component, ES8323_CHIPLOPOW1, 0xff);
705 snd_soc_component_write(component, ES8323_CHIPLOPOW2, 0xff);
706 clk_disable_unprepare(es8323->mclk);
707 break;
708 }
709
710 return 0;
711 }
712
es8323_remove(struct snd_soc_component * component)713 static void es8323_remove(struct snd_soc_component *component)
714 {
715 struct es8323_priv *es8323 = snd_soc_component_get_drvdata(component);
716
717 clk_disable_unprepare(es8323->mclk);
718 es8323_set_bias_level(component, SND_SOC_BIAS_OFF);
719 }
720
es8323_suspend(struct snd_soc_component * component)721 static int es8323_suspend(struct snd_soc_component *component)
722 {
723 struct es8323_priv *es8323 = snd_soc_component_get_drvdata(component);
724
725 regcache_cache_only(es8323->regmap, true);
726 regcache_mark_dirty(es8323->regmap);
727
728 return 0;
729 }
730
es8323_resume(struct snd_soc_component * component)731 static int es8323_resume(struct snd_soc_component *component)
732 {
733 struct es8323_priv *es8323 = snd_soc_component_get_drvdata(component);
734
735 regcache_cache_only(es8323->regmap, false);
736 regcache_sync(es8323->regmap);
737
738 return 0;
739 }
740
741 static const struct snd_soc_component_driver soc_component_dev_es8323 = {
742 .probe = es8323_probe,
743 .remove = es8323_remove,
744 .suspend = es8323_suspend,
745 .resume = es8323_resume,
746 .set_bias_level = es8323_set_bias_level,
747 .controls = es8323_snd_controls,
748 .num_controls = ARRAY_SIZE(es8323_snd_controls),
749 .dapm_widgets = es8323_dapm_widgets,
750 .num_dapm_widgets = ARRAY_SIZE(es8323_dapm_widgets),
751 .dapm_routes = es8323_dapm_routes,
752 .num_dapm_routes = ARRAY_SIZE(es8323_dapm_routes),
753 .use_pmdown_time = 1,
754 .endianness = 1,
755 };
756
757 static const struct regmap_config es8323_regmap = {
758 .reg_bits = 8,
759 .val_bits = 8,
760 .use_single_read = true,
761 .use_single_write = true,
762 .max_register = 0x53,
763 .reg_defaults = es8323_reg_defaults,
764 .num_reg_defaults = ARRAY_SIZE(es8323_reg_defaults),
765 .cache_type = REGCACHE_MAPLE,
766 };
767
es8323_i2c_probe(struct i2c_client * i2c_client)768 static int es8323_i2c_probe(struct i2c_client *i2c_client)
769 {
770 struct es8323_priv *es8323;
771 struct device *dev = &i2c_client->dev;
772
773 es8323 = devm_kzalloc(dev, sizeof(*es8323), GFP_KERNEL);
774 if (!es8323)
775 return -ENOMEM;
776
777 i2c_set_clientdata(i2c_client, es8323);
778
779 es8323->regmap = devm_regmap_init_i2c(i2c_client, &es8323_regmap);
780 if (IS_ERR(es8323->regmap))
781 return PTR_ERR(es8323->regmap);
782
783 return devm_snd_soc_register_component(dev,
784 &soc_component_dev_es8323,
785 &es8323_dai, 1);
786 }
787
788 static const struct i2c_device_id es8323_i2c_id[] = {
789 { .name = "es8323" },
790 { }
791 };
792 MODULE_DEVICE_TABLE(i2c, es8323_i2c_id);
793
794 static const struct acpi_device_id es8323_acpi_match[] = {
795 { "ESSX8323", 0 },
796 { }
797 };
798 MODULE_DEVICE_TABLE(acpi, es8323_acpi_match);
799
800 static const struct of_device_id es8323_of_match[] = {
801 { .compatible = "everest,es8323" },
802 { }
803 };
804 MODULE_DEVICE_TABLE(of, es8323_of_match);
805
806 static struct i2c_driver es8323_i2c_driver = {
807 .driver = {
808 .name = "ES8323",
809 .acpi_match_table = es8323_acpi_match,
810 .of_match_table = es8323_of_match,
811 },
812 .probe = es8323_i2c_probe,
813 .id_table = es8323_i2c_id,
814 };
815 module_i2c_driver(es8323_i2c_driver);
816
817 MODULE_DESCRIPTION("Everest Semi ES8323 ALSA SoC Codec Driver");
818 MODULE_AUTHOR("Mark Brown <broonie@kernel.org>");
819 MODULE_AUTHOR("Binbin Zhou <zhoubinbin@loongson.cn>");
820 MODULE_LICENSE("GPL");
821