1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * linux/arch/arm/common/sa1111.c
4 *
5 * SA1111 support
6 *
7 * Original code by John Dorsey
8 *
9 * This file contains all generic SA1111 support.
10 *
11 * All initialization functions provided here are intended to be called
12 * from machine specific code with proper arguments when required.
13 */
14 #include <linux/module.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/init.h>
17 #include <linux/irq.h>
18 #include <linux/kernel.h>
19 #include <linux/delay.h>
20 #include <linux/errno.h>
21 #include <linux/ioport.h>
22 #include <linux/platform_device.h>
23 #include <linux/slab.h>
24 #include <linux/spinlock.h>
25 #include <linux/dma-map-ops.h>
26 #include <linux/clk.h>
27 #include <linux/io.h>
28
29 #include <asm/mach/irq.h>
30 #include <asm/mach-types.h>
31 #include <linux/sizes.h>
32
33 #include <asm/hardware/sa1111.h>
34
35 #ifdef CONFIG_ARCH_SA1100
36 #include <mach/hardware.h>
37 #endif
38
39 /* SA1111 IRQs */
40 #define IRQ_GPAIN0 (0)
41 #define IRQ_GPAIN1 (1)
42 #define IRQ_GPAIN2 (2)
43 #define IRQ_GPAIN3 (3)
44 #define IRQ_GPBIN0 (4)
45 #define IRQ_GPBIN1 (5)
46 #define IRQ_GPBIN2 (6)
47 #define IRQ_GPBIN3 (7)
48 #define IRQ_GPBIN4 (8)
49 #define IRQ_GPBIN5 (9)
50 #define IRQ_GPCIN0 (10)
51 #define IRQ_GPCIN1 (11)
52 #define IRQ_GPCIN2 (12)
53 #define IRQ_GPCIN3 (13)
54 #define IRQ_GPCIN4 (14)
55 #define IRQ_GPCIN5 (15)
56 #define IRQ_GPCIN6 (16)
57 #define IRQ_GPCIN7 (17)
58 #define IRQ_MSTXINT (18)
59 #define IRQ_MSRXINT (19)
60 #define IRQ_MSSTOPERRINT (20)
61 #define IRQ_TPTXINT (21)
62 #define IRQ_TPRXINT (22)
63 #define IRQ_TPSTOPERRINT (23)
64 #define SSPXMTINT (24)
65 #define SSPRCVINT (25)
66 #define SSPROR (26)
67 #define AUDXMTDMADONEA (32)
68 #define AUDRCVDMADONEA (33)
69 #define AUDXMTDMADONEB (34)
70 #define AUDRCVDMADONEB (35)
71 #define AUDTFSR (36)
72 #define AUDRFSR (37)
73 #define AUDTUR (38)
74 #define AUDROR (39)
75 #define AUDDTS (40)
76 #define AUDRDD (41)
77 #define AUDSTO (42)
78 #define IRQ_USBPWR (43)
79 #define IRQ_HCIM (44)
80 #define IRQ_HCIBUFFACC (45)
81 #define IRQ_HCIRMTWKP (46)
82 #define IRQ_NHCIMFCIR (47)
83 #define IRQ_USB_PORT_RESUME (48)
84 #define IRQ_S0_READY_NINT (49)
85 #define IRQ_S1_READY_NINT (50)
86 #define IRQ_S0_CD_VALID (51)
87 #define IRQ_S1_CD_VALID (52)
88 #define IRQ_S0_BVD1_STSCHG (53)
89 #define IRQ_S1_BVD1_STSCHG (54)
90 #define SA1111_IRQ_NR (55)
91
92 extern void sa1110_mb_enable(void);
93 extern void sa1110_mb_disable(void);
94
95 /*
96 * We keep the following data for the overall SA1111. Note that the
97 * struct device and struct resource are "fake"; they should be supplied
98 * by the bus above us. However, in the interests of getting all SA1111
99 * drivers converted over to the device model, we provide this as an
100 * anchor point for all the other drivers.
101 */
102 struct sa1111 {
103 struct device *dev;
104 struct clk *clk;
105 unsigned long phys;
106 int irq;
107 int irq_base; /* base for cascaded on-chip IRQs */
108 spinlock_t lock;
109 void __iomem *base;
110 struct sa1111_platform_data *pdata;
111 struct irq_domain *irqdomain;
112 struct gpio_chip gc;
113 #ifdef CONFIG_PM
114 void *saved_state;
115 #endif
116 };
117
118 /*
119 * We _really_ need to eliminate this. Its only users
120 * are the PWM and DMA checking code.
121 */
122 static struct sa1111 *g_sa1111;
123
124 struct sa1111_dev_info {
125 unsigned long offset;
126 unsigned long skpcr_mask;
127 bool dma;
128 unsigned int devid;
129 unsigned int hwirq[6];
130 };
131
132 static struct sa1111_dev_info sa1111_devices[] = {
133 {
134 .offset = SA1111_USB,
135 .skpcr_mask = SKPCR_UCLKEN,
136 .dma = true,
137 .devid = SA1111_DEVID_USB,
138 .hwirq = {
139 IRQ_USBPWR,
140 IRQ_HCIM,
141 IRQ_HCIBUFFACC,
142 IRQ_HCIRMTWKP,
143 IRQ_NHCIMFCIR,
144 IRQ_USB_PORT_RESUME
145 },
146 },
147 {
148 .offset = 0x0600,
149 .skpcr_mask = SKPCR_I2SCLKEN | SKPCR_L3CLKEN,
150 .dma = true,
151 .devid = SA1111_DEVID_SAC,
152 .hwirq = {
153 AUDXMTDMADONEA,
154 AUDXMTDMADONEB,
155 AUDRCVDMADONEA,
156 AUDRCVDMADONEB
157 },
158 },
159 {
160 .offset = 0x0800,
161 .skpcr_mask = SKPCR_SCLKEN,
162 .devid = SA1111_DEVID_SSP,
163 },
164 {
165 .offset = SA1111_KBD,
166 .skpcr_mask = SKPCR_PTCLKEN,
167 .devid = SA1111_DEVID_PS2_KBD,
168 .hwirq = {
169 IRQ_TPRXINT,
170 IRQ_TPTXINT
171 },
172 },
173 {
174 .offset = SA1111_MSE,
175 .skpcr_mask = SKPCR_PMCLKEN,
176 .devid = SA1111_DEVID_PS2_MSE,
177 .hwirq = {
178 IRQ_MSRXINT,
179 IRQ_MSTXINT
180 },
181 },
182 {
183 .offset = 0x1800,
184 .skpcr_mask = 0,
185 .devid = SA1111_DEVID_PCMCIA,
186 .hwirq = {
187 IRQ_S0_READY_NINT,
188 IRQ_S0_CD_VALID,
189 IRQ_S0_BVD1_STSCHG,
190 IRQ_S1_READY_NINT,
191 IRQ_S1_CD_VALID,
192 IRQ_S1_BVD1_STSCHG,
193 },
194 },
195 };
196
sa1111_map_irq(struct sa1111 * sachip,irq_hw_number_t hwirq)197 static int sa1111_map_irq(struct sa1111 *sachip, irq_hw_number_t hwirq)
198 {
199 return irq_create_mapping(sachip->irqdomain, hwirq);
200 }
201
202 /*
203 * SA1111 interrupt support. Since clearing an IRQ while there are
204 * active IRQs causes the interrupt output to pulse, the upper levels
205 * will call us again if there are more interrupts to process.
206 */
sa1111_irq_handler(struct irq_desc * desc)207 static void sa1111_irq_handler(struct irq_desc *desc)
208 {
209 unsigned int stat0, stat1, i;
210 struct sa1111 *sachip = irq_desc_get_handler_data(desc);
211 struct irq_domain *irqdomain;
212 void __iomem *mapbase = sachip->base + SA1111_INTC;
213
214 stat0 = readl_relaxed(mapbase + SA1111_INTSTATCLR0);
215 stat1 = readl_relaxed(mapbase + SA1111_INTSTATCLR1);
216
217 writel_relaxed(stat0, mapbase + SA1111_INTSTATCLR0);
218
219 desc->irq_data.chip->irq_ack(&desc->irq_data);
220
221 writel_relaxed(stat1, mapbase + SA1111_INTSTATCLR1);
222
223 if (stat0 == 0 && stat1 == 0) {
224 do_bad_IRQ(desc);
225 return;
226 }
227
228 irqdomain = sachip->irqdomain;
229
230 for (i = 0; stat0; i++, stat0 >>= 1)
231 if (stat0 & 1)
232 generic_handle_domain_irq(irqdomain, i);
233
234 for (i = 32; stat1; i++, stat1 >>= 1)
235 if (stat1 & 1)
236 generic_handle_domain_irq(irqdomain, i);
237
238 /* For level-based interrupts */
239 desc->irq_data.chip->irq_unmask(&desc->irq_data);
240 }
241
sa1111_irqmask(struct irq_data * d)242 static u32 sa1111_irqmask(struct irq_data *d)
243 {
244 return BIT(irqd_to_hwirq(d) & 31);
245 }
246
sa1111_irqbank(struct irq_data * d)247 static int sa1111_irqbank(struct irq_data *d)
248 {
249 return (irqd_to_hwirq(d) / 32) * 4;
250 }
251
sa1111_ack_irq(struct irq_data * d)252 static void sa1111_ack_irq(struct irq_data *d)
253 {
254 }
255
sa1111_mask_irq(struct irq_data * d)256 static void sa1111_mask_irq(struct irq_data *d)
257 {
258 struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
259 void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
260 u32 ie;
261
262 ie = readl_relaxed(mapbase + SA1111_INTEN0);
263 ie &= ~sa1111_irqmask(d);
264 writel(ie, mapbase + SA1111_INTEN0);
265 }
266
sa1111_unmask_irq(struct irq_data * d)267 static void sa1111_unmask_irq(struct irq_data *d)
268 {
269 struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
270 void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
271 u32 ie;
272
273 ie = readl_relaxed(mapbase + SA1111_INTEN0);
274 ie |= sa1111_irqmask(d);
275 writel_relaxed(ie, mapbase + SA1111_INTEN0);
276 }
277
278 /*
279 * Attempt to re-trigger the interrupt. The SA1111 contains a register
280 * (INTSET) which claims to do this. However, in practice no amount of
281 * manipulation of INTEN and INTSET guarantees that the interrupt will
282 * be triggered. In fact, its very difficult, if not impossible to get
283 * INTSET to re-trigger the interrupt.
284 */
sa1111_retrigger_irq(struct irq_data * d)285 static int sa1111_retrigger_irq(struct irq_data *d)
286 {
287 struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
288 void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
289 u32 ip, mask = sa1111_irqmask(d);
290 int i;
291
292 ip = readl_relaxed(mapbase + SA1111_INTPOL0);
293 for (i = 0; i < 8; i++) {
294 writel_relaxed(ip ^ mask, mapbase + SA1111_INTPOL0);
295 writel_relaxed(ip, mapbase + SA1111_INTPOL0);
296 if (readl_relaxed(mapbase + SA1111_INTSTATCLR0) & mask)
297 break;
298 }
299
300 if (i == 8) {
301 pr_err("Danger Will Robinson: failed to re-trigger IRQ%d\n",
302 d->irq);
303 return 0;
304 }
305
306 return 1;
307 }
308
sa1111_type_irq(struct irq_data * d,unsigned int flags)309 static int sa1111_type_irq(struct irq_data *d, unsigned int flags)
310 {
311 struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
312 void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
313 u32 ip, mask = sa1111_irqmask(d);
314
315 if (flags == IRQ_TYPE_PROBE)
316 return 0;
317
318 if ((!(flags & IRQ_TYPE_EDGE_RISING) ^ !(flags & IRQ_TYPE_EDGE_FALLING)) == 0)
319 return -EINVAL;
320
321 ip = readl_relaxed(mapbase + SA1111_INTPOL0);
322 if (flags & IRQ_TYPE_EDGE_RISING)
323 ip &= ~mask;
324 else
325 ip |= mask;
326 writel_relaxed(ip, mapbase + SA1111_INTPOL0);
327 writel_relaxed(ip, mapbase + SA1111_WAKEPOL0);
328
329 return 0;
330 }
331
sa1111_wake_irq(struct irq_data * d,unsigned int on)332 static int sa1111_wake_irq(struct irq_data *d, unsigned int on)
333 {
334 struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
335 void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
336 u32 we, mask = sa1111_irqmask(d);
337
338 we = readl_relaxed(mapbase + SA1111_WAKEEN0);
339 if (on)
340 we |= mask;
341 else
342 we &= ~mask;
343 writel_relaxed(we, mapbase + SA1111_WAKEEN0);
344
345 return 0;
346 }
347
348 static struct irq_chip sa1111_irq_chip = {
349 .name = "SA1111",
350 .irq_ack = sa1111_ack_irq,
351 .irq_mask = sa1111_mask_irq,
352 .irq_unmask = sa1111_unmask_irq,
353 .irq_retrigger = sa1111_retrigger_irq,
354 .irq_set_type = sa1111_type_irq,
355 .irq_set_wake = sa1111_wake_irq,
356 };
357
sa1111_irqdomain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hwirq)358 static int sa1111_irqdomain_map(struct irq_domain *d, unsigned int irq,
359 irq_hw_number_t hwirq)
360 {
361 struct sa1111 *sachip = d->host_data;
362
363 /* Disallow unavailable interrupts */
364 if (hwirq > SSPROR && hwirq < AUDXMTDMADONEA)
365 return -EINVAL;
366
367 irq_set_chip_data(irq, sachip);
368 irq_set_chip_and_handler(irq, &sa1111_irq_chip, handle_edge_irq);
369 irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
370
371 return 0;
372 }
373
374 static const struct irq_domain_ops sa1111_irqdomain_ops = {
375 .map = sa1111_irqdomain_map,
376 .xlate = irq_domain_xlate_twocell,
377 };
378
sa1111_setup_irq(struct sa1111 * sachip,unsigned irq_base)379 static int sa1111_setup_irq(struct sa1111 *sachip, unsigned irq_base)
380 {
381 void __iomem *irqbase = sachip->base + SA1111_INTC;
382 int ret;
383
384 /*
385 * We're guaranteed that this region hasn't been taken.
386 */
387 request_mem_region(sachip->phys + SA1111_INTC, 512, "irq");
388
389 ret = irq_alloc_descs(-1, irq_base, SA1111_IRQ_NR, -1);
390 if (ret <= 0) {
391 dev_err(sachip->dev, "unable to allocate %u irqs: %d\n",
392 SA1111_IRQ_NR, ret);
393 if (ret == 0)
394 ret = -EINVAL;
395 return ret;
396 }
397
398 sachip->irq_base = ret;
399
400 /* disable all IRQs */
401 writel_relaxed(0, irqbase + SA1111_INTEN0);
402 writel_relaxed(0, irqbase + SA1111_INTEN1);
403 writel_relaxed(0, irqbase + SA1111_WAKEEN0);
404 writel_relaxed(0, irqbase + SA1111_WAKEEN1);
405
406 /*
407 * detect on rising edge. Note: Feb 2001 Errata for SA1111
408 * specifies that S0ReadyInt and S1ReadyInt should be '1'.
409 */
410 writel_relaxed(0, irqbase + SA1111_INTPOL0);
411 writel_relaxed(BIT(IRQ_S0_READY_NINT & 31) |
412 BIT(IRQ_S1_READY_NINT & 31),
413 irqbase + SA1111_INTPOL1);
414
415 /* clear all IRQs */
416 writel_relaxed(~0, irqbase + SA1111_INTSTATCLR0);
417 writel_relaxed(~0, irqbase + SA1111_INTSTATCLR1);
418
419 sachip->irqdomain = irq_domain_create_linear(NULL, SA1111_IRQ_NR,
420 &sa1111_irqdomain_ops,
421 sachip);
422 if (!sachip->irqdomain) {
423 irq_free_descs(sachip->irq_base, SA1111_IRQ_NR);
424 return -ENOMEM;
425 }
426
427 irq_domain_associate_many(sachip->irqdomain,
428 sachip->irq_base + IRQ_GPAIN0,
429 IRQ_GPAIN0, SSPROR + 1 - IRQ_GPAIN0);
430 irq_domain_associate_many(sachip->irqdomain,
431 sachip->irq_base + AUDXMTDMADONEA,
432 AUDXMTDMADONEA,
433 IRQ_S1_BVD1_STSCHG + 1 - AUDXMTDMADONEA);
434
435 /*
436 * Register SA1111 interrupt
437 */
438 irq_set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING);
439 irq_set_chained_handler_and_data(sachip->irq, sa1111_irq_handler,
440 sachip);
441
442 dev_info(sachip->dev, "Providing IRQ%u-%u\n",
443 sachip->irq_base, sachip->irq_base + SA1111_IRQ_NR - 1);
444
445 return 0;
446 }
447
sa1111_remove_irq(struct sa1111 * sachip)448 static void sa1111_remove_irq(struct sa1111 *sachip)
449 {
450 struct irq_domain *domain = sachip->irqdomain;
451 void __iomem *irqbase = sachip->base + SA1111_INTC;
452 int i;
453
454 /* disable all IRQs */
455 writel_relaxed(0, irqbase + SA1111_INTEN0);
456 writel_relaxed(0, irqbase + SA1111_INTEN1);
457 writel_relaxed(0, irqbase + SA1111_WAKEEN0);
458 writel_relaxed(0, irqbase + SA1111_WAKEEN1);
459
460 irq_set_chained_handler_and_data(sachip->irq, NULL, NULL);
461 for (i = 0; i < SA1111_IRQ_NR; i++)
462 irq_dispose_mapping(irq_find_mapping(domain, i));
463 irq_domain_remove(domain);
464
465 release_mem_region(sachip->phys + SA1111_INTC, 512);
466 }
467
468 enum {
469 SA1111_GPIO_PXDDR = (SA1111_GPIO_PADDR - SA1111_GPIO_PADDR),
470 SA1111_GPIO_PXDRR = (SA1111_GPIO_PADRR - SA1111_GPIO_PADDR),
471 SA1111_GPIO_PXDWR = (SA1111_GPIO_PADWR - SA1111_GPIO_PADDR),
472 SA1111_GPIO_PXSDR = (SA1111_GPIO_PASDR - SA1111_GPIO_PADDR),
473 SA1111_GPIO_PXSSR = (SA1111_GPIO_PASSR - SA1111_GPIO_PADDR),
474 };
475
gc_to_sa1111(struct gpio_chip * gc)476 static struct sa1111 *gc_to_sa1111(struct gpio_chip *gc)
477 {
478 return container_of(gc, struct sa1111, gc);
479 }
480
sa1111_gpio_map_reg(struct sa1111 * sachip,unsigned offset)481 static void __iomem *sa1111_gpio_map_reg(struct sa1111 *sachip, unsigned offset)
482 {
483 void __iomem *reg = sachip->base + SA1111_GPIO;
484
485 if (offset < 4)
486 return reg + SA1111_GPIO_PADDR;
487 if (offset < 10)
488 return reg + SA1111_GPIO_PBDDR;
489 if (offset < 18)
490 return reg + SA1111_GPIO_PCDDR;
491 return NULL;
492 }
493
sa1111_gpio_map_bit(unsigned offset)494 static u32 sa1111_gpio_map_bit(unsigned offset)
495 {
496 if (offset < 4)
497 return BIT(offset);
498 if (offset < 10)
499 return BIT(offset - 4);
500 if (offset < 18)
501 return BIT(offset - 10);
502 return 0;
503 }
504
sa1111_gpio_modify(void __iomem * reg,u32 mask,u32 set)505 static void sa1111_gpio_modify(void __iomem *reg, u32 mask, u32 set)
506 {
507 u32 val;
508
509 val = readl_relaxed(reg);
510 val &= ~mask;
511 val |= mask & set;
512 writel_relaxed(val, reg);
513 }
514
sa1111_gpio_get_direction(struct gpio_chip * gc,unsigned offset)515 static int sa1111_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
516 {
517 struct sa1111 *sachip = gc_to_sa1111(gc);
518 void __iomem *reg = sa1111_gpio_map_reg(sachip, offset);
519 u32 mask = sa1111_gpio_map_bit(offset);
520
521 return !!(readl_relaxed(reg + SA1111_GPIO_PXDDR) & mask);
522 }
523
sa1111_gpio_direction_input(struct gpio_chip * gc,unsigned offset)524 static int sa1111_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
525 {
526 struct sa1111 *sachip = gc_to_sa1111(gc);
527 unsigned long flags;
528 void __iomem *reg = sa1111_gpio_map_reg(sachip, offset);
529 u32 mask = sa1111_gpio_map_bit(offset);
530
531 spin_lock_irqsave(&sachip->lock, flags);
532 sa1111_gpio_modify(reg + SA1111_GPIO_PXDDR, mask, mask);
533 sa1111_gpio_modify(reg + SA1111_GPIO_PXSDR, mask, mask);
534 spin_unlock_irqrestore(&sachip->lock, flags);
535
536 return 0;
537 }
538
sa1111_gpio_direction_output(struct gpio_chip * gc,unsigned offset,int value)539 static int sa1111_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
540 int value)
541 {
542 struct sa1111 *sachip = gc_to_sa1111(gc);
543 unsigned long flags;
544 void __iomem *reg = sa1111_gpio_map_reg(sachip, offset);
545 u32 mask = sa1111_gpio_map_bit(offset);
546
547 spin_lock_irqsave(&sachip->lock, flags);
548 sa1111_gpio_modify(reg + SA1111_GPIO_PXDWR, mask, value ? mask : 0);
549 sa1111_gpio_modify(reg + SA1111_GPIO_PXSSR, mask, value ? mask : 0);
550 sa1111_gpio_modify(reg + SA1111_GPIO_PXDDR, mask, 0);
551 sa1111_gpio_modify(reg + SA1111_GPIO_PXSDR, mask, 0);
552 spin_unlock_irqrestore(&sachip->lock, flags);
553
554 return 0;
555 }
556
sa1111_gpio_get(struct gpio_chip * gc,unsigned offset)557 static int sa1111_gpio_get(struct gpio_chip *gc, unsigned offset)
558 {
559 struct sa1111 *sachip = gc_to_sa1111(gc);
560 void __iomem *reg = sa1111_gpio_map_reg(sachip, offset);
561 u32 mask = sa1111_gpio_map_bit(offset);
562
563 return !!(readl_relaxed(reg + SA1111_GPIO_PXDRR) & mask);
564 }
565
sa1111_gpio_set(struct gpio_chip * gc,unsigned int offset,int value)566 static int sa1111_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
567 {
568 struct sa1111 *sachip = gc_to_sa1111(gc);
569 unsigned long flags;
570 void __iomem *reg = sa1111_gpio_map_reg(sachip, offset);
571 u32 mask = sa1111_gpio_map_bit(offset);
572
573 spin_lock_irqsave(&sachip->lock, flags);
574 sa1111_gpio_modify(reg + SA1111_GPIO_PXDWR, mask, value ? mask : 0);
575 sa1111_gpio_modify(reg + SA1111_GPIO_PXSSR, mask, value ? mask : 0);
576 spin_unlock_irqrestore(&sachip->lock, flags);
577
578 return 0;
579 }
580
sa1111_gpio_set_multiple(struct gpio_chip * gc,unsigned long * mask,unsigned long * bits)581 static void sa1111_gpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
582 unsigned long *bits)
583 {
584 struct sa1111 *sachip = gc_to_sa1111(gc);
585 unsigned long flags;
586 void __iomem *reg = sachip->base + SA1111_GPIO;
587 u32 msk, val;
588
589 msk = *mask;
590 val = *bits;
591
592 spin_lock_irqsave(&sachip->lock, flags);
593 sa1111_gpio_modify(reg + SA1111_GPIO_PADWR, msk & 15, val);
594 sa1111_gpio_modify(reg + SA1111_GPIO_PASSR, msk & 15, val);
595 sa1111_gpio_modify(reg + SA1111_GPIO_PBDWR, (msk >> 4) & 255, val >> 4);
596 sa1111_gpio_modify(reg + SA1111_GPIO_PBSSR, (msk >> 4) & 255, val >> 4);
597 sa1111_gpio_modify(reg + SA1111_GPIO_PCDWR, (msk >> 12) & 255, val >> 12);
598 sa1111_gpio_modify(reg + SA1111_GPIO_PCSSR, (msk >> 12) & 255, val >> 12);
599 spin_unlock_irqrestore(&sachip->lock, flags);
600 }
601
sa1111_gpio_to_irq(struct gpio_chip * gc,unsigned offset)602 static int sa1111_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
603 {
604 struct sa1111 *sachip = gc_to_sa1111(gc);
605
606 return sa1111_map_irq(sachip, offset);
607 }
608
sa1111_setup_gpios(struct sa1111 * sachip)609 static int sa1111_setup_gpios(struct sa1111 *sachip)
610 {
611 sachip->gc.label = "sa1111";
612 sachip->gc.parent = sachip->dev;
613 sachip->gc.owner = THIS_MODULE;
614 sachip->gc.get_direction = sa1111_gpio_get_direction;
615 sachip->gc.direction_input = sa1111_gpio_direction_input;
616 sachip->gc.direction_output = sa1111_gpio_direction_output;
617 sachip->gc.get = sa1111_gpio_get;
618 sachip->gc.set_rv = sa1111_gpio_set;
619 sachip->gc.set_multiple = sa1111_gpio_set_multiple;
620 sachip->gc.to_irq = sa1111_gpio_to_irq;
621 sachip->gc.base = -1;
622 sachip->gc.ngpio = 18;
623
624 return devm_gpiochip_add_data(sachip->dev, &sachip->gc, sachip);
625 }
626
627 /*
628 * Bring the SA1111 out of reset. This requires a set procedure:
629 * 1. nRESET asserted (by hardware)
630 * 2. CLK turned on from SA1110
631 * 3. nRESET deasserted
632 * 4. VCO turned on, PLL_BYPASS turned off
633 * 5. Wait lock time, then assert RCLKEn
634 * 7. PCR set to allow clocking of individual functions
635 *
636 * Until we've done this, the only registers we can access are:
637 * SBI_SKCR
638 * SBI_SMCR
639 * SBI_SKID
640 */
sa1111_wake(struct sa1111 * sachip)641 static void sa1111_wake(struct sa1111 *sachip)
642 {
643 unsigned long flags, r;
644
645 spin_lock_irqsave(&sachip->lock, flags);
646
647 clk_enable(sachip->clk);
648
649 /*
650 * Turn VCO on, and disable PLL Bypass.
651 */
652 r = readl_relaxed(sachip->base + SA1111_SKCR);
653 r &= ~SKCR_VCO_OFF;
654 writel_relaxed(r, sachip->base + SA1111_SKCR);
655 r |= SKCR_PLL_BYPASS | SKCR_OE_EN;
656 writel_relaxed(r, sachip->base + SA1111_SKCR);
657
658 /*
659 * Wait lock time. SA1111 manual _doesn't_
660 * specify a figure for this! We choose 100us.
661 */
662 udelay(100);
663
664 /*
665 * Enable RCLK. We also ensure that RDYEN is set.
666 */
667 r |= SKCR_RCLKEN | SKCR_RDYEN;
668 writel_relaxed(r, sachip->base + SA1111_SKCR);
669
670 /*
671 * Wait 14 RCLK cycles for the chip to finish coming out
672 * of reset. (RCLK=24MHz). This is 590ns.
673 */
674 udelay(1);
675
676 /*
677 * Ensure all clocks are initially off.
678 */
679 writel_relaxed(0, sachip->base + SA1111_SKPCR);
680
681 spin_unlock_irqrestore(&sachip->lock, flags);
682 }
683
684 #ifdef CONFIG_ARCH_SA1100
685
686 static u32 sa1111_dma_mask[] = {
687 ~0,
688 ~(1 << 20),
689 ~(1 << 23),
690 ~(1 << 24),
691 ~(1 << 25),
692 ~(1 << 20),
693 ~(1 << 20),
694 0,
695 };
696
697 /*
698 * Configure the SA1111 shared memory controller.
699 */
700 static void
sa1111_configure_smc(struct sa1111 * sachip,int sdram,unsigned int drac,unsigned int cas_latency)701 sa1111_configure_smc(struct sa1111 *sachip, int sdram, unsigned int drac,
702 unsigned int cas_latency)
703 {
704 unsigned int smcr = SMCR_DTIM | SMCR_MBGE | FInsrt(drac, SMCR_DRAC);
705
706 if (cas_latency == 3)
707 smcr |= SMCR_CLAT;
708
709 writel_relaxed(smcr, sachip->base + SA1111_SMCR);
710
711 /*
712 * Now clear the bits in the DMA mask to work around the SA1111
713 * DMA erratum (Intel StrongARM SA-1111 Microprocessor Companion
714 * Chip Specification Update, June 2000, Erratum #7).
715 */
716 if (sachip->dev->dma_mask)
717 *sachip->dev->dma_mask &= sa1111_dma_mask[drac >> 2];
718
719 sachip->dev->coherent_dma_mask &= sa1111_dma_mask[drac >> 2];
720 }
721 #endif
722
sa1111_dev_release(struct device * _dev)723 static void sa1111_dev_release(struct device *_dev)
724 {
725 struct sa1111_dev *dev = to_sa1111_device(_dev);
726
727 kfree(dev);
728 }
729
730 static int
sa1111_init_one_child(struct sa1111 * sachip,struct resource * parent,struct sa1111_dev_info * info)731 sa1111_init_one_child(struct sa1111 *sachip, struct resource *parent,
732 struct sa1111_dev_info *info)
733 {
734 struct sa1111_dev *dev;
735 unsigned i;
736 int ret;
737
738 dev = kzalloc(sizeof(struct sa1111_dev), GFP_KERNEL);
739 if (!dev) {
740 ret = -ENOMEM;
741 goto err_alloc;
742 }
743
744 device_initialize(&dev->dev);
745 dev_set_name(&dev->dev, "%4.4lx", info->offset);
746 dev->devid = info->devid;
747 dev->dev.parent = sachip->dev;
748 dev->dev.bus = &sa1111_bus_type;
749 dev->dev.release = sa1111_dev_release;
750 dev->res.start = sachip->phys + info->offset;
751 dev->res.end = dev->res.start + 511;
752 dev->res.name = dev_name(&dev->dev);
753 dev->res.flags = IORESOURCE_MEM;
754 dev->mapbase = sachip->base + info->offset;
755 dev->skpcr_mask = info->skpcr_mask;
756
757 for (i = 0; i < ARRAY_SIZE(info->hwirq); i++)
758 dev->hwirq[i] = info->hwirq[i];
759
760 /*
761 * If the parent device has a DMA mask associated with it, and
762 * this child supports DMA, propagate it down to the children.
763 */
764 if (info->dma && sachip->dev->dma_mask) {
765 dev->dma_mask = *sachip->dev->dma_mask;
766 dev->dev.dma_mask = &dev->dma_mask;
767 dev->dev.coherent_dma_mask = sachip->dev->coherent_dma_mask;
768 }
769
770 ret = request_resource(parent, &dev->res);
771 if (ret) {
772 dev_err(sachip->dev, "failed to allocate resource for %s\n",
773 dev->res.name);
774 goto err_resource;
775 }
776
777 ret = device_add(&dev->dev);
778 if (ret)
779 goto err_add;
780 return 0;
781
782 err_add:
783 release_resource(&dev->res);
784 err_resource:
785 put_device(&dev->dev);
786 err_alloc:
787 return ret;
788 }
789
__sa1111_probe(struct device * me,struct resource * mem,int irq)790 static int __sa1111_probe(struct device *me, struct resource *mem, int irq)
791 {
792 struct sa1111_platform_data *pd = me->platform_data;
793 struct sa1111 *sachip;
794 unsigned long id;
795 unsigned int has_devs;
796 int i, ret = -ENODEV;
797
798 if (!pd)
799 return -EINVAL;
800
801 sachip = devm_kzalloc(me, sizeof(struct sa1111), GFP_KERNEL);
802 if (!sachip)
803 return -ENOMEM;
804
805 sachip->clk = devm_clk_get(me, "SA1111_CLK");
806 if (IS_ERR(sachip->clk))
807 return PTR_ERR(sachip->clk);
808
809 ret = clk_prepare(sachip->clk);
810 if (ret)
811 return ret;
812
813 spin_lock_init(&sachip->lock);
814
815 sachip->dev = me;
816 dev_set_drvdata(sachip->dev, sachip);
817
818 sachip->pdata = pd;
819 sachip->phys = mem->start;
820 sachip->irq = irq;
821
822 /*
823 * Map the whole region. This also maps the
824 * registers for our children.
825 */
826 sachip->base = ioremap(mem->start, PAGE_SIZE * 2);
827 if (!sachip->base) {
828 ret = -ENOMEM;
829 goto err_clk_unprep;
830 }
831
832 /*
833 * Probe for the chip. Only touch the SBI registers.
834 */
835 id = readl_relaxed(sachip->base + SA1111_SKID);
836 if ((id & SKID_ID_MASK) != SKID_SA1111_ID) {
837 printk(KERN_DEBUG "SA1111 not detected: ID = %08lx\n", id);
838 ret = -ENODEV;
839 goto err_unmap;
840 }
841
842 pr_info("SA1111 Microprocessor Companion Chip: silicon revision %lx, metal revision %lx\n",
843 (id & SKID_SIREV_MASK) >> 4, id & SKID_MTREV_MASK);
844
845 /*
846 * We found it. Wake the chip up, and initialise.
847 */
848 sa1111_wake(sachip);
849
850 /*
851 * The interrupt controller must be initialised before any
852 * other device to ensure that the interrupts are available.
853 */
854 ret = sa1111_setup_irq(sachip, pd->irq_base);
855 if (ret)
856 goto err_clk;
857
858 /* Setup the GPIOs - should really be done after the IRQ setup */
859 ret = sa1111_setup_gpios(sachip);
860 if (ret)
861 goto err_irq;
862
863 #ifdef CONFIG_ARCH_SA1100
864 {
865 unsigned int val;
866
867 /*
868 * The SDRAM configuration of the SA1110 and the SA1111 must
869 * match. This is very important to ensure that SA1111 accesses
870 * don't corrupt the SDRAM. Note that this ungates the SA1111's
871 * MBGNT signal, so we must have called sa1110_mb_disable()
872 * beforehand.
873 */
874 sa1111_configure_smc(sachip, 1,
875 FExtr(MDCNFG, MDCNFG_SA1110_DRAC0),
876 FExtr(MDCNFG, MDCNFG_SA1110_TDL0));
877
878 /*
879 * We only need to turn on DCLK whenever we want to use the
880 * DMA. It can otherwise be held firmly in the off position.
881 * (currently, we always enable it.)
882 */
883 val = readl_relaxed(sachip->base + SA1111_SKPCR);
884 writel_relaxed(val | SKPCR_DCLKEN, sachip->base + SA1111_SKPCR);
885
886 /*
887 * Enable the SA1110 memory bus request and grant signals.
888 */
889 sa1110_mb_enable();
890 }
891 #endif
892
893 g_sa1111 = sachip;
894
895 has_devs = ~0;
896 if (pd)
897 has_devs &= ~pd->disable_devs;
898
899 for (i = 0; i < ARRAY_SIZE(sa1111_devices); i++)
900 if (sa1111_devices[i].devid & has_devs)
901 sa1111_init_one_child(sachip, mem, &sa1111_devices[i]);
902
903 return 0;
904
905 err_irq:
906 sa1111_remove_irq(sachip);
907 err_clk:
908 clk_disable(sachip->clk);
909 err_unmap:
910 iounmap(sachip->base);
911 err_clk_unprep:
912 clk_unprepare(sachip->clk);
913 return ret;
914 }
915
sa1111_remove_one(struct device * dev,void * data)916 static int sa1111_remove_one(struct device *dev, void *data)
917 {
918 struct sa1111_dev *sadev = to_sa1111_device(dev);
919 if (dev->bus != &sa1111_bus_type)
920 return 0;
921 device_del(&sadev->dev);
922 release_resource(&sadev->res);
923 put_device(&sadev->dev);
924 return 0;
925 }
926
__sa1111_remove(struct sa1111 * sachip)927 static void __sa1111_remove(struct sa1111 *sachip)
928 {
929 device_for_each_child(sachip->dev, NULL, sa1111_remove_one);
930
931 sa1111_remove_irq(sachip);
932
933 clk_disable(sachip->clk);
934 clk_unprepare(sachip->clk);
935
936 iounmap(sachip->base);
937 }
938
939 struct sa1111_save_data {
940 unsigned int skcr;
941 unsigned int skpcr;
942 unsigned int skcdr;
943 unsigned char skaud;
944 unsigned char skpwm0;
945 unsigned char skpwm1;
946
947 /*
948 * Interrupt controller
949 */
950 unsigned int intpol0;
951 unsigned int intpol1;
952 unsigned int inten0;
953 unsigned int inten1;
954 unsigned int wakepol0;
955 unsigned int wakepol1;
956 unsigned int wakeen0;
957 unsigned int wakeen1;
958 };
959
960 #ifdef CONFIG_PM
961
sa1111_suspend_noirq(struct device * dev)962 static int sa1111_suspend_noirq(struct device *dev)
963 {
964 struct sa1111 *sachip = dev_get_drvdata(dev);
965 struct sa1111_save_data *save;
966 unsigned long flags;
967 unsigned int val;
968 void __iomem *base;
969
970 save = kmalloc(sizeof(struct sa1111_save_data), GFP_KERNEL);
971 if (!save)
972 return -ENOMEM;
973 sachip->saved_state = save;
974
975 spin_lock_irqsave(&sachip->lock, flags);
976
977 /*
978 * Save state.
979 */
980 base = sachip->base;
981 save->skcr = readl_relaxed(base + SA1111_SKCR);
982 save->skpcr = readl_relaxed(base + SA1111_SKPCR);
983 save->skcdr = readl_relaxed(base + SA1111_SKCDR);
984 save->skaud = readl_relaxed(base + SA1111_SKAUD);
985 save->skpwm0 = readl_relaxed(base + SA1111_SKPWM0);
986 save->skpwm1 = readl_relaxed(base + SA1111_SKPWM1);
987
988 writel_relaxed(0, sachip->base + SA1111_SKPWM0);
989 writel_relaxed(0, sachip->base + SA1111_SKPWM1);
990
991 base = sachip->base + SA1111_INTC;
992 save->intpol0 = readl_relaxed(base + SA1111_INTPOL0);
993 save->intpol1 = readl_relaxed(base + SA1111_INTPOL1);
994 save->inten0 = readl_relaxed(base + SA1111_INTEN0);
995 save->inten1 = readl_relaxed(base + SA1111_INTEN1);
996 save->wakepol0 = readl_relaxed(base + SA1111_WAKEPOL0);
997 save->wakepol1 = readl_relaxed(base + SA1111_WAKEPOL1);
998 save->wakeen0 = readl_relaxed(base + SA1111_WAKEEN0);
999 save->wakeen1 = readl_relaxed(base + SA1111_WAKEEN1);
1000
1001 /*
1002 * Disable.
1003 */
1004 val = readl_relaxed(sachip->base + SA1111_SKCR);
1005 writel_relaxed(val | SKCR_SLEEP, sachip->base + SA1111_SKCR);
1006
1007 clk_disable(sachip->clk);
1008
1009 spin_unlock_irqrestore(&sachip->lock, flags);
1010
1011 #ifdef CONFIG_ARCH_SA1100
1012 sa1110_mb_disable();
1013 #endif
1014
1015 return 0;
1016 }
1017
1018 /*
1019 * sa1111_resume - Restore the SA1111 device state.
1020 * @dev: device to restore
1021 *
1022 * Restore the general state of the SA1111; clock control and
1023 * interrupt controller. Other parts of the SA1111 must be
1024 * restored by their respective drivers, and must be called
1025 * via LDM after this function.
1026 */
sa1111_resume_noirq(struct device * dev)1027 static int sa1111_resume_noirq(struct device *dev)
1028 {
1029 struct sa1111 *sachip = dev_get_drvdata(dev);
1030 struct sa1111_save_data *save;
1031 unsigned long flags, id;
1032 void __iomem *base;
1033
1034 save = sachip->saved_state;
1035 if (!save)
1036 return 0;
1037
1038 /*
1039 * Ensure that the SA1111 is still here.
1040 * FIXME: shouldn't do this here.
1041 */
1042 id = readl_relaxed(sachip->base + SA1111_SKID);
1043 if ((id & SKID_ID_MASK) != SKID_SA1111_ID) {
1044 __sa1111_remove(sachip);
1045 dev_set_drvdata(dev, NULL);
1046 kfree(save);
1047 return 0;
1048 }
1049
1050 /*
1051 * First of all, wake up the chip.
1052 */
1053 sa1111_wake(sachip);
1054
1055 #ifdef CONFIG_ARCH_SA1100
1056 /* Enable the memory bus request/grant signals */
1057 sa1110_mb_enable();
1058 #endif
1059
1060 /*
1061 * Only lock for write ops. Also, sa1111_wake must be called with
1062 * released spinlock!
1063 */
1064 spin_lock_irqsave(&sachip->lock, flags);
1065
1066 writel_relaxed(0, sachip->base + SA1111_INTC + SA1111_INTEN0);
1067 writel_relaxed(0, sachip->base + SA1111_INTC + SA1111_INTEN1);
1068
1069 base = sachip->base;
1070 writel_relaxed(save->skcr, base + SA1111_SKCR);
1071 writel_relaxed(save->skpcr, base + SA1111_SKPCR);
1072 writel_relaxed(save->skcdr, base + SA1111_SKCDR);
1073 writel_relaxed(save->skaud, base + SA1111_SKAUD);
1074 writel_relaxed(save->skpwm0, base + SA1111_SKPWM0);
1075 writel_relaxed(save->skpwm1, base + SA1111_SKPWM1);
1076
1077 base = sachip->base + SA1111_INTC;
1078 writel_relaxed(save->intpol0, base + SA1111_INTPOL0);
1079 writel_relaxed(save->intpol1, base + SA1111_INTPOL1);
1080 writel_relaxed(save->inten0, base + SA1111_INTEN0);
1081 writel_relaxed(save->inten1, base + SA1111_INTEN1);
1082 writel_relaxed(save->wakepol0, base + SA1111_WAKEPOL0);
1083 writel_relaxed(save->wakepol1, base + SA1111_WAKEPOL1);
1084 writel_relaxed(save->wakeen0, base + SA1111_WAKEEN0);
1085 writel_relaxed(save->wakeen1, base + SA1111_WAKEEN1);
1086
1087 spin_unlock_irqrestore(&sachip->lock, flags);
1088
1089 sachip->saved_state = NULL;
1090 kfree(save);
1091
1092 return 0;
1093 }
1094
1095 #else
1096 #define sa1111_suspend_noirq NULL
1097 #define sa1111_resume_noirq NULL
1098 #endif
1099
1100 /**
1101 * sa1111_probe - probe for a single SA1111 chip.
1102 * @pdev: platform device.
1103 *
1104 * Probe for a SA1111 chip. This must be called
1105 * before any other SA1111-specific code.
1106 *
1107 * Returns:
1108 * * %-ENODEV - device not found.
1109 * * %-ENOMEM - memory allocation failure.
1110 * * %-EBUSY - physical address already marked in-use.
1111 * * %-EINVAL - no platform data passed
1112 * * %0 - successful.
1113 */
sa1111_probe(struct platform_device * pdev)1114 static int sa1111_probe(struct platform_device *pdev)
1115 {
1116 struct resource *mem;
1117 int irq;
1118
1119 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1120 if (!mem)
1121 return -EINVAL;
1122 irq = platform_get_irq(pdev, 0);
1123 if (irq < 0)
1124 return irq;
1125
1126 return __sa1111_probe(&pdev->dev, mem, irq);
1127 }
1128
sa1111_remove(struct platform_device * pdev)1129 static void sa1111_remove(struct platform_device *pdev)
1130 {
1131 struct sa1111 *sachip = platform_get_drvdata(pdev);
1132
1133 if (sachip) {
1134 #ifdef CONFIG_PM
1135 kfree(sachip->saved_state);
1136 sachip->saved_state = NULL;
1137 #endif
1138 __sa1111_remove(sachip);
1139 platform_set_drvdata(pdev, NULL);
1140 }
1141 }
1142
1143 static struct dev_pm_ops sa1111_pm_ops = {
1144 .suspend_noirq = sa1111_suspend_noirq,
1145 .resume_noirq = sa1111_resume_noirq,
1146 };
1147
1148 /*
1149 * Not sure if this should be on the system bus or not yet.
1150 * We really want some way to register a system device at
1151 * the per-machine level, and then have this driver pick
1152 * up the registered devices.
1153 *
1154 * We also need to handle the SDRAM configuration for
1155 * PXA250/SA1110 machine classes.
1156 */
1157 static struct platform_driver sa1111_device_driver = {
1158 .probe = sa1111_probe,
1159 .remove = sa1111_remove,
1160 .driver = {
1161 .name = "sa1111",
1162 .pm = &sa1111_pm_ops,
1163 },
1164 };
1165
1166 /*
1167 * Get the parent device driver (us) structure
1168 * from a child function device
1169 */
sa1111_chip_driver(struct sa1111_dev * sadev)1170 static inline struct sa1111 *sa1111_chip_driver(struct sa1111_dev *sadev)
1171 {
1172 return (struct sa1111 *)dev_get_drvdata(sadev->dev.parent);
1173 }
1174
1175 /*
1176 * The bits in the opdiv field are non-linear.
1177 */
1178 static unsigned char opdiv_table[] = { 1, 4, 2, 8 };
1179
__sa1111_pll_clock(struct sa1111 * sachip)1180 static unsigned int __sa1111_pll_clock(struct sa1111 *sachip)
1181 {
1182 unsigned int skcdr, fbdiv, ipdiv, opdiv;
1183
1184 skcdr = readl_relaxed(sachip->base + SA1111_SKCDR);
1185
1186 fbdiv = (skcdr & 0x007f) + 2;
1187 ipdiv = ((skcdr & 0x0f80) >> 7) + 2;
1188 opdiv = opdiv_table[(skcdr & 0x3000) >> 12];
1189
1190 return 3686400 * fbdiv / (ipdiv * opdiv);
1191 }
1192
1193 /**
1194 * sa1111_pll_clock - return the current PLL clock frequency.
1195 * @sadev: SA1111 function block
1196 *
1197 * BUG: we should look at SKCR. We also blindly believe that
1198 * the chip is being fed with the 3.6864MHz clock.
1199 *
1200 * Returns the PLL clock in Hz.
1201 */
sa1111_pll_clock(struct sa1111_dev * sadev)1202 unsigned int sa1111_pll_clock(struct sa1111_dev *sadev)
1203 {
1204 struct sa1111 *sachip = sa1111_chip_driver(sadev);
1205
1206 return __sa1111_pll_clock(sachip);
1207 }
1208 EXPORT_SYMBOL(sa1111_pll_clock);
1209
1210 /**
1211 * sa1111_select_audio_mode - select I2S or AC link mode
1212 * @sadev: SA1111 function block
1213 * @mode: One of %SA1111_AUDIO_ACLINK or %SA1111_AUDIO_I2S
1214 *
1215 * Frob the SKCR to select AC Link mode or I2S mode for
1216 * the audio block.
1217 */
sa1111_select_audio_mode(struct sa1111_dev * sadev,int mode)1218 void sa1111_select_audio_mode(struct sa1111_dev *sadev, int mode)
1219 {
1220 struct sa1111 *sachip = sa1111_chip_driver(sadev);
1221 unsigned long flags;
1222 unsigned int val;
1223
1224 spin_lock_irqsave(&sachip->lock, flags);
1225
1226 val = readl_relaxed(sachip->base + SA1111_SKCR);
1227 if (mode == SA1111_AUDIO_I2S) {
1228 val &= ~SKCR_SELAC;
1229 } else {
1230 val |= SKCR_SELAC;
1231 }
1232 writel_relaxed(val, sachip->base + SA1111_SKCR);
1233
1234 spin_unlock_irqrestore(&sachip->lock, flags);
1235 }
1236 EXPORT_SYMBOL(sa1111_select_audio_mode);
1237
1238 /**
1239 * sa1111_set_audio_rate - set the audio sample rate
1240 * @sadev: SA1111 SAC function block
1241 * @rate: sample rate to select
1242 */
sa1111_set_audio_rate(struct sa1111_dev * sadev,int rate)1243 int sa1111_set_audio_rate(struct sa1111_dev *sadev, int rate)
1244 {
1245 struct sa1111 *sachip = sa1111_chip_driver(sadev);
1246 unsigned int div;
1247
1248 if (sadev->devid != SA1111_DEVID_SAC)
1249 return -EINVAL;
1250
1251 div = (__sa1111_pll_clock(sachip) / 256 + rate / 2) / rate;
1252 if (div == 0)
1253 div = 1;
1254 if (div > 128)
1255 div = 128;
1256
1257 writel_relaxed(div - 1, sachip->base + SA1111_SKAUD);
1258
1259 return 0;
1260 }
1261 EXPORT_SYMBOL(sa1111_set_audio_rate);
1262
1263 /**
1264 * sa1111_get_audio_rate - get the audio sample rate
1265 * @sadev: SA1111 SAC function block device
1266 */
sa1111_get_audio_rate(struct sa1111_dev * sadev)1267 int sa1111_get_audio_rate(struct sa1111_dev *sadev)
1268 {
1269 struct sa1111 *sachip = sa1111_chip_driver(sadev);
1270 unsigned long div;
1271
1272 if (sadev->devid != SA1111_DEVID_SAC)
1273 return -EINVAL;
1274
1275 div = readl_relaxed(sachip->base + SA1111_SKAUD) + 1;
1276
1277 return __sa1111_pll_clock(sachip) / (256 * div);
1278 }
1279 EXPORT_SYMBOL(sa1111_get_audio_rate);
1280
1281 /*
1282 * Individual device operations.
1283 */
1284
1285 /**
1286 * sa1111_enable_device - enable an on-chip SA1111 function block
1287 * @sadev: SA1111 function block device to enable
1288 */
sa1111_enable_device(struct sa1111_dev * sadev)1289 int sa1111_enable_device(struct sa1111_dev *sadev)
1290 {
1291 struct sa1111 *sachip = sa1111_chip_driver(sadev);
1292 unsigned long flags;
1293 unsigned int val;
1294 int ret = 0;
1295
1296 if (sachip->pdata && sachip->pdata->enable)
1297 ret = sachip->pdata->enable(sachip->pdata->data, sadev->devid);
1298
1299 if (ret == 0) {
1300 spin_lock_irqsave(&sachip->lock, flags);
1301 val = readl_relaxed(sachip->base + SA1111_SKPCR);
1302 writel_relaxed(val | sadev->skpcr_mask, sachip->base + SA1111_SKPCR);
1303 spin_unlock_irqrestore(&sachip->lock, flags);
1304 }
1305 return ret;
1306 }
1307 EXPORT_SYMBOL(sa1111_enable_device);
1308
1309 /**
1310 * sa1111_disable_device - disable an on-chip SA1111 function block
1311 * @sadev: SA1111 function block device to disable
1312 */
sa1111_disable_device(struct sa1111_dev * sadev)1313 void sa1111_disable_device(struct sa1111_dev *sadev)
1314 {
1315 struct sa1111 *sachip = sa1111_chip_driver(sadev);
1316 unsigned long flags;
1317 unsigned int val;
1318
1319 spin_lock_irqsave(&sachip->lock, flags);
1320 val = readl_relaxed(sachip->base + SA1111_SKPCR);
1321 writel_relaxed(val & ~sadev->skpcr_mask, sachip->base + SA1111_SKPCR);
1322 spin_unlock_irqrestore(&sachip->lock, flags);
1323
1324 if (sachip->pdata && sachip->pdata->disable)
1325 sachip->pdata->disable(sachip->pdata->data, sadev->devid);
1326 }
1327 EXPORT_SYMBOL(sa1111_disable_device);
1328
sa1111_get_irq(struct sa1111_dev * sadev,unsigned num)1329 int sa1111_get_irq(struct sa1111_dev *sadev, unsigned num)
1330 {
1331 struct sa1111 *sachip = sa1111_chip_driver(sadev);
1332 if (num >= ARRAY_SIZE(sadev->hwirq))
1333 return -EINVAL;
1334 return sa1111_map_irq(sachip, sadev->hwirq[num]);
1335 }
1336 EXPORT_SYMBOL_GPL(sa1111_get_irq);
1337
1338 /*
1339 * SA1111 "Register Access Bus."
1340 *
1341 * We model this as a regular bus type, and hang devices directly
1342 * off this.
1343 */
sa1111_match(struct device * _dev,const struct device_driver * _drv)1344 static int sa1111_match(struct device *_dev, const struct device_driver *_drv)
1345 {
1346 struct sa1111_dev *dev = to_sa1111_device(_dev);
1347 const struct sa1111_driver *drv = SA1111_DRV(_drv);
1348
1349 return !!(dev->devid & drv->devid);
1350 }
1351
sa1111_bus_probe(struct device * dev)1352 static int sa1111_bus_probe(struct device *dev)
1353 {
1354 struct sa1111_dev *sadev = to_sa1111_device(dev);
1355 struct sa1111_driver *drv = SA1111_DRV(dev->driver);
1356 int ret = -ENODEV;
1357
1358 if (drv->probe)
1359 ret = drv->probe(sadev);
1360 return ret;
1361 }
1362
sa1111_bus_remove(struct device * dev)1363 static void sa1111_bus_remove(struct device *dev)
1364 {
1365 struct sa1111_dev *sadev = to_sa1111_device(dev);
1366 struct sa1111_driver *drv = SA1111_DRV(dev->driver);
1367
1368 if (drv->remove)
1369 drv->remove(sadev);
1370 }
1371
1372 struct bus_type sa1111_bus_type = {
1373 .name = "sa1111-rab",
1374 .match = sa1111_match,
1375 .probe = sa1111_bus_probe,
1376 .remove = sa1111_bus_remove,
1377 };
1378 EXPORT_SYMBOL(sa1111_bus_type);
1379
sa1111_driver_register(struct sa1111_driver * driver)1380 int sa1111_driver_register(struct sa1111_driver *driver)
1381 {
1382 driver->drv.bus = &sa1111_bus_type;
1383 return driver_register(&driver->drv);
1384 }
1385 EXPORT_SYMBOL(sa1111_driver_register);
1386
sa1111_driver_unregister(struct sa1111_driver * driver)1387 void sa1111_driver_unregister(struct sa1111_driver *driver)
1388 {
1389 driver_unregister(&driver->drv);
1390 }
1391 EXPORT_SYMBOL(sa1111_driver_unregister);
1392
sa1111_init(void)1393 static int __init sa1111_init(void)
1394 {
1395 int ret = bus_register(&sa1111_bus_type);
1396 if (ret == 0)
1397 platform_driver_register(&sa1111_device_driver);
1398 return ret;
1399 }
1400
sa1111_exit(void)1401 static void __exit sa1111_exit(void)
1402 {
1403 platform_driver_unregister(&sa1111_device_driver);
1404 bus_unregister(&sa1111_bus_type);
1405 }
1406
1407 subsys_initcall(sa1111_init);
1408 module_exit(sa1111_exit);
1409
1410 MODULE_DESCRIPTION("Intel Corporation SA1111 core driver");
1411 MODULE_LICENSE("GPL");
1412