xref: /linux/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi (revision 115e74a29b530d121891238e9551c4bcdf7b04b5)
1// SPDX-License-Identifier: GPL-2.0-only OR MIT
2/*
3 * Device Tree Source for J784S4 and J742S2 SoC Family Main Domain peripherals
4 *
5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8#include <dt-bindings/mux/mux.h>
9#include <dt-bindings/phy/phy.h>
10#include <dt-bindings/phy/phy-ti.h>
11
12#include "k3-serdes.h"
13
14/ {
15	serdes_refclk: clock-serdes {
16		#clock-cells = <0>;
17		compatible = "fixed-clock";
18		/* To be enabled when serdes_wiz* is functional */
19		status = "disabled";
20	};
21};
22
23&cbass_main {
24	/*
25	 * MSMC is configured by bootloaders and a runtime fixup is done in the
26	 * DT for this node
27	 */
28	msmc_ram: sram@70000000 {
29		compatible = "mmio-sram";
30		reg = <0x00 0x70000000 0x00 0x800000>;
31		#address-cells = <1>;
32		#size-cells = <1>;
33		ranges = <0x00 0x00 0x70000000 0x800000>;
34
35		atf-sram@0 {
36			reg = <0x00 0x20000>;
37		};
38
39		tifs-sram@1f0000 {
40			reg = <0x1f0000 0x10000>;
41		};
42
43		l3cache-sram@200000 {
44			reg = <0x200000 0x200000>;
45		};
46	};
47
48	scm_conf: bus@100000 {
49		compatible = "simple-bus";
50		reg = <0x00 0x00100000 0x00 0x1c000>;
51		#address-cells = <1>;
52		#size-cells = <1>;
53		ranges = <0x00 0x00 0x00100000 0x1c000>;
54
55		cpsw1_phy_gmii_sel: phy@4034 {
56			compatible = "ti,am654-phy-gmii-sel";
57			reg = <0x4034 0x4>;
58			#phy-cells = <1>;
59		};
60
61		cpsw0_phy_gmii_sel: phy@4044 {
62			compatible = "ti,j784s4-cpsw9g-phy-gmii-sel";
63			reg = <0x4044 0x20>;
64			#phy-cells = <1>;
65			ti,qsgmii-main-ports = <7>, <7>;
66		};
67
68		pcie0_ctrl: pcie0-ctrl@4070 {
69			compatible = "ti,j784s4-pcie-ctrl", "syscon";
70			reg = <0x4070 0x4>;
71		};
72
73		pcie1_ctrl: pcie1-ctrl@4074 {
74			compatible = "ti,j784s4-pcie-ctrl", "syscon";
75			reg = <0x4074 0x4>;
76		};
77
78		serdes_ln_ctrl: mux-controller@4080 {
79			compatible = "reg-mux";
80			reg = <0x00004080 0x50>;
81			#mux-control-cells = <1>;
82			mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
83					<0x8 0x3>, <0xc 0x3>, /* SERDES0 lane2/3 select */
84					<0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */
85					<0x18 0x3>, <0x1c 0x3>, /* SERDES1 lane2/3 select */
86					<0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */
87					<0x28 0x3>, <0x2c 0x3>, /* SERDES2 lane2/3 select */
88					<0x40 0x3>, <0x44 0x3>, /* SERDES4 lane0/1 select */
89					<0x48 0x3>, <0x4c 0x3>; /* SERDES4 lane2/3 select */
90			idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>,
91				      <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
92				      <J784S4_SERDES0_LANE2_IP3_UNUSED>,
93				      <J784S4_SERDES0_LANE3_USB>,
94				      <J784S4_SERDES1_LANE0_PCIE0_LANE0>,
95				      <J784S4_SERDES1_LANE1_PCIE0_LANE1>,
96				      <J784S4_SERDES1_LANE2_PCIE0_LANE2>,
97				      <J784S4_SERDES1_LANE3_PCIE0_LANE3>,
98				      <J784S4_SERDES2_LANE0_IP2_UNUSED>,
99				      <J784S4_SERDES2_LANE1_IP2_UNUSED>,
100				      <J784S4_SERDES2_LANE2_QSGMII_LANE1>,
101				      <J784S4_SERDES2_LANE3_QSGMII_LANE2>,
102				      <J784S4_SERDES4_LANE0_EDP_LANE0>,
103				      <J784S4_SERDES4_LANE1_EDP_LANE1>,
104				      <J784S4_SERDES4_LANE2_EDP_LANE2>,
105				      <J784S4_SERDES4_LANE3_EDP_LANE3>;
106		};
107
108		usb_serdes_mux: mux-controller@4000 {
109			compatible = "reg-mux";
110			reg = <0x4000 0x4>;
111			#mux-control-cells = <1>;
112			mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 3 mux */
113		};
114
115		ehrpwm_tbclk: clock-controller@4140 {
116			compatible = "ti,am654-ehrpwm-tbclk";
117			reg = <0x4140 0x18>;
118			#clock-cells = <1>;
119		};
120
121		audio_refclk1: clock@82e4 {
122			compatible = "ti,am62-audio-refclk";
123			reg = <0x82e4 0x4>;
124			clocks = <&k3_clks 157 34>;
125			assigned-clocks = <&k3_clks 157 34>;
126			assigned-clock-parents = <&k3_clks 157 63>;
127			#clock-cells = <0>;
128		};
129
130		acspcie0_proxy_ctrl: clock-controller@1a090 {
131			compatible = "ti,j784s4-acspcie-proxy-ctrl", "syscon";
132			reg = <0x1a090 0x4>;
133		};
134
135		acspcie1_proxy_ctrl: clock-controller@1a094 {
136			compatible = "ti,j784s4-acspcie-proxy-ctrl", "syscon";
137			reg = <0x1a094 0x4>;
138		};
139	};
140
141	main_ehrpwm0: pwm@3000000 {
142		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
143		reg = <0x00 0x3000000 0x00 0x100>;
144		clocks = <&ehrpwm_tbclk 0>, <&k3_clks 219 0>;
145		clock-names = "tbclk", "fck";
146		power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>;
147		#pwm-cells = <3>;
148		status = "disabled";
149	};
150
151	main_ehrpwm1: pwm@3010000 {
152		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
153		reg = <0x00 0x3010000 0x00 0x100>;
154		clocks = <&ehrpwm_tbclk 1>, <&k3_clks 220 0>;
155		clock-names = "tbclk", "fck";
156		power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>;
157		#pwm-cells = <3>;
158		status = "disabled";
159	};
160
161	main_ehrpwm2: pwm@3020000 {
162		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
163		reg = <0x00 0x3020000 0x00 0x100>;
164		clocks = <&ehrpwm_tbclk 2>, <&k3_clks 221 0>;
165		clock-names = "tbclk", "fck";
166		power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>;
167		#pwm-cells = <3>;
168		status = "disabled";
169	};
170
171	main_ehrpwm3: pwm@3030000 {
172		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
173		reg = <0x00 0x3030000 0x00 0x100>;
174		clocks = <&ehrpwm_tbclk 3>, <&k3_clks 222 0>;
175		clock-names = "tbclk", "fck";
176		power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>;
177		#pwm-cells = <3>;
178		status = "disabled";
179	};
180
181	main_ehrpwm4: pwm@3040000 {
182		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
183		reg = <0x00 0x3040000 0x00 0x100>;
184		clocks = <&ehrpwm_tbclk 4>, <&k3_clks 223 0>;
185		clock-names = "tbclk", "fck";
186		power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>;
187		#pwm-cells = <3>;
188		status = "disabled";
189	};
190
191	main_ehrpwm5: pwm@3050000 {
192		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
193		reg = <0x00 0x3050000 0x00 0x100>;
194		clocks = <&ehrpwm_tbclk 5>, <&k3_clks 224 0>;
195		clock-names = "tbclk", "fck";
196		power-domains = <&k3_pds 224 TI_SCI_PD_EXCLUSIVE>;
197		#pwm-cells = <3>;
198		status = "disabled";
199	};
200
201	gic500: interrupt-controller@1800000 {
202		compatible = "arm,gic-v3";
203		#address-cells = <2>;
204		#size-cells = <2>;
205		ranges;
206		#interrupt-cells = <3>;
207		interrupt-controller;
208		reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
209		      <0x00 0x01900000 0x00 0x100000>, /* GICR */
210		      <0x00 0x6f000000 0x00 0x2000>,   /* GICC */
211		      <0x00 0x6f010000 0x00 0x1000>,   /* GICH */
212		      <0x00 0x6f020000 0x00 0x2000>;   /* GICV */
213
214		/* vcpumntirq: virtual CPU interface maintenance interrupt */
215		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
216
217		gic_its: msi-controller@1820000 {
218			compatible = "arm,gic-v3-its";
219			reg = <0x00 0x01820000 0x00 0x10000>;
220			socionext,synquacer-pre-its = <0x1000000 0x400000>;
221			msi-controller;
222			#msi-cells = <1>;
223		};
224	};
225
226	main_gpio_intr: interrupt-controller@a00000 {
227		compatible = "ti,sci-intr";
228		reg = <0x00 0x00a00000 0x00 0x800>;
229		ti,intr-trigger-type = <1>;
230		interrupt-controller;
231		interrupt-parent = <&gic500>;
232		#interrupt-cells = <1>;
233		ti,sci = <&sms>;
234		ti,sci-dev-id = <10>;
235		ti,interrupt-ranges = <8 392 56>;
236	};
237
238	main_pmx0: pinctrl@11c000 {
239		compatible = "ti,j7200-padconf", "pinctrl-single";
240		/* Proxy 0 addressing */
241		reg = <0x00 0x11c000 0x00 0x120>;
242		#pinctrl-cells = <1>;
243		pinctrl-single,register-width = <32>;
244		pinctrl-single,function-mask = <0xffffffff>;
245	};
246
247	/* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
248	main_timerio_input: pinctrl@104200 {
249		compatible = "ti,j7200-padconf", "pinctrl-single";
250		reg = <0x00 0x104200 0x00 0x50>;
251		#pinctrl-cells = <1>;
252		pinctrl-single,register-width = <32>;
253		pinctrl-single,function-mask = <0x00000007>;
254	};
255
256	/* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
257	main_timerio_output: pinctrl@104280 {
258		compatible = "ti,j7200-padconf", "pinctrl-single";
259		reg = <0x00 0x104280 0x00 0x20>;
260		#pinctrl-cells = <1>;
261		pinctrl-single,register-width = <32>;
262		pinctrl-single,function-mask = <0x0000001f>;
263	};
264
265	main_crypto: crypto@4e00000 {
266		compatible = "ti,j721e-sa2ul";
267		reg = <0x00 0x4e00000 0x00 0x1200>;
268		power-domains = <&k3_pds 369 TI_SCI_PD_EXCLUSIVE>;
269		#address-cells = <2>;
270		#size-cells = <2>;
271		ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>;
272
273		dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>,
274				<&main_udmap 0x4a41>;
275		dma-names = "tx", "rx1", "rx2";
276
277		rng: rng@4e10000 {
278			compatible = "inside-secure,safexcel-eip76";
279			reg = <0x00 0x4e10000 0x00 0x7d>;
280			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
281		};
282	};
283
284	main_timer0: timer@2400000 {
285		compatible = "ti,am654-timer";
286		reg = <0x00 0x2400000 0x00 0x400>;
287		interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
288		clocks = <&k3_clks 97 2>;
289		clock-names = "fck";
290		assigned-clocks = <&k3_clks 97 2>;
291		assigned-clock-parents = <&k3_clks 97 3>;
292		power-domains = <&k3_pds 97 TI_SCI_PD_EXCLUSIVE>;
293		ti,timer-pwm;
294	};
295
296	main_timer1: timer@2410000 {
297		compatible = "ti,am654-timer";
298		reg = <0x00 0x2410000 0x00 0x400>;
299		interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
300		clocks = <&k3_clks 98 2>;
301		clock-names = "fck";
302		assigned-clocks = <&k3_clks 98 2>;
303		assigned-clock-parents = <&k3_clks 98 3>;
304		power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
305		ti,timer-pwm;
306	};
307
308	main_timer2: timer@2420000 {
309		compatible = "ti,am654-timer";
310		reg = <0x00 0x2420000 0x00 0x400>;
311		interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
312		clocks = <&k3_clks 99 2>;
313		clock-names = "fck";
314		assigned-clocks = <&k3_clks 99 2>;
315		assigned-clock-parents = <&k3_clks 99 3>;
316		power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>;
317		ti,timer-pwm;
318	};
319
320	main_timer3: timer@2430000 {
321		compatible = "ti,am654-timer";
322		reg = <0x00 0x2430000 0x00 0x400>;
323		interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
324		clocks = <&k3_clks 100 2>;
325		clock-names = "fck";
326		assigned-clocks = <&k3_clks 100 2>;
327		assigned-clock-parents = <&k3_clks 100 3>;
328		power-domains = <&k3_pds 100 TI_SCI_PD_EXCLUSIVE>;
329		ti,timer-pwm;
330	};
331
332	main_timer4: timer@2440000 {
333		compatible = "ti,am654-timer";
334		reg = <0x00 0x2440000 0x00 0x400>;
335		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
336		clocks = <&k3_clks 101 2>;
337		clock-names = "fck";
338		assigned-clocks = <&k3_clks 101 2>;
339		assigned-clock-parents = <&k3_clks 101 3>;
340		power-domains = <&k3_pds 101 TI_SCI_PD_EXCLUSIVE>;
341		ti,timer-pwm;
342	};
343
344	main_timer5: timer@2450000 {
345		compatible = "ti,am654-timer";
346		reg = <0x00 0x2450000 0x00 0x400>;
347		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
348		clocks = <&k3_clks 102 2>;
349		clock-names = "fck";
350		assigned-clocks = <&k3_clks 102 2>;
351		assigned-clock-parents = <&k3_clks 102 3>;
352		power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
353		ti,timer-pwm;
354	};
355
356	main_timer6: timer@2460000 {
357		compatible = "ti,am654-timer";
358		reg = <0x00 0x2460000 0x00 0x400>;
359		interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
360		clocks = <&k3_clks 103 2>;
361		clock-names = "fck";
362		assigned-clocks = <&k3_clks 103 2>;
363		assigned-clock-parents = <&k3_clks 103 3>;
364		power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
365		ti,timer-pwm;
366	};
367
368	main_timer7: timer@2470000 {
369		compatible = "ti,am654-timer";
370		reg = <0x00 0x2470000 0x00 0x400>;
371		interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
372		clocks = <&k3_clks 104 2>;
373		clock-names = "fck";
374		assigned-clocks = <&k3_clks 104 2>;
375		assigned-clock-parents = <&k3_clks 104 3>;
376		power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
377		ti,timer-pwm;
378	};
379
380	main_timer8: timer@2480000 {
381		compatible = "ti,am654-timer";
382		reg = <0x00 0x2480000 0x00 0x400>;
383		interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
384		clocks = <&k3_clks 105 2>;
385		clock-names = "fck";
386		assigned-clocks = <&k3_clks 105 2>;
387		assigned-clock-parents = <&k3_clks 105 3>;
388		power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
389		ti,timer-pwm;
390	};
391
392	main_timer9: timer@2490000 {
393		compatible = "ti,am654-timer";
394		reg = <0x00 0x2490000 0x00 0x400>;
395		interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
396		clocks = <&k3_clks 106 2>;
397		clock-names = "fck";
398		assigned-clocks = <&k3_clks 106 2>;
399		assigned-clock-parents = <&k3_clks 106 3>;
400		power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
401		ti,timer-pwm;
402	};
403
404	main_timer10: timer@24a0000 {
405		compatible = "ti,am654-timer";
406		reg = <0x00 0x24a0000 0x00 0x400>;
407		interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
408		clocks = <&k3_clks 107 2>;
409		clock-names = "fck";
410		assigned-clocks = <&k3_clks 107 2>;
411		assigned-clock-parents = <&k3_clks 107 3>;
412		power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
413		ti,timer-pwm;
414	};
415
416	main_timer11: timer@24b0000 {
417		compatible = "ti,am654-timer";
418		reg = <0x00 0x24b0000 0x00 0x400>;
419		interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
420		clocks = <&k3_clks 108 2>;
421		clock-names = "fck";
422		assigned-clocks = <&k3_clks 108 2>;
423		assigned-clock-parents = <&k3_clks 108 3>;
424		power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>;
425		ti,timer-pwm;
426	};
427
428	main_timer12: timer@24c0000 {
429		compatible = "ti,am654-timer";
430		reg = <0x00 0x24c0000 0x00 0x400>;
431		interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
432		clocks = <&k3_clks 109 2>;
433		clock-names = "fck";
434		assigned-clocks = <&k3_clks 109 2>;
435		assigned-clock-parents = <&k3_clks 109 3>;
436		power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
437		ti,timer-pwm;
438	};
439
440	main_timer13: timer@24d0000 {
441		compatible = "ti,am654-timer";
442		reg = <0x00 0x24d0000 0x00 0x400>;
443		interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
444		clocks = <&k3_clks 110 2>;
445		clock-names = "fck";
446		assigned-clocks = <&k3_clks 110 2>;
447		assigned-clock-parents = <&k3_clks 110 3>;
448		power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
449		ti,timer-pwm;
450	};
451
452	main_timer14: timer@24e0000 {
453		compatible = "ti,am654-timer";
454		reg = <0x00 0x24e0000 0x00 0x400>;
455		interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
456		clocks = <&k3_clks 111 2>;
457		clock-names = "fck";
458		assigned-clocks = <&k3_clks 111 2>;
459		assigned-clock-parents = <&k3_clks 111 3>;
460		power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
461		ti,timer-pwm;
462	};
463
464	main_timer15: timer@24f0000 {
465		compatible = "ti,am654-timer";
466		reg = <0x00 0x24f0000 0x00 0x400>;
467		interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
468		clocks = <&k3_clks 112 2>;
469		clock-names = "fck";
470		assigned-clocks = <&k3_clks 112 2>;
471		assigned-clock-parents = <&k3_clks 112 3>;
472		power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
473		ti,timer-pwm;
474	};
475
476	main_timer16: timer@2500000 {
477		compatible = "ti,am654-timer";
478		reg = <0x00 0x2500000 0x00 0x400>;
479		interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
480		clocks = <&k3_clks 113 2>;
481		clock-names = "fck";
482		assigned-clocks = <&k3_clks 113 2>;
483		assigned-clock-parents = <&k3_clks 113 3>;
484		power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
485		ti,timer-pwm;
486	};
487
488	main_timer17: timer@2510000 {
489		compatible = "ti,am654-timer";
490		reg = <0x00 0x2510000 0x00 0x400>;
491		interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
492		clocks = <&k3_clks 114 2>;
493		clock-names = "fck";
494		assigned-clocks = <&k3_clks 114 2>;
495		assigned-clock-parents = <&k3_clks 114 3>;
496		power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
497		ti,timer-pwm;
498	};
499
500	main_timer18: timer@2520000 {
501		compatible = "ti,am654-timer";
502		reg = <0x00 0x2520000 0x00 0x400>;
503		interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
504		clocks = <&k3_clks 115 2>;
505		clock-names = "fck";
506		assigned-clocks = <&k3_clks 115 2>;
507		assigned-clock-parents = <&k3_clks 115 3>;
508		power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
509		ti,timer-pwm;
510	};
511
512	main_timer19: timer@2530000 {
513		compatible = "ti,am654-timer";
514		reg = <0x00 0x2530000 0x00 0x400>;
515		interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
516		clocks = <&k3_clks 116 2>;
517		clock-names = "fck";
518		assigned-clocks = <&k3_clks 116 2>;
519		assigned-clock-parents = <&k3_clks 116 3>;
520		power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>;
521		ti,timer-pwm;
522	};
523
524	main_uart0: serial@2800000 {
525		compatible = "ti,j721e-uart", "ti,am654-uart";
526		reg = <0x00 0x02800000 0x00 0x200>;
527		interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
528		clocks = <&k3_clks 146 0>;
529		clock-names = "fclk";
530		power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
531		status = "disabled";
532	};
533
534	main_uart1: serial@2810000 {
535		compatible = "ti,j721e-uart", "ti,am654-uart";
536		reg = <0x00 0x02810000 0x00 0x200>;
537		interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
538		clocks = <&k3_clks 388 0>;
539		clock-names = "fclk";
540		power-domains = <&k3_pds 388 TI_SCI_PD_EXCLUSIVE>;
541		status = "disabled";
542	};
543
544	main_uart2: serial@2820000 {
545		compatible = "ti,j721e-uart", "ti,am654-uart";
546		reg = <0x00 0x02820000 0x00 0x200>;
547		interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
548		clocks = <&k3_clks 389 0>;
549		clock-names = "fclk";
550		power-domains = <&k3_pds 389 TI_SCI_PD_EXCLUSIVE>;
551		status = "disabled";
552	};
553
554	main_uart3: serial@2830000 {
555		compatible = "ti,j721e-uart", "ti,am654-uart";
556		reg = <0x00 0x02830000 0x00 0x200>;
557		interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
558		clocks = <&k3_clks 390 0>;
559		clock-names = "fclk";
560		power-domains = <&k3_pds 390 TI_SCI_PD_EXCLUSIVE>;
561		status = "disabled";
562	};
563
564	main_uart4: serial@2840000 {
565		compatible = "ti,j721e-uart", "ti,am654-uart";
566		reg = <0x00 0x02840000 0x00 0x200>;
567		interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
568		clocks = <&k3_clks 391 0>;
569		clock-names = "fclk";
570		power-domains = <&k3_pds 391 TI_SCI_PD_EXCLUSIVE>;
571		status = "disabled";
572	};
573
574	main_uart5: serial@2850000 {
575		compatible = "ti,j721e-uart", "ti,am654-uart";
576		reg = <0x00 0x02850000 0x00 0x200>;
577		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
578		clocks = <&k3_clks 392 0>;
579		clock-names = "fclk";
580		power-domains = <&k3_pds 392 TI_SCI_PD_EXCLUSIVE>;
581		status = "disabled";
582	};
583
584	main_uart6: serial@2860000 {
585		compatible = "ti,j721e-uart", "ti,am654-uart";
586		reg = <0x00 0x02860000 0x00 0x200>;
587		interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
588		clocks = <&k3_clks 393 0>;
589		clock-names = "fclk";
590		power-domains = <&k3_pds 393 TI_SCI_PD_EXCLUSIVE>;
591		status = "disabled";
592	};
593
594	main_uart7: serial@2870000 {
595		compatible = "ti,j721e-uart", "ti,am654-uart";
596		reg = <0x00 0x02870000 0x00 0x200>;
597		interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
598		clocks = <&k3_clks 394 0>;
599		clock-names = "fclk";
600		power-domains = <&k3_pds 394 TI_SCI_PD_EXCLUSIVE>;
601		status = "disabled";
602	};
603
604	main_uart8: serial@2880000 {
605		compatible = "ti,j721e-uart", "ti,am654-uart";
606		reg = <0x00 0x02880000 0x00 0x200>;
607		interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
608		clocks = <&k3_clks 395 0>;
609		clock-names = "fclk";
610		power-domains = <&k3_pds 395 TI_SCI_PD_EXCLUSIVE>;
611		status = "disabled";
612	};
613
614	main_uart9: serial@2890000 {
615		compatible = "ti,j721e-uart", "ti,am654-uart";
616		reg = <0x00 0x02890000 0x00 0x200>;
617		interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
618		clocks = <&k3_clks 396 0>;
619		clock-names = "fclk";
620		power-domains = <&k3_pds 396 TI_SCI_PD_EXCLUSIVE>;
621		status = "disabled";
622	};
623
624	main_gpio0: gpio@600000 {
625		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
626		reg = <0x00 0x00600000 0x00 0x100>;
627		gpio-controller;
628		#gpio-cells = <2>;
629		interrupt-parent = <&main_gpio_intr>;
630		interrupts = <145>, <146>, <147>, <148>, <149>;
631		interrupt-controller;
632		#interrupt-cells = <2>;
633		ti,ngpio = <66>;
634		ti,davinci-gpio-unbanked = <0>;
635		power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
636		clocks = <&k3_clks 163 0>;
637		clock-names = "gpio";
638		status = "disabled";
639	};
640
641	main_gpio2: gpio@610000 {
642		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
643		reg = <0x00 0x00610000 0x00 0x100>;
644		gpio-controller;
645		#gpio-cells = <2>;
646		interrupt-parent = <&main_gpio_intr>;
647		interrupts = <154>, <155>, <156>, <157>, <158>;
648		interrupt-controller;
649		#interrupt-cells = <2>;
650		ti,ngpio = <66>;
651		ti,davinci-gpio-unbanked = <0>;
652		power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
653		clocks = <&k3_clks 164 0>;
654		clock-names = "gpio";
655		status = "disabled";
656	};
657
658	main_gpio4: gpio@620000 {
659		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
660		reg = <0x00 0x00620000 0x00 0x100>;
661		gpio-controller;
662		#gpio-cells = <2>;
663		interrupt-parent = <&main_gpio_intr>;
664		interrupts = <163>, <164>, <165>, <166>, <167>;
665		interrupt-controller;
666		#interrupt-cells = <2>;
667		ti,ngpio = <66>;
668		ti,davinci-gpio-unbanked = <0>;
669		power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
670		clocks = <&k3_clks 165 0>;
671		clock-names = "gpio";
672		status = "disabled";
673	};
674
675	main_gpio6: gpio@630000 {
676		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
677		reg = <0x00 0x00630000 0x00 0x100>;
678		gpio-controller;
679		#gpio-cells = <2>;
680		interrupt-parent = <&main_gpio_intr>;
681		interrupts = <172>, <173>, <174>, <175>, <176>;
682		interrupt-controller;
683		#interrupt-cells = <2>;
684		ti,ngpio = <66>;
685		ti,davinci-gpio-unbanked = <0>;
686		power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
687		clocks = <&k3_clks 166 0>;
688		clock-names = "gpio";
689		status = "disabled";
690	};
691
692	usbss0: usb@4104000 {
693		bootph-all;
694		compatible = "ti,j721e-usb";
695		reg = <0x00 0x4104000 0x00 0x100>;
696		dma-coherent;
697		power-domains = <&k3_pds 398 TI_SCI_PD_EXCLUSIVE>;
698		clocks = <&k3_clks 398 21>, <&k3_clks 398 2>;
699		clock-names = "ref", "lpm";
700		assigned-clocks = <&k3_clks 398 21>;    /* USB2_REFCLK */
701		assigned-clock-parents = <&k3_clks 398 22>; /* HFOSC0 */
702		#address-cells = <2>;
703		#size-cells = <2>;
704		ranges;
705
706		status = "disabled"; /* Needs lane config */
707
708		usb0: usb@6000000 {
709			bootph-all;
710			compatible = "cdns,usb3";
711			reg = <0x00 0x6000000 0x00 0x10000>,
712			      <0x00 0x6010000 0x00 0x10000>,
713			      <0x00 0x6020000 0x00 0x10000>;
714			reg-names = "otg", "xhci", "dev";
715			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,  /* irq.0 */
716				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
717				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
718			interrupt-names = "host",
719					  "peripheral",
720					  "otg";
721		};
722	};
723
724	main_i2c0: i2c@2000000 {
725		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
726		reg = <0x00 0x02000000 0x00 0x100>;
727		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
728		#address-cells = <1>;
729		#size-cells = <0>;
730		clocks = <&k3_clks 270 2>;
731		clock-names = "fck";
732		power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>;
733		status = "disabled";
734	};
735
736	main_i2c1: i2c@2010000 {
737		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
738		reg = <0x00 0x02010000 0x00 0x100>;
739		interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
740		#address-cells = <1>;
741		#size-cells = <0>;
742		clocks = <&k3_clks 271 2>;
743		clock-names = "fck";
744		power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>;
745		status = "disabled";
746	};
747
748	main_i2c2: i2c@2020000 {
749		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
750		reg = <0x00 0x02020000 0x00 0x100>;
751		interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
752		#address-cells = <1>;
753		#size-cells = <0>;
754		clocks = <&k3_clks 272 2>;
755		clock-names = "fck";
756		power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>;
757		status = "disabled";
758	};
759
760	main_i2c3: i2c@2030000 {
761		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
762		reg = <0x00 0x02030000 0x00 0x100>;
763		interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
764		#address-cells = <1>;
765		#size-cells = <0>;
766		clocks = <&k3_clks 273 2>;
767		clock-names = "fck";
768		power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>;
769		status = "disabled";
770	};
771
772	main_i2c4: i2c@2040000 {
773		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
774		reg = <0x00 0x02040000 0x00 0x100>;
775		interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
776		#address-cells = <1>;
777		#size-cells = <0>;
778		clocks = <&k3_clks 274 2>;
779		clock-names = "fck";
780		power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>;
781		status = "disabled";
782	};
783
784	main_i2c5: i2c@2050000 {
785		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
786		reg = <0x00 0x02050000 0x00 0x100>;
787		interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
788		#address-cells = <1>;
789		#size-cells = <0>;
790		clocks = <&k3_clks 275 2>;
791		clock-names = "fck";
792		power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>;
793		status = "disabled";
794	};
795
796	main_i2c6: i2c@2060000 {
797		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
798		reg = <0x00 0x02060000 0x00 0x100>;
799		interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
800		#address-cells = <1>;
801		#size-cells = <0>;
802		clocks = <&k3_clks 276 2>;
803		clock-names = "fck";
804		power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
805		status = "disabled";
806	};
807
808	ti_csi2rx0: ticsi2rx@4500000 {
809		compatible = "ti,j721e-csi2rx-shim";
810		reg = <0x00 0x04500000 0x00 0x00001000>;
811		ranges;
812		#address-cells = <2>;
813		#size-cells = <2>;
814		dmas = <&main_bcdma_csi 0 0x4940 0>;
815		dma-names = "rx0";
816		power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>;
817		status = "disabled";
818
819		cdns_csi2rx0: csi-bridge@4504000 {
820			compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
821			reg = <0x00 0x04504000 0x00 0x00001000>;
822			clocks = <&k3_clks 72 2>, <&k3_clks 72 0>, <&k3_clks 72 2>,
823				<&k3_clks 72 2>, <&k3_clks 72 3>, <&k3_clks 72 3>;
824			clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
825				"pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
826			phys = <&dphy0>;
827			phy-names = "dphy";
828
829			ports {
830				#address-cells = <1>;
831				#size-cells = <0>;
832
833				csi0_port0: port@0 {
834					reg = <0>;
835					status = "disabled";
836				};
837
838				csi0_port1: port@1 {
839					reg = <1>;
840					status = "disabled";
841				};
842
843				csi0_port2: port@2 {
844					reg = <2>;
845					status = "disabled";
846				};
847
848				csi0_port3: port@3 {
849					reg = <3>;
850					status = "disabled";
851				};
852
853				csi0_port4: port@4 {
854					reg = <4>;
855					status = "disabled";
856				};
857			};
858		};
859	};
860
861	ti_csi2rx1: ticsi2rx@4510000 {
862		compatible = "ti,j721e-csi2rx-shim";
863		reg = <0x00 0x04510000 0x00 0x1000>;
864		ranges;
865		#address-cells = <2>;
866		#size-cells = <2>;
867		dmas = <&main_bcdma_csi 0 0x4960 0>;
868		dma-names = "rx0";
869		power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>;
870		status = "disabled";
871
872		cdns_csi2rx1: csi-bridge@4514000 {
873			compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
874			reg = <0x00 0x04514000 0x00 0x00001000>;
875			clocks = <&k3_clks 73 2>, <&k3_clks 73 0>, <&k3_clks 73 2>,
876				<&k3_clks 73 2>, <&k3_clks 73 3>, <&k3_clks 73 3>;
877			clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
878				"pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
879			phys = <&dphy1>;
880			phy-names = "dphy";
881			ports {
882				#address-cells = <1>;
883				#size-cells = <0>;
884
885				csi1_port0: port@0 {
886					reg = <0>;
887					status = "disabled";
888				};
889
890				csi1_port1: port@1 {
891					reg = <1>;
892					status = "disabled";
893				};
894
895				csi1_port2: port@2 {
896					reg = <2>;
897					status = "disabled";
898				};
899
900				csi1_port3: port@3 {
901					reg = <3>;
902					status = "disabled";
903				};
904
905				csi1_port4: port@4 {
906					reg = <4>;
907					status = "disabled";
908				};
909			};
910		};
911	};
912
913	ti_csi2rx2: ticsi2rx@4520000 {
914		compatible = "ti,j721e-csi2rx-shim";
915		reg = <0x00 0x04520000 0x00 0x00001000>;
916		ranges;
917		#address-cells = <2>;
918		#size-cells = <2>;
919		dmas = <&main_bcdma_csi 0 0x4980 0>;
920		dma-names = "rx0";
921		power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>;
922		status = "disabled";
923
924		cdns_csi2rx2: csi-bridge@4524000 {
925			compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
926			reg = <0x00 0x04524000 0x00 0x00001000>;
927			clocks = <&k3_clks 74 2>, <&k3_clks 74 0>, <&k3_clks 74 2>,
928				<&k3_clks 74 2>, <&k3_clks 74 3>, <&k3_clks 74 3>;
929			clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
930				"pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
931			phys = <&dphy2>;
932			phy-names = "dphy";
933
934			ports {
935				#address-cells = <1>;
936				#size-cells = <0>;
937
938				csi2_port0: port@0 {
939					reg = <0>;
940					status = "disabled";
941				};
942
943				csi2_port1: port@1 {
944					reg = <1>;
945					status = "disabled";
946				};
947
948				csi2_port2: port@2 {
949					reg = <2>;
950					status = "disabled";
951				};
952
953				csi2_port3: port@3 {
954					reg = <3>;
955					status = "disabled";
956				};
957
958				csi2_port4: port@4 {
959					reg = <4>;
960					status = "disabled";
961				};
962			};
963		};
964	};
965
966	dphy0: phy@4580000 {
967		compatible = "cdns,dphy-rx";
968		reg = <0x00 0x04580000 0x00 0x00001100>;
969		#phy-cells = <0>;
970		power-domains = <&k3_pds 212 TI_SCI_PD_EXCLUSIVE>;
971		status = "disabled";
972	};
973
974	dphy1: phy@4590000 {
975		compatible = "cdns,dphy-rx";
976		reg = <0x00 0x04590000 0x00 0x00001100>;
977		#phy-cells = <0>;
978		power-domains = <&k3_pds 213 TI_SCI_PD_EXCLUSIVE>;
979		status = "disabled";
980	};
981
982	dphy2: phy@45a0000 {
983		compatible = "cdns,dphy-rx";
984		reg = <0x00 0x045a0000 0x00 0x00001100>;
985		#phy-cells = <0>;
986		power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>;
987		status = "disabled";
988	};
989
990	vpu0: video-codec@4210000 {
991		compatible = "ti,j721s2-wave521c", "cnm,wave521c";
992		reg = <0x00 0x4210000 0x00 0x10000>;
993		interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
994		clocks = <&k3_clks 241 2>;
995		power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
996	};
997
998	vpu1: video-codec@4220000 {
999		compatible = "ti,j721s2-wave521c", "cnm,wave521c";
1000		reg = <0x00 0x4220000 0x00 0x10000>;
1001		interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
1002		clocks = <&k3_clks 242 2>;
1003		power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
1004	};
1005
1006	main_sdhci0: mmc@4f80000 {
1007		compatible = "ti,j721e-sdhci-8bit";
1008		reg = <0x00 0x04f80000 0x00 0x1000>,
1009		      <0x00 0x04f88000 0x00 0x400>;
1010		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1011		power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>;
1012		clocks = <&k3_clks 140 1>, <&k3_clks 140 2>;
1013		clock-names = "clk_ahb", "clk_xin";
1014		assigned-clocks = <&k3_clks 140 2>;
1015		assigned-clock-parents = <&k3_clks 140 3>;
1016		bus-width = <8>;
1017		ti,otap-del-sel-legacy = <0x0>;
1018		ti,otap-del-sel-mmc-hs = <0x0>;
1019		ti,otap-del-sel-ddr52 = <0x6>;
1020		ti,otap-del-sel-hs200 = <0x8>;
1021		ti,otap-del-sel-hs400 = <0x5>;
1022		ti,itap-del-sel-legacy = <0x10>;
1023		ti,itap-del-sel-mmc-hs = <0xa>;
1024		ti,strobe-sel = <0x77>;
1025		ti,clkbuf-sel = <0x7>;
1026		ti,trm-icp = <0x8>;
1027		mmc-ddr-1_8v;
1028		mmc-hs200-1_8v;
1029		mmc-hs400-1_8v;
1030		dma-coherent;
1031		status = "disabled";
1032	};
1033
1034	main_sdhci1: mmc@4fb0000 {
1035		compatible = "ti,j721e-sdhci-4bit";
1036		reg = <0x00 0x04fb0000 0x00 0x1000>,
1037		      <0x00 0x04fb8000 0x00 0x400>;
1038		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1039		power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
1040		clocks = <&k3_clks 141 3>, <&k3_clks 141 4>;
1041		clock-names = "clk_ahb", "clk_xin";
1042		assigned-clocks = <&k3_clks 141 4>;
1043		assigned-clock-parents = <&k3_clks 141 5>;
1044		bus-width = <4>;
1045		ti,otap-del-sel-legacy = <0x0>;
1046		ti,otap-del-sel-sd-hs = <0x0>;
1047		ti,otap-del-sel-sdr12 = <0xf>;
1048		ti,otap-del-sel-sdr25 = <0xf>;
1049		ti,otap-del-sel-sdr50 = <0xc>;
1050		ti,otap-del-sel-sdr104 = <0x5>;
1051		ti,otap-del-sel-ddr50 = <0xc>;
1052		ti,itap-del-sel-legacy = <0x0>;
1053		ti,itap-del-sel-sd-hs = <0x0>;
1054		ti,itap-del-sel-sdr12 = <0x0>;
1055		ti,itap-del-sel-sdr25 = <0x0>;
1056		ti,itap-del-sel-ddr50 = <0x2>;
1057		ti,clkbuf-sel = <0x7>;
1058		ti,trm-icp = <0x8>;
1059		dma-coherent;
1060		status = "disabled";
1061	};
1062
1063	pcie0_rc: pcie@2900000 {
1064		compatible = "ti,j784s4-pcie-host";
1065		reg = <0x00 0x02900000 0x00 0x1000>,
1066		      <0x00 0x02907000 0x00 0x400>,
1067		      <0x00 0x0d000000 0x00 0x00800000>,
1068		      <0x40 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */
1069		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
1070		interrupt-names = "link_state";
1071		interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
1072		device_type = "pci";
1073		ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
1074		max-link-speed = <3>;
1075		num-lanes = <4>;
1076		power-domains = <&k3_pds 332 TI_SCI_PD_EXCLUSIVE>;
1077		clocks = <&k3_clks 332 0>;
1078		clock-names = "fck";
1079		#address-cells = <3>;
1080		#size-cells = <2>;
1081		bus-range = <0x0 0xff>;
1082		vendor-id = <0x104c>;
1083		device-id = <0xb012>;
1084		msi-map = <0x0 &gic_its 0x0 0x10000>;
1085		dma-coherent;
1086		ranges = <0x01000000 0x00 0x00001000 0x40 0x00001000 0x00 0x00100000>, /* IO (1 MB) */
1087			 <0x02000000 0x00 0x00101000 0x40 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */
1088		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
1089		status = "disabled";
1090	};
1091
1092	pcie1_rc: pcie@2910000 {
1093		compatible = "ti,j784s4-pcie-host";
1094		reg = <0x00 0x02910000 0x00 0x1000>,
1095		      <0x00 0x02917000 0x00 0x400>,
1096		      <0x00 0x0d800000 0x00 0x00800000>,
1097		      <0x41 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */
1098		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
1099		interrupt-names = "link_state";
1100		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
1101		device_type = "pci";
1102		ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
1103		max-link-speed = <3>;
1104		num-lanes = <4>;
1105		power-domains = <&k3_pds 333 TI_SCI_PD_EXCLUSIVE>;
1106		clocks = <&k3_clks 333 0>;
1107		clock-names = "fck";
1108		#address-cells = <3>;
1109		#size-cells = <2>;
1110		bus-range = <0x0 0xff>;
1111		vendor-id = <0x104c>;
1112		device-id = <0xb012>;
1113		msi-map = <0x0 &gic_its 0x10000 0x10000>;
1114		dma-coherent;
1115		ranges = <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>, /* IO (1 MB) */
1116			 <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */
1117		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
1118		status = "disabled";
1119	};
1120
1121	serdes_wiz0: wiz@5060000 {
1122		compatible = "ti,j784s4-wiz-10g";
1123		#address-cells = <1>;
1124		#size-cells = <1>;
1125		power-domains = <&k3_pds 404 TI_SCI_PD_EXCLUSIVE>;
1126		clocks = <&k3_clks 404 2>, <&k3_clks 404 6>, <&serdes_refclk>, <&k3_clks 404 5>;
1127		clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
1128		assigned-clocks = <&k3_clks 404 6>;
1129		assigned-clock-parents = <&k3_clks 404 10>;
1130		num-lanes = <4>;
1131		#reset-cells = <1>;
1132		#clock-cells = <1>;
1133		ranges = <0x5060000 0x00 0x5060000 0x10000>;
1134		status = "disabled";
1135
1136		serdes0: serdes@5060000 {
1137			compatible = "ti,j721e-serdes-10g";
1138			reg = <0x05060000 0x010000>;
1139			reg-names = "torrent_phy";
1140			resets = <&serdes_wiz0 0>;
1141			reset-names = "torrent_reset";
1142			clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
1143				 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
1144			clock-names = "refclk", "phy_en_refclk";
1145			assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
1146					  <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
1147					  <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
1148			assigned-clock-parents = <&k3_clks 404 6>,
1149						 <&k3_clks 404 6>,
1150						 <&k3_clks 404 6>;
1151			#address-cells = <1>;
1152			#size-cells = <0>;
1153			#clock-cells = <1>;
1154			status = "disabled";
1155		};
1156	};
1157
1158	serdes_wiz1: wiz@5070000 {
1159		compatible = "ti,j784s4-wiz-10g";
1160		#address-cells = <1>;
1161		#size-cells = <1>;
1162		power-domains = <&k3_pds 405 TI_SCI_PD_EXCLUSIVE>;
1163		clocks = <&k3_clks 405 2>, <&k3_clks 405 6>, <&serdes_refclk>, <&k3_clks 405 5>;
1164		clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
1165		assigned-clocks = <&k3_clks 405 6>;
1166		assigned-clock-parents = <&k3_clks 405 10>;
1167		num-lanes = <4>;
1168		#reset-cells = <1>;
1169		#clock-cells = <1>;
1170		ranges = <0x05070000 0x00 0x05070000 0x10000>;
1171		status = "disabled";
1172
1173		serdes1: serdes@5070000 {
1174			compatible = "ti,j721e-serdes-10g";
1175			reg = <0x05070000 0x010000>;
1176			reg-names = "torrent_phy";
1177			resets = <&serdes_wiz1 0>;
1178			reset-names = "torrent_reset";
1179			clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
1180				 <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>;
1181			clock-names = "refclk", "phy_en_refclk";
1182			assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
1183					  <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>,
1184					  <&serdes_wiz1 TI_WIZ_REFCLK_DIG>;
1185			assigned-clock-parents = <&k3_clks 405 6>,
1186						 <&k3_clks 405 6>,
1187						 <&k3_clks 405 6>;
1188			#address-cells = <1>;
1189			#size-cells = <0>;
1190			#clock-cells = <1>;
1191			status = "disabled";
1192		};
1193	};
1194
1195	serdes_wiz4: wiz@5050000 {
1196		compatible = "ti,j784s4-wiz-10g";
1197		#address-cells = <1>;
1198		#size-cells = <1>;
1199		power-domains = <&k3_pds 407 TI_SCI_PD_EXCLUSIVE>;
1200		clocks = <&k3_clks 407 2>, <&k3_clks 407 6>, <&serdes_refclk>, <&k3_clks 407 5>;
1201		clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
1202		assigned-clocks = <&k3_clks 407 6>;
1203		assigned-clock-parents = <&k3_clks 407 10>;
1204		num-lanes = <4>;
1205		#reset-cells = <1>;
1206		#clock-cells = <1>;
1207		ranges = <0x05050000 0x00 0x05050000 0x10000>,
1208			 <0xa030a00 0x00 0xa030a00 0x40>; /* DPTX PHY */
1209		status = "disabled";
1210
1211		serdes4: serdes@5050000 {
1212			/*
1213			 * Note: we also map DPTX PHY registers as the Torrent
1214			 * needs to manage those.
1215			 */
1216			compatible = "ti,j721e-serdes-10g";
1217			reg = <0x05050000 0x010000>,
1218			      <0x0a030a00 0x40>; /* DPTX PHY */
1219			reg-names = "torrent_phy";
1220			resets = <&serdes_wiz4 0>;
1221			reset-names = "torrent_reset";
1222			clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
1223				 <&serdes_wiz4 TI_WIZ_PHY_EN_REFCLK>;
1224			clock-names = "refclk", "phy_en_refclk";
1225			assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
1226					  <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>,
1227					  <&serdes_wiz4 TI_WIZ_REFCLK_DIG>;
1228			assigned-clock-parents = <&k3_clks 407 6>,
1229						 <&k3_clks 407 6>,
1230						 <&k3_clks 407 6>;
1231			#address-cells = <1>;
1232			#size-cells = <0>;
1233			#clock-cells = <1>;
1234			status = "disabled";
1235		};
1236	};
1237
1238	main_navss: bus@30000000 {
1239		bootph-all;
1240		compatible = "simple-bus";
1241		#address-cells = <2>;
1242		#size-cells = <2>;
1243		ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
1244		ti,sci-dev-id = <280>;
1245		dma-coherent;
1246		dma-ranges;
1247
1248		main_navss_intr: interrupt-controller@310e0000 {
1249			compatible = "ti,sci-intr";
1250			reg = <0x00 0x310e0000 0x00 0x4000>;
1251			ti,intr-trigger-type = <4>;
1252			interrupt-controller;
1253			interrupt-parent = <&gic500>;
1254			#interrupt-cells = <1>;
1255			ti,sci = <&sms>;
1256			ti,sci-dev-id = <283>;
1257			ti,interrupt-ranges = <0 64 64>,
1258					      <64 448 64>,
1259					      <128 672 64>;
1260		};
1261
1262		main_udmass_inta: msi-controller@33d00000 {
1263			compatible = "ti,sci-inta";
1264			reg = <0x00 0x33d00000 0x00 0x100000>;
1265			interrupt-controller;
1266			#interrupt-cells = <0>;
1267			interrupt-parent = <&main_navss_intr>;
1268			msi-controller;
1269			ti,sci = <&sms>;
1270			ti,sci-dev-id = <321>;
1271			ti,interrupt-ranges = <0 0 256>;
1272			ti,unmapped-event-sources = <&main_bcdma_csi>;
1273		};
1274
1275		secure_proxy_main: mailbox@32c00000 {
1276			bootph-all;
1277			compatible = "ti,am654-secure-proxy";
1278			#mbox-cells = <1>;
1279			reg-names = "target_data", "rt", "scfg";
1280			reg = <0x00 0x32c00000 0x00 0x100000>,
1281			      <0x00 0x32400000 0x00 0x100000>,
1282			      <0x00 0x32800000 0x00 0x100000>;
1283			interrupt-names = "rx_011";
1284			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1285		};
1286
1287		hwspinlock: hwlock@30e00000 {
1288			compatible = "ti,am654-hwspinlock";
1289			reg = <0x00 0x30e00000 0x00 0x1000>;
1290			#hwlock-cells = <1>;
1291		};
1292
1293		mailbox0_cluster0: mailbox@31f80000 {
1294			compatible = "ti,am654-mailbox";
1295			reg = <0x00 0x31f80000 0x00 0x200>;
1296			#mbox-cells = <1>;
1297			ti,mbox-num-users = <4>;
1298			ti,mbox-num-fifos = <16>;
1299			interrupt-parent = <&main_navss_intr>;
1300			status = "disabled";
1301		};
1302
1303		mailbox0_cluster1: mailbox@31f81000 {
1304			compatible = "ti,am654-mailbox";
1305			reg = <0x00 0x31f81000 0x00 0x200>;
1306			#mbox-cells = <1>;
1307			ti,mbox-num-users = <4>;
1308			ti,mbox-num-fifos = <16>;
1309			interrupt-parent = <&main_navss_intr>;
1310			status = "disabled";
1311		};
1312
1313		mailbox0_cluster2: mailbox@31f82000 {
1314			compatible = "ti,am654-mailbox";
1315			reg = <0x00 0x31f82000 0x00 0x200>;
1316			#mbox-cells = <1>;
1317			ti,mbox-num-users = <4>;
1318			ti,mbox-num-fifos = <16>;
1319			interrupt-parent = <&main_navss_intr>;
1320			status = "disabled";
1321		};
1322
1323		mailbox0_cluster3: mailbox@31f83000 {
1324			compatible = "ti,am654-mailbox";
1325			reg = <0x00 0x31f83000 0x00 0x200>;
1326			#mbox-cells = <1>;
1327			ti,mbox-num-users = <4>;
1328			ti,mbox-num-fifos = <16>;
1329			interrupt-parent = <&main_navss_intr>;
1330			status = "disabled";
1331		};
1332
1333		mailbox0_cluster4: mailbox@31f84000 {
1334			compatible = "ti,am654-mailbox";
1335			reg = <0x00 0x31f84000 0x00 0x200>;
1336			#mbox-cells = <1>;
1337			ti,mbox-num-users = <4>;
1338			ti,mbox-num-fifos = <16>;
1339			interrupt-parent = <&main_navss_intr>;
1340			status = "disabled";
1341		};
1342
1343		mailbox0_cluster5: mailbox@31f85000 {
1344			compatible = "ti,am654-mailbox";
1345			reg = <0x00 0x31f85000 0x00 0x200>;
1346			#mbox-cells = <1>;
1347			ti,mbox-num-users = <4>;
1348			ti,mbox-num-fifos = <16>;
1349			interrupt-parent = <&main_navss_intr>;
1350			status = "disabled";
1351		};
1352
1353		mailbox0_cluster6: mailbox@31f86000 {
1354			compatible = "ti,am654-mailbox";
1355			reg = <0x00 0x31f86000 0x00 0x200>;
1356			#mbox-cells = <1>;
1357			ti,mbox-num-users = <4>;
1358			ti,mbox-num-fifos = <16>;
1359			interrupt-parent = <&main_navss_intr>;
1360			status = "disabled";
1361		};
1362
1363		mailbox0_cluster7: mailbox@31f87000 {
1364			compatible = "ti,am654-mailbox";
1365			reg = <0x00 0x31f87000 0x00 0x200>;
1366			#mbox-cells = <1>;
1367			ti,mbox-num-users = <4>;
1368			ti,mbox-num-fifos = <16>;
1369			interrupt-parent = <&main_navss_intr>;
1370			status = "disabled";
1371		};
1372
1373		mailbox0_cluster8: mailbox@31f88000 {
1374			compatible = "ti,am654-mailbox";
1375			reg = <0x00 0x31f88000 0x00 0x200>;
1376			#mbox-cells = <1>;
1377			ti,mbox-num-users = <4>;
1378			ti,mbox-num-fifos = <16>;
1379			interrupt-parent = <&main_navss_intr>;
1380			status = "disabled";
1381		};
1382
1383		mailbox0_cluster9: mailbox@31f89000 {
1384			compatible = "ti,am654-mailbox";
1385			reg = <0x00 0x31f89000 0x00 0x200>;
1386			#mbox-cells = <1>;
1387			ti,mbox-num-users = <4>;
1388			ti,mbox-num-fifos = <16>;
1389			interrupt-parent = <&main_navss_intr>;
1390			status = "disabled";
1391		};
1392
1393		mailbox0_cluster10: mailbox@31f8a000 {
1394			compatible = "ti,am654-mailbox";
1395			reg = <0x00 0x31f8a000 0x00 0x200>;
1396			#mbox-cells = <1>;
1397			ti,mbox-num-users = <4>;
1398			ti,mbox-num-fifos = <16>;
1399			interrupt-parent = <&main_navss_intr>;
1400			status = "disabled";
1401		};
1402
1403		mailbox0_cluster11: mailbox@31f8b000 {
1404			compatible = "ti,am654-mailbox";
1405			reg = <0x00 0x31f8b000 0x00 0x200>;
1406			#mbox-cells = <1>;
1407			ti,mbox-num-users = <4>;
1408			ti,mbox-num-fifos = <16>;
1409			interrupt-parent = <&main_navss_intr>;
1410			status = "disabled";
1411		};
1412
1413		mailbox1_cluster0: mailbox@31f90000 {
1414			compatible = "ti,am654-mailbox";
1415			reg = <0x00 0x31f90000 0x00 0x200>;
1416			#mbox-cells = <1>;
1417			ti,mbox-num-users = <4>;
1418			ti,mbox-num-fifos = <16>;
1419			interrupt-parent = <&main_navss_intr>;
1420			status = "disabled";
1421		};
1422
1423		mailbox1_cluster1: mailbox@31f91000 {
1424			compatible = "ti,am654-mailbox";
1425			reg = <0x00 0x31f91000 0x00 0x200>;
1426			#mbox-cells = <1>;
1427			ti,mbox-num-users = <4>;
1428			ti,mbox-num-fifos = <16>;
1429			interrupt-parent = <&main_navss_intr>;
1430			status = "disabled";
1431		};
1432
1433		mailbox1_cluster2: mailbox@31f92000 {
1434			compatible = "ti,am654-mailbox";
1435			reg = <0x00 0x31f92000 0x00 0x200>;
1436			#mbox-cells = <1>;
1437			ti,mbox-num-users = <4>;
1438			ti,mbox-num-fifos = <16>;
1439			interrupt-parent = <&main_navss_intr>;
1440			status = "disabled";
1441		};
1442
1443		mailbox1_cluster3: mailbox@31f93000 {
1444			compatible = "ti,am654-mailbox";
1445			reg = <0x00 0x31f93000 0x00 0x200>;
1446			#mbox-cells = <1>;
1447			ti,mbox-num-users = <4>;
1448			ti,mbox-num-fifos = <16>;
1449			interrupt-parent = <&main_navss_intr>;
1450			status = "disabled";
1451		};
1452
1453		mailbox1_cluster4: mailbox@31f94000 {
1454			compatible = "ti,am654-mailbox";
1455			reg = <0x00 0x31f94000 0x00 0x200>;
1456			#mbox-cells = <1>;
1457			ti,mbox-num-users = <4>;
1458			ti,mbox-num-fifos = <16>;
1459			interrupt-parent = <&main_navss_intr>;
1460			status = "disabled";
1461		};
1462
1463		mailbox1_cluster5: mailbox@31f95000 {
1464			compatible = "ti,am654-mailbox";
1465			reg = <0x00 0x31f95000 0x00 0x200>;
1466			#mbox-cells = <1>;
1467			ti,mbox-num-users = <4>;
1468			ti,mbox-num-fifos = <16>;
1469			interrupt-parent = <&main_navss_intr>;
1470			status = "disabled";
1471		};
1472
1473		mailbox1_cluster6: mailbox@31f96000 {
1474			compatible = "ti,am654-mailbox";
1475			reg = <0x00 0x31f96000 0x00 0x200>;
1476			#mbox-cells = <1>;
1477			ti,mbox-num-users = <4>;
1478			ti,mbox-num-fifos = <16>;
1479			interrupt-parent = <&main_navss_intr>;
1480			status = "disabled";
1481		};
1482
1483		mailbox1_cluster7: mailbox@31f97000 {
1484			compatible = "ti,am654-mailbox";
1485			reg = <0x00 0x31f97000 0x00 0x200>;
1486			#mbox-cells = <1>;
1487			ti,mbox-num-users = <4>;
1488			ti,mbox-num-fifos = <16>;
1489			interrupt-parent = <&main_navss_intr>;
1490			status = "disabled";
1491		};
1492
1493		mailbox1_cluster8: mailbox@31f98000 {
1494			compatible = "ti,am654-mailbox";
1495			reg = <0x00 0x31f98000 0x00 0x200>;
1496			#mbox-cells = <1>;
1497			ti,mbox-num-users = <4>;
1498			ti,mbox-num-fifos = <16>;
1499			interrupt-parent = <&main_navss_intr>;
1500			status = "disabled";
1501		};
1502
1503		mailbox1_cluster9: mailbox@31f99000 {
1504			compatible = "ti,am654-mailbox";
1505			reg = <0x00 0x31f99000 0x00 0x200>;
1506			#mbox-cells = <1>;
1507			ti,mbox-num-users = <4>;
1508			ti,mbox-num-fifos = <16>;
1509			interrupt-parent = <&main_navss_intr>;
1510			status = "disabled";
1511		};
1512
1513		mailbox1_cluster10: mailbox@31f9a000 {
1514			compatible = "ti,am654-mailbox";
1515			reg = <0x00 0x31f9a000 0x00 0x200>;
1516			#mbox-cells = <1>;
1517			ti,mbox-num-users = <4>;
1518			ti,mbox-num-fifos = <16>;
1519			interrupt-parent = <&main_navss_intr>;
1520			status = "disabled";
1521		};
1522
1523		mailbox1_cluster11: mailbox@31f9b000 {
1524			compatible = "ti,am654-mailbox";
1525			reg = <0x00 0x31f9b000 0x00 0x200>;
1526			#mbox-cells = <1>;
1527			ti,mbox-num-users = <4>;
1528			ti,mbox-num-fifos = <16>;
1529			interrupt-parent = <&main_navss_intr>;
1530			status = "disabled";
1531		};
1532
1533		main_ringacc: ringacc@3c000000 {
1534			compatible = "ti,am654-navss-ringacc";
1535			reg = <0x00 0x3c000000 0x00 0x400000>,
1536			      <0x00 0x38000000 0x00 0x400000>,
1537			      <0x00 0x31120000 0x00 0x100>,
1538			      <0x00 0x33000000 0x00 0x40000>,
1539			      <0x00 0x31080000 0x00 0x40000>;
1540			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
1541			ti,num-rings = <1024>;
1542			ti,sci-rm-range-gp-rings = <0x1>;
1543			ti,sci = <&sms>;
1544			ti,sci-dev-id = <315>;
1545			msi-parent = <&main_udmass_inta>;
1546		};
1547
1548		main_udmap: dma-controller@31150000 {
1549			compatible = "ti,j721e-navss-main-udmap";
1550			reg = <0x00 0x31150000 0x00 0x100>,
1551			      <0x00 0x34000000 0x00 0x80000>,
1552			      <0x00 0x35000000 0x00 0x200000>,
1553			      <0x00 0x30b00000 0x00 0x20000>,
1554			      <0x00 0x30c00000 0x00 0x8000>,
1555			      <0x00 0x30d00000 0x00 0x4000>;
1556			reg-names = "gcfg", "rchanrt", "tchanrt",
1557				    "tchan", "rchan", "rflow";
1558			msi-parent = <&main_udmass_inta>;
1559			#dma-cells = <1>;
1560
1561			ti,sci = <&sms>;
1562			ti,sci-dev-id = <319>;
1563			ti,ringacc = <&main_ringacc>;
1564
1565			ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
1566						<0x0f>, /* TX_HCHAN */
1567						<0x10>; /* TX_UHCHAN */
1568			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
1569						<0x0b>, /* RX_HCHAN */
1570						<0x0c>; /* RX_UHCHAN */
1571			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
1572		};
1573
1574		main_bcdma_csi: dma-controller@311a0000 {
1575			compatible = "ti,j721s2-dmss-bcdma-csi";
1576			reg = <0x00 0x311a0000 0x00 0x100>,
1577			      <0x00 0x35d00000 0x00 0x20000>,
1578			      <0x00 0x35c00000 0x00 0x10000>,
1579			      <0x00 0x35e00000 0x00 0x80000>;
1580			reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
1581			msi-parent = <&main_udmass_inta>;
1582			#dma-cells = <3>;
1583			ti,sci = <&sms>;
1584			ti,sci-dev-id = <281>;
1585			ti,sci-rm-range-rchan = <0x21>;
1586			ti,sci-rm-range-tchan = <0x22>;
1587		};
1588
1589		cpts@310d0000 {
1590			compatible = "ti,j721e-cpts";
1591			reg = <0x00 0x310d0000 0x00 0x400>;
1592			reg-names = "cpts";
1593			clocks = <&k3_clks 282 0>;
1594			clock-names = "cpts";
1595			assigned-clocks = <&k3_clks 62 3>; /* CPTS_RFT_CLK */
1596			assigned-clock-parents = <&k3_clks 62 5>; /* MAIN_0_HSDIV6_CLK */
1597			interrupts-extended = <&main_navss_intr 391>;
1598			interrupt-names = "cpts";
1599			ti,cpts-periodic-outputs = <6>;
1600			ti,cpts-ext-ts-inputs = <8>;
1601		};
1602	};
1603
1604	main_cpsw0: ethernet@c000000 {
1605		compatible = "ti,j784s4-cpswxg-nuss";
1606		reg = <0x00 0xc000000 0x00 0x200000>;
1607		reg-names = "cpsw_nuss";
1608		ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>;
1609		#address-cells = <2>;
1610		#size-cells = <2>;
1611		dma-coherent;
1612		clocks = <&k3_clks 64 0>;
1613		clock-names = "fck";
1614		power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
1615
1616		dmas = <&main_udmap 0xca00>,
1617		       <&main_udmap 0xca01>,
1618		       <&main_udmap 0xca02>,
1619		       <&main_udmap 0xca03>,
1620		       <&main_udmap 0xca04>,
1621		       <&main_udmap 0xca05>,
1622		       <&main_udmap 0xca06>,
1623		       <&main_udmap 0xca07>,
1624		       <&main_udmap 0x4a00>;
1625		dma-names = "tx0", "tx1", "tx2", "tx3",
1626			    "tx4", "tx5", "tx6", "tx7",
1627			    "rx";
1628
1629		status = "disabled";
1630
1631		ethernet-ports {
1632			#address-cells = <1>;
1633			#size-cells = <0>;
1634
1635			main_cpsw0_port1: port@1 {
1636				reg = <1>;
1637				label = "port1";
1638				ti,mac-only;
1639				status = "disabled";
1640			};
1641
1642			main_cpsw0_port2: port@2 {
1643				reg = <2>;
1644				label = "port2";
1645				ti,mac-only;
1646				status = "disabled";
1647			};
1648
1649			main_cpsw0_port3: port@3 {
1650				reg = <3>;
1651				label = "port3";
1652				ti,mac-only;
1653				status = "disabled";
1654			};
1655
1656			main_cpsw0_port4: port@4 {
1657				reg = <4>;
1658				label = "port4";
1659				ti,mac-only;
1660				status = "disabled";
1661			};
1662
1663			main_cpsw0_port5: port@5 {
1664				reg = <5>;
1665				label = "port5";
1666				ti,mac-only;
1667				status = "disabled";
1668			};
1669
1670			main_cpsw0_port6: port@6 {
1671				reg = <6>;
1672				label = "port6";
1673				ti,mac-only;
1674				status = "disabled";
1675			};
1676
1677			main_cpsw0_port7: port@7 {
1678				reg = <7>;
1679				label = "port7";
1680				ti,mac-only;
1681				status = "disabled";
1682			};
1683
1684			main_cpsw0_port8: port@8 {
1685				reg = <8>;
1686				label = "port8";
1687				ti,mac-only;
1688				status = "disabled";
1689			};
1690		};
1691
1692		main_cpsw0_mdio: mdio@f00 {
1693			compatible = "ti,cpsw-mdio","ti,davinci_mdio";
1694			reg = <0x00 0xf00 0x00 0x100>;
1695			#address-cells = <1>;
1696			#size-cells = <0>;
1697			clocks = <&k3_clks 64 0>;
1698			clock-names = "fck";
1699			bus_freq = <1000000>;
1700			status = "disabled";
1701		};
1702
1703		cpts@3d000 {
1704			compatible = "ti,am65-cpts";
1705			reg = <0x00 0x3d000 0x00 0x400>;
1706			clocks = <&k3_clks 64 3>;
1707			clock-names = "cpts";
1708			interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1709			interrupt-names = "cpts";
1710			ti,cpts-ext-ts-inputs = <4>;
1711			ti,cpts-periodic-outputs = <2>;
1712		};
1713	};
1714
1715	main_cpsw1: ethernet@c200000 {
1716		compatible = "ti,j721e-cpsw-nuss";
1717		reg = <0x00 0xc200000 0x00 0x200000>;
1718		reg-names = "cpsw_nuss";
1719		ranges = <0x00 0x00 0x00 0xc200000 0x00 0x200000>;
1720		#address-cells = <2>;
1721		#size-cells = <2>;
1722		dma-coherent;
1723		clocks = <&k3_clks 62 0>;
1724		clock-names = "fck";
1725		power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
1726
1727		dmas = <&main_udmap 0xc640>,
1728			<&main_udmap 0xc641>,
1729			<&main_udmap 0xc642>,
1730			<&main_udmap 0xc643>,
1731			<&main_udmap 0xc644>,
1732			<&main_udmap 0xc645>,
1733			<&main_udmap 0xc646>,
1734			<&main_udmap 0xc647>,
1735			<&main_udmap 0x4640>;
1736		dma-names = "tx0", "tx1", "tx2", "tx3",
1737				"tx4", "tx5", "tx6", "tx7",
1738				"rx";
1739
1740		status = "disabled";
1741
1742		ethernet-ports {
1743			#address-cells = <1>;
1744			#size-cells = <0>;
1745
1746			main_cpsw1_port1: port@1 {
1747				reg = <1>;
1748				label = "port1";
1749				phys = <&cpsw1_phy_gmii_sel 1>;
1750				ti,mac-only;
1751				status = "disabled";
1752			};
1753		};
1754
1755		main_cpsw1_mdio: mdio@f00 {
1756			compatible = "ti,cpsw-mdio", "ti,davinci_mdio";
1757			reg = <0x00 0xf00 0x00 0x100>;
1758			#address-cells = <1>;
1759			#size-cells = <0>;
1760			clocks = <&k3_clks 62 0>;
1761			clock-names = "fck";
1762			bus_freq = <1000000>;
1763			status = "disabled";
1764		};
1765
1766		cpts@3d000 {
1767			compatible = "ti,am65-cpts";
1768			reg = <0x00 0x3d000 0x00 0x400>;
1769			clocks = <&k3_clks 62 3>;
1770			clock-names = "cpts";
1771			interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1772			interrupt-names = "cpts";
1773			ti,cpts-ext-ts-inputs = <4>;
1774			ti,cpts-periodic-outputs = <2>;
1775		};
1776	};
1777
1778	main_mcan0: can@2701000 {
1779		compatible = "bosch,m_can";
1780		reg = <0x00 0x02701000 0x00 0x200>,
1781		      <0x00 0x02708000 0x00 0x8000>;
1782		reg-names = "m_can", "message_ram";
1783		power-domains = <&k3_pds 245 TI_SCI_PD_EXCLUSIVE>;
1784		clocks = <&k3_clks 245 6>, <&k3_clks 245 1>;
1785		clock-names = "hclk", "cclk";
1786		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1787			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
1788		interrupt-names = "int0", "int1";
1789		bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1790		status = "disabled";
1791	};
1792
1793	main_mcan1: can@2711000 {
1794		compatible = "bosch,m_can";
1795		reg = <0x00 0x02711000 0x00 0x200>,
1796		      <0x00 0x02718000 0x00 0x8000>;
1797		reg-names = "m_can", "message_ram";
1798		power-domains = <&k3_pds 246 TI_SCI_PD_EXCLUSIVE>;
1799		clocks = <&k3_clks 246 6>, <&k3_clks 246 1>;
1800		clock-names = "hclk", "cclk";
1801		interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
1802			     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
1803		interrupt-names = "int0", "int1";
1804		bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1805		status = "disabled";
1806	};
1807
1808	main_mcan2: can@2721000 {
1809		compatible = "bosch,m_can";
1810		reg = <0x00 0x02721000 0x00 0x200>,
1811		      <0x00 0x02728000 0x00 0x8000>;
1812		reg-names = "m_can", "message_ram";
1813		power-domains = <&k3_pds 247 TI_SCI_PD_EXCLUSIVE>;
1814		clocks = <&k3_clks 247 6>, <&k3_clks 247 1>;
1815		clock-names = "hclk", "cclk";
1816		interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
1817			     <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
1818		interrupt-names = "int0", "int1";
1819		bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1820		status = "disabled";
1821	};
1822
1823	main_mcan3: can@2731000 {
1824		compatible = "bosch,m_can";
1825		reg = <0x00 0x02731000 0x00 0x200>,
1826		      <0x00 0x02738000 0x00 0x8000>;
1827		reg-names = "m_can", "message_ram";
1828		power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
1829		clocks = <&k3_clks 248 6>, <&k3_clks 248 1>;
1830		clock-names = "hclk", "cclk";
1831		interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
1832			     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
1833		interrupt-names = "int0", "int1";
1834		bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1835		status = "disabled";
1836	};
1837
1838	main_mcan4: can@2741000 {
1839		compatible = "bosch,m_can";
1840		reg = <0x00 0x02741000 0x00 0x200>,
1841		      <0x00 0x02748000 0x00 0x8000>;
1842		reg-names = "m_can", "message_ram";
1843		power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
1844		clocks = <&k3_clks 249 6>, <&k3_clks 249 1>;
1845		clock-names = "hclk", "cclk";
1846		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
1847			     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
1848		interrupt-names = "int0", "int1";
1849		bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1850		status = "disabled";
1851	};
1852
1853	main_mcan5: can@2751000 {
1854		compatible = "bosch,m_can";
1855		reg = <0x00 0x02751000 0x00 0x200>,
1856		      <0x00 0x02758000 0x00 0x8000>;
1857		reg-names = "m_can", "message_ram";
1858		power-domains = <&k3_pds 250 TI_SCI_PD_EXCLUSIVE>;
1859		clocks = <&k3_clks 250 6>, <&k3_clks 250 1>;
1860		clock-names = "hclk", "cclk";
1861		interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
1862			     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
1863		interrupt-names = "int0", "int1";
1864		bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1865		status = "disabled";
1866	};
1867
1868	main_mcan6: can@2761000 {
1869		compatible = "bosch,m_can";
1870		reg = <0x00 0x02761000 0x00 0x200>,
1871		      <0x00 0x02768000 0x00 0x8000>;
1872		reg-names = "m_can", "message_ram";
1873		power-domains = <&k3_pds 251 TI_SCI_PD_EXCLUSIVE>;
1874		clocks = <&k3_clks 251 6>, <&k3_clks 251 1>;
1875		clock-names = "hclk", "cclk";
1876		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1877			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
1878		interrupt-names = "int0", "int1";
1879		bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1880		status = "disabled";
1881	};
1882
1883	main_mcan7: can@2771000 {
1884		compatible = "bosch,m_can";
1885		reg = <0x00 0x02771000 0x00 0x200>,
1886		      <0x00 0x02778000 0x00 0x8000>;
1887		reg-names = "m_can", "message_ram";
1888		power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
1889		clocks = <&k3_clks 252 6>, <&k3_clks 252 1>;
1890		clock-names = "hclk", "cclk";
1891		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1892			     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1893		interrupt-names = "int0", "int1";
1894		bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1895		status = "disabled";
1896	};
1897
1898	main_mcan8: can@2781000 {
1899		compatible = "bosch,m_can";
1900		reg = <0x00 0x02781000 0x00 0x200>,
1901		      <0x00 0x02788000 0x00 0x8000>;
1902		reg-names = "m_can", "message_ram";
1903		power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
1904		clocks = <&k3_clks 253 6>, <&k3_clks 253 1>;
1905		clock-names = "hclk", "cclk";
1906		interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
1907			     <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
1908		interrupt-names = "int0", "int1";
1909		bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1910		status = "disabled";
1911	};
1912
1913	main_mcan9: can@2791000 {
1914		compatible = "bosch,m_can";
1915		reg = <0x00 0x02791000 0x00 0x200>,
1916		      <0x00 0x02798000 0x00 0x8000>;
1917		reg-names = "m_can", "message_ram";
1918		power-domains = <&k3_pds 254 TI_SCI_PD_EXCLUSIVE>;
1919		clocks = <&k3_clks 254 6>, <&k3_clks 254 1>;
1920		clock-names = "hclk", "cclk";
1921		interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>,
1922			     <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
1923		interrupt-names = "int0", "int1";
1924		bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1925		status = "disabled";
1926	};
1927
1928	main_mcan10: can@27a1000 {
1929		compatible = "bosch,m_can";
1930		reg = <0x00 0x027a1000 0x00 0x200>,
1931		      <0x00 0x027a8000 0x00 0x8000>;
1932		reg-names = "m_can", "message_ram";
1933		power-domains = <&k3_pds 255 TI_SCI_PD_EXCLUSIVE>;
1934		clocks = <&k3_clks 255 6>, <&k3_clks 255 1>;
1935		clock-names = "hclk", "cclk";
1936		interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>,
1937			     <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1938		interrupt-names = "int0", "int1";
1939		bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1940		status = "disabled";
1941	};
1942
1943	main_mcan11: can@27b1000 {
1944		compatible = "bosch,m_can";
1945		reg = <0x00 0x027b1000 0x00 0x200>,
1946		      <0x00 0x027b8000 0x00 0x8000>;
1947		reg-names = "m_can", "message_ram";
1948		power-domains = <&k3_pds 256 TI_SCI_PD_EXCLUSIVE>;
1949		clocks = <&k3_clks 256 6>, <&k3_clks 256 1>;
1950		clock-names = "hclk", "cclk";
1951		interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
1952			     <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1953		interrupt-names = "int0", "int1";
1954		bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1955		status = "disabled";
1956	};
1957
1958	main_mcan12: can@27c1000 {
1959		compatible = "bosch,m_can";
1960		reg = <0x00 0x027c1000 0x00 0x200>,
1961		      <0x00 0x027c8000 0x00 0x8000>;
1962		reg-names = "m_can", "message_ram";
1963		power-domains = <&k3_pds 257 TI_SCI_PD_EXCLUSIVE>;
1964		clocks = <&k3_clks 257 6>, <&k3_clks 257 1>;
1965		clock-names = "hclk", "cclk";
1966		interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
1967			     <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
1968		interrupt-names = "int0", "int1";
1969		bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1970		status = "disabled";
1971	};
1972
1973	main_mcan13: can@27d1000 {
1974		compatible = "bosch,m_can";
1975		reg = <0x00 0x027d1000 0x00 0x200>,
1976		      <0x00 0x027d8000 0x00 0x8000>;
1977		reg-names = "m_can", "message_ram";
1978		power-domains = <&k3_pds 258 TI_SCI_PD_EXCLUSIVE>;
1979		clocks = <&k3_clks 258 6>, <&k3_clks 258 1>;
1980		clock-names = "hclk", "cclk";
1981		interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
1982			     <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
1983		interrupt-names = "int0", "int1";
1984		bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1985		status = "disabled";
1986	};
1987
1988	main_mcan14: can@2681000 {
1989		compatible = "bosch,m_can";
1990		reg = <0x00 0x02681000 0x00 0x200>,
1991		      <0x00 0x02688000 0x00 0x8000>;
1992		reg-names = "m_can", "message_ram";
1993		power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>;
1994		clocks = <&k3_clks 259 6>, <&k3_clks 259 1>;
1995		clock-names = "hclk", "cclk";
1996		interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
1997			     <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>;
1998		interrupt-names = "int0", "int1";
1999		bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
2000		status = "disabled";
2001	};
2002
2003	main_mcan15: can@2691000 {
2004		compatible = "bosch,m_can";
2005		reg = <0x00 0x02691000 0x00 0x200>,
2006		      <0x00 0x02698000 0x00 0x8000>;
2007		reg-names = "m_can", "message_ram";
2008		power-domains = <&k3_pds 260 TI_SCI_PD_EXCLUSIVE>;
2009		clocks = <&k3_clks 260 6>, <&k3_clks 260 1>;
2010		clock-names = "hclk", "cclk";
2011		interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
2012			     <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>;
2013		interrupt-names = "int0", "int1";
2014		bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
2015		status = "disabled";
2016	};
2017
2018	main_mcan16: can@26a1000 {
2019		compatible = "bosch,m_can";
2020		reg = <0x00 0x026a1000 0x00 0x200>,
2021		      <0x00 0x026a8000 0x00 0x8000>;
2022		reg-names = "m_can", "message_ram";
2023		power-domains = <&k3_pds 261 TI_SCI_PD_EXCLUSIVE>;
2024		clocks = <&k3_clks 261 6>, <&k3_clks 261 1>;
2025		clock-names = "hclk", "cclk";
2026		interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
2027			     <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>;
2028		interrupt-names = "int0", "int1";
2029		bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
2030		status = "disabled";
2031	};
2032
2033	main_mcan17: can@26b1000 {
2034		compatible = "bosch,m_can";
2035		reg = <0x00 0x026b1000 0x00 0x200>,
2036		      <0x00 0x026b8000 0x00 0x8000>;
2037		reg-names = "m_can", "message_ram";
2038		power-domains = <&k3_pds 262 TI_SCI_PD_EXCLUSIVE>;
2039		clocks = <&k3_clks 262 6>, <&k3_clks 262 1>;
2040		clock-names = "hclk", "cclk";
2041		interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>,
2042			     <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>;
2043		interrupt-names = "int0", "int1";
2044		bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
2045		status = "disabled";
2046	};
2047
2048	main_spi0: spi@2100000 {
2049		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2050		reg = <0x00 0x02100000 0x00 0x400>;
2051		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
2052		#address-cells = <1>;
2053		#size-cells = <0>;
2054		power-domains = <&k3_pds 376 TI_SCI_PD_EXCLUSIVE>;
2055		clocks = <&k3_clks 376 0>;
2056		status = "disabled";
2057	};
2058
2059	main_spi1: spi@2110000 {
2060		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2061		reg = <0x00 0x02110000 0x00 0x400>;
2062		interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
2063		#address-cells = <1>;
2064		#size-cells = <0>;
2065		power-domains = <&k3_pds 377 TI_SCI_PD_EXCLUSIVE>;
2066		clocks = <&k3_clks 377 0>;
2067		status = "disabled";
2068	};
2069
2070	main_spi2: spi@2120000 {
2071		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2072		reg = <0x00 0x02120000 0x00 0x400>;
2073		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
2074		#address-cells = <1>;
2075		#size-cells = <0>;
2076		power-domains = <&k3_pds 378 TI_SCI_PD_EXCLUSIVE>;
2077		clocks = <&k3_clks 378 0>;
2078		status = "disabled";
2079	};
2080
2081	main_spi3: spi@2130000 {
2082		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2083		reg = <0x00 0x02130000 0x00 0x400>;
2084		interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
2085		#address-cells = <1>;
2086		#size-cells = <0>;
2087		power-domains = <&k3_pds 379 TI_SCI_PD_EXCLUSIVE>;
2088		clocks = <&k3_clks 379 0>;
2089		status = "disabled";
2090	};
2091
2092	main_spi4: spi@2140000 {
2093		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2094		reg = <0x00 0x02140000 0x00 0x400>;
2095		interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
2096		#address-cells = <1>;
2097		#size-cells = <0>;
2098		power-domains = <&k3_pds 380 TI_SCI_PD_EXCLUSIVE>;
2099		clocks = <&k3_clks 380 0>;
2100		status = "disabled";
2101	};
2102
2103	main_spi5: spi@2150000 {
2104		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2105		reg = <0x00 0x02150000 0x00 0x400>;
2106		interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
2107		#address-cells = <1>;
2108		#size-cells = <0>;
2109		power-domains = <&k3_pds 381 TI_SCI_PD_EXCLUSIVE>;
2110		clocks = <&k3_clks 381 0>;
2111		status = "disabled";
2112	};
2113
2114	main_spi6: spi@2160000 {
2115		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2116		reg = <0x00 0x02160000 0x00 0x400>;
2117		interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
2118		#address-cells = <1>;
2119		#size-cells = <0>;
2120		power-domains = <&k3_pds 382 TI_SCI_PD_EXCLUSIVE>;
2121		clocks = <&k3_clks 382 0>;
2122		status = "disabled";
2123	};
2124
2125	main_spi7: spi@2170000 {
2126		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2127		reg = <0x00 0x02170000 0x00 0x400>;
2128		interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
2129		#address-cells = <1>;
2130		#size-cells = <0>;
2131		power-domains = <&k3_pds 383 TI_SCI_PD_EXCLUSIVE>;
2132		clocks = <&k3_clks 383 0>;
2133		status = "disabled";
2134	};
2135
2136	ufs_wrapper: ufs-wrapper@4e80000 {
2137		compatible = "ti,j721e-ufs";
2138		reg = <0x00 0x4e80000 0x00 0x100>;
2139		power-domains = <&k3_pds 387 TI_SCI_PD_EXCLUSIVE>;
2140		clocks = <&k3_clks 387 3>;
2141		assigned-clocks = <&k3_clks 387 3>;
2142		assigned-clock-parents = <&k3_clks 387 6>;
2143		ranges;
2144		#address-cells = <2>;
2145		#size-cells = <2>;
2146		status = "disabled";
2147
2148		ufs@4e84000 {
2149			compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
2150			reg = <0x00 0x4e84000 0x00 0x10000>;
2151			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
2152			freq-table-hz = <250000000 250000000>, <19200000 19200000>,
2153					<19200000 19200000>;
2154			clocks = <&k3_clks 387 1>, <&k3_clks 387 3>, <&k3_clks 387 3>;
2155			clock-names = "core_clk", "phy_clk", "ref_clk";
2156			dma-coherent;
2157		};
2158	};
2159
2160	main_r5fss0: r5fss@5c00000 {
2161		compatible = "ti,j721s2-r5fss";
2162		ti,cluster-mode = <1>;
2163		#address-cells = <1>;
2164		#size-cells = <1>;
2165		ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
2166			 <0x5d00000 0x00 0x5d00000 0x20000>;
2167		power-domains = <&k3_pds 336 TI_SCI_PD_EXCLUSIVE>;
2168
2169		main_r5fss0_core0: r5f@5c00000 {
2170			compatible = "ti,j721s2-r5f";
2171			reg = <0x5c00000 0x00010000>,
2172			      <0x5c10000 0x00010000>;
2173			reg-names = "atcm", "btcm";
2174			ti,sci = <&sms>;
2175			ti,sci-dev-id = <339>;
2176			ti,sci-proc-ids = <0x06 0xff>;
2177			resets = <&k3_reset 339 1>;
2178			firmware-name = "j784s4-main-r5f0_0-fw";
2179			ti,atcm-enable = <1>;
2180			ti,btcm-enable = <1>;
2181			ti,loczrama = <1>;
2182		};
2183
2184		main_r5fss0_core1: r5f@5d00000 {
2185			compatible = "ti,j721s2-r5f";
2186			reg = <0x5d00000 0x00010000>,
2187			      <0x5d10000 0x00010000>;
2188			reg-names = "atcm", "btcm";
2189			ti,sci = <&sms>;
2190			ti,sci-dev-id = <340>;
2191			ti,sci-proc-ids = <0x07 0xff>;
2192			resets = <&k3_reset 340 1>;
2193			firmware-name = "j784s4-main-r5f0_1-fw";
2194			ti,atcm-enable = <1>;
2195			ti,btcm-enable = <1>;
2196			ti,loczrama = <1>;
2197		};
2198	};
2199
2200	main_r5fss1: r5fss@5e00000 {
2201		compatible = "ti,j721s2-r5fss";
2202		ti,cluster-mode = <1>;
2203		#address-cells = <1>;
2204		#size-cells = <1>;
2205		ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
2206			 <0x5f00000 0x00 0x5f00000 0x20000>;
2207		power-domains = <&k3_pds 337 TI_SCI_PD_EXCLUSIVE>;
2208
2209		main_r5fss1_core0: r5f@5e00000 {
2210			compatible = "ti,j721s2-r5f";
2211			reg = <0x5e00000 0x00010000>,
2212			      <0x5e10000 0x00010000>;
2213			reg-names = "atcm", "btcm";
2214			ti,sci = <&sms>;
2215			ti,sci-dev-id = <341>;
2216			ti,sci-proc-ids = <0x08 0xff>;
2217			resets = <&k3_reset 341 1>;
2218			firmware-name = "j784s4-main-r5f1_0-fw";
2219			ti,atcm-enable = <1>;
2220			ti,btcm-enable = <1>;
2221			ti,loczrama = <1>;
2222		};
2223
2224		main_r5fss1_core1: r5f@5f00000 {
2225			compatible = "ti,j721s2-r5f";
2226			reg = <0x5f00000 0x00010000>,
2227			      <0x5f10000 0x00010000>;
2228			reg-names = "atcm", "btcm";
2229			ti,sci = <&sms>;
2230			ti,sci-dev-id = <342>;
2231			ti,sci-proc-ids = <0x09 0xff>;
2232			resets = <&k3_reset 342 1>;
2233			firmware-name = "j784s4-main-r5f1_1-fw";
2234			ti,atcm-enable = <1>;
2235			ti,btcm-enable = <1>;
2236			ti,loczrama = <1>;
2237		};
2238	};
2239
2240	main_r5fss2: r5fss@5900000 {
2241		compatible = "ti,j721s2-r5fss";
2242		ti,cluster-mode = <1>;
2243		#address-cells = <1>;
2244		#size-cells = <1>;
2245		ranges = <0x5900000 0x00 0x5900000 0x20000>,
2246			 <0x5a00000 0x00 0x5a00000 0x20000>;
2247		power-domains = <&k3_pds 338 TI_SCI_PD_EXCLUSIVE>;
2248
2249		main_r5fss2_core0: r5f@5900000 {
2250			compatible = "ti,j721s2-r5f";
2251			reg = <0x5900000 0x00010000>,
2252			      <0x5910000 0x00010000>;
2253			reg-names = "atcm", "btcm";
2254			ti,sci = <&sms>;
2255			ti,sci-dev-id = <343>;
2256			ti,sci-proc-ids = <0x0a 0xff>;
2257			resets = <&k3_reset 343 1>;
2258			firmware-name = "j784s4-main-r5f2_0-fw";
2259			ti,atcm-enable = <1>;
2260			ti,btcm-enable = <1>;
2261			ti,loczrama = <1>;
2262		};
2263
2264		main_r5fss2_core1: r5f@5a00000 {
2265			compatible = "ti,j721s2-r5f";
2266			reg = <0x5a00000 0x00010000>,
2267			      <0x5a10000 0x00010000>;
2268			reg-names = "atcm", "btcm";
2269			ti,sci = <&sms>;
2270			ti,sci-dev-id = <344>;
2271			ti,sci-proc-ids = <0x0b 0xff>;
2272			resets = <&k3_reset 344 1>;
2273			firmware-name = "j784s4-main-r5f2_1-fw";
2274			ti,atcm-enable = <1>;
2275			ti,btcm-enable = <1>;
2276			ti,loczrama = <1>;
2277		};
2278	};
2279
2280	c71_0: dsp@64800000 {
2281		compatible = "ti,j721s2-c71-dsp";
2282		reg = <0x00 0x64800000 0x00 0x00080000>,
2283		      <0x00 0x64e00000 0x00 0x0000c000>;
2284		reg-names = "l2sram", "l1dram";
2285		ti,sci = <&sms>;
2286		ti,sci-dev-id = <30>;
2287		ti,sci-proc-ids = <0x30 0xff>;
2288		resets = <&k3_reset 30 1>;
2289		firmware-name = "j784s4-c71_0-fw";
2290		status = "disabled";
2291	};
2292
2293	c71_1: dsp@65800000 {
2294		compatible = "ti,j721s2-c71-dsp";
2295		reg = <0x00 0x65800000 0x00 0x00080000>,
2296		      <0x00 0x65e00000 0x00 0x0000c000>;
2297		reg-names = "l2sram", "l1dram";
2298		ti,sci = <&sms>;
2299		ti,sci-dev-id = <33>;
2300		ti,sci-proc-ids = <0x31 0xff>;
2301		resets = <&k3_reset 33 1>;
2302		firmware-name = "j784s4-c71_1-fw";
2303		status = "disabled";
2304	};
2305
2306	c71_2: dsp@66800000 {
2307		compatible = "ti,j721s2-c71-dsp";
2308		reg = <0x00 0x66800000 0x00 0x00080000>,
2309		      <0x00 0x66e00000 0x00 0x0000c000>;
2310		reg-names = "l2sram", "l1dram";
2311		ti,sci = <&sms>;
2312		ti,sci-dev-id = <37>;
2313		ti,sci-proc-ids = <0x32 0xff>;
2314		resets = <&k3_reset 37 1>;
2315		firmware-name = "j784s4-c71_2-fw";
2316		status = "disabled";
2317	};
2318
2319	main_esm: esm@700000 {
2320		compatible = "ti,j721e-esm";
2321		reg = <0x00 0x700000 0x00 0x1000>;
2322		ti,esm-pins = <688>, <689>, <690>, <691>, <692>, <693>, <694>,
2323			      <695>;
2324		bootph-pre-ram;
2325	};
2326
2327	watchdog0: watchdog@2200000 {
2328		compatible = "ti,j7-rti-wdt";
2329		reg = <0x00 0x2200000 0x00 0x100>;
2330		clocks = <&k3_clks 348 0>;
2331		power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>;
2332		assigned-clocks = <&k3_clks 348 0>;
2333		assigned-clock-parents = <&k3_clks 348 4>;
2334	};
2335
2336	watchdog1: watchdog@2210000 {
2337		compatible = "ti,j7-rti-wdt";
2338		reg = <0x00 0x2210000 0x00 0x100>;
2339		clocks = <&k3_clks 349 0>;
2340		power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>;
2341		assigned-clocks = <&k3_clks 349 0>;
2342		assigned-clock-parents = <&k3_clks 349 4>;
2343	};
2344
2345	watchdog2: watchdog@2220000 {
2346		compatible = "ti,j7-rti-wdt";
2347		reg = <0x00 0x2220000 0x00 0x100>;
2348		clocks = <&k3_clks 350 0>;
2349		power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>;
2350		assigned-clocks = <&k3_clks 350 0>;
2351		assigned-clock-parents = <&k3_clks 350 4>;
2352	};
2353
2354	watchdog3: watchdog@2230000 {
2355		compatible = "ti,j7-rti-wdt";
2356		reg = <0x00 0x2230000 0x00 0x100>;
2357		clocks = <&k3_clks 351 0>;
2358		power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>;
2359		assigned-clocks = <&k3_clks 351 0>;
2360		assigned-clock-parents = <&k3_clks 351 4>;
2361	};
2362
2363	watchdog4: watchdog@2240000 {
2364		compatible = "ti,j7-rti-wdt";
2365		reg = <0x00 0x2240000 0x00 0x100>;
2366		clocks = <&k3_clks 352 0>;
2367		power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>;
2368		assigned-clocks = <&k3_clks 352 0>;
2369		assigned-clock-parents = <&k3_clks 352 4>;
2370	};
2371
2372	watchdog5: watchdog@2250000 {
2373		compatible = "ti,j7-rti-wdt";
2374		reg = <0x00 0x2250000 0x00 0x100>;
2375		clocks = <&k3_clks 353 0>;
2376		power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>;
2377		assigned-clocks = <&k3_clks 353 0>;
2378		assigned-clock-parents = <&k3_clks 353 4>;
2379	};
2380
2381	watchdog6: watchdog@2260000 {
2382		compatible = "ti,j7-rti-wdt";
2383		reg = <0x00 0x2260000 0x00 0x100>;
2384		clocks = <&k3_clks 354 0>;
2385		power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>;
2386		assigned-clocks = <&k3_clks 354 0>;
2387		assigned-clock-parents = <&k3_clks 354 4>;
2388	};
2389
2390	watchdog7: watchdog@2270000 {
2391		compatible = "ti,j7-rti-wdt";
2392		reg = <0x00 0x2270000 0x00 0x100>;
2393		clocks = <&k3_clks 355 0>;
2394		power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>;
2395		assigned-clocks = <&k3_clks 355 0>;
2396		assigned-clock-parents = <&k3_clks 355 4>;
2397	};
2398
2399	/*
2400	 * The following RTI instances are coupled with MCU R5Fs, c7x and
2401	 * GPU so keeping them reserved as these will be used by their
2402	 * respective firmware
2403	 */
2404	watchdog8: watchdog@22f0000 {
2405		compatible = "ti,j7-rti-wdt";
2406		reg = <0x00 0x22f0000 0x00 0x100>;
2407		clocks = <&k3_clks 360 0>;
2408		power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>;
2409		assigned-clocks = <&k3_clks 360 0>;
2410		assigned-clock-parents = <&k3_clks 360 4>;
2411		/* reserved for GPU */
2412		status = "reserved";
2413	};
2414
2415	watchdog9: watchdog@2300000 {
2416		compatible = "ti,j7-rti-wdt";
2417		reg = <0x00 0x2300000 0x00 0x100>;
2418		clocks = <&k3_clks 356 0>;
2419		power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>;
2420		assigned-clocks = <&k3_clks 356 0>;
2421		assigned-clock-parents = <&k3_clks 356 4>;
2422		/* reserved for C7X_0 DSP */
2423		status = "reserved";
2424	};
2425
2426	watchdog10: watchdog@2310000 {
2427		compatible = "ti,j7-rti-wdt";
2428		reg = <0x00 0x2310000 0x00 0x100>;
2429		clocks = <&k3_clks 357 0>;
2430		power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>;
2431		assigned-clocks = <&k3_clks 357 0>;
2432		assigned-clock-parents = <&k3_clks 357 4>;
2433		/* reserved for C7X_1 DSP */
2434		status = "reserved";
2435	};
2436
2437	watchdog11: watchdog@2320000 {
2438		compatible = "ti,j7-rti-wdt";
2439		reg = <0x00 0x2320000 0x00 0x100>;
2440		clocks = <&k3_clks 358 0>;
2441		power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>;
2442		assigned-clocks = <&k3_clks 358 0>;
2443		assigned-clock-parents = <&k3_clks 358 4>;
2444		/* reserved for C7X_2 DSP */
2445		status = "reserved";
2446	};
2447
2448	watchdog12: watchdog@2330000 {
2449		compatible = "ti,j7-rti-wdt";
2450		reg = <0x00 0x2330000 0x00 0x100>;
2451		clocks = <&k3_clks 359 0>;
2452		power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>;
2453		assigned-clocks = <&k3_clks 359 0>;
2454		assigned-clock-parents = <&k3_clks 359 4>;
2455		/* reserved for C7X_3 DSP */
2456		status = "reserved";
2457	};
2458
2459	watchdog13: watchdog@23c0000 {
2460		compatible = "ti,j7-rti-wdt";
2461		reg = <0x00 0x23c0000 0x00 0x100>;
2462		clocks = <&k3_clks 361 0>;
2463		power-domains = <&k3_pds 361 TI_SCI_PD_EXCLUSIVE>;
2464		assigned-clocks = <&k3_clks 361 0>;
2465		assigned-clock-parents = <&k3_clks 361 4>;
2466		/* reserved for MAIN_R5F0_0 */
2467		status = "reserved";
2468	};
2469
2470	watchdog14: watchdog@23d0000 {
2471		compatible = "ti,j7-rti-wdt";
2472		reg = <0x00 0x23d0000 0x00 0x100>;
2473		clocks = <&k3_clks 362 0>;
2474		power-domains = <&k3_pds 362 TI_SCI_PD_EXCLUSIVE>;
2475		assigned-clocks = <&k3_clks 362 0>;
2476		assigned-clock-parents = <&k3_clks 362 4>;
2477		/* reserved for MAIN_R5F0_1 */
2478		status = "reserved";
2479	};
2480
2481	watchdog15: watchdog@23e0000 {
2482		compatible = "ti,j7-rti-wdt";
2483		reg = <0x00 0x23e0000 0x00 0x100>;
2484		clocks = <&k3_clks 363 0>;
2485		power-domains = <&k3_pds 363 TI_SCI_PD_EXCLUSIVE>;
2486		assigned-clocks = <&k3_clks 363 0>;
2487		assigned-clock-parents = <&k3_clks 363 4>;
2488		/* reserved for MAIN_R5F1_0 */
2489		status = "reserved";
2490	};
2491
2492	watchdog16: watchdog@23f0000 {
2493		compatible = "ti,j7-rti-wdt";
2494		reg = <0x00 0x23f0000 0x00 0x100>;
2495		clocks = <&k3_clks 364 0>;
2496		power-domains = <&k3_pds 364 TI_SCI_PD_EXCLUSIVE>;
2497		assigned-clocks = <&k3_clks 364 0>;
2498		assigned-clock-parents = <&k3_clks 364 4>;
2499		/* reserved for MAIN_R5F1_1 */
2500		status = "reserved";
2501	};
2502
2503	watchdog17: watchdog@2540000 {
2504		compatible = "ti,j7-rti-wdt";
2505		reg = <0x00 0x2540000 0x00 0x100>;
2506		clocks = <&k3_clks 365 0>;
2507		power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>;
2508		assigned-clocks = <&k3_clks 365 0>;
2509		assigned-clock-parents = <&k3_clks 366 4>;
2510		/* reserved for MAIN_R5F2_0 */
2511		status = "reserved";
2512	};
2513
2514	watchdog18: watchdog@2550000 {
2515		compatible = "ti,j7-rti-wdt";
2516		reg = <0x00 0x2550000 0x00 0x100>;
2517		clocks = <&k3_clks 366 0>;
2518		power-domains = <&k3_pds 366 TI_SCI_PD_EXCLUSIVE>;
2519		assigned-clocks = <&k3_clks 366 0>;
2520		assigned-clock-parents = <&k3_clks 366 4>;
2521		/* reserved for MAIN_R5F2_1 */
2522		status = "reserved";
2523	};
2524
2525	mhdp: bridge@a000000 {
2526		compatible = "ti,j721e-mhdp8546";
2527		reg = <0x0 0xa000000 0x0 0x30a00>,
2528		      <0x0 0x4f40000 0x0 0x20>;
2529		reg-names = "mhdptx", "j721e-intg";
2530		clocks = <&k3_clks 217 11>;
2531		interrupt-parent = <&gic500>;
2532		interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
2533		power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>;
2534		status = "disabled";
2535
2536		dp0_ports: ports {
2537			#address-cells = <1>;
2538			#size-cells = <0>;
2539			/* Remote-endpoints are on the boards so
2540			 * ports are defined in the platform dt file.
2541			 */
2542		};
2543	};
2544
2545	dss: dss@4a00000 {
2546		compatible = "ti,j721e-dss";
2547		reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */
2548		      <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
2549		      <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
2550		      <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
2551		      <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
2552		      <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
2553		      <0x00 0x04a50000 0x00 0x10000>, /* vid1 */
2554		      <0x00 0x04a60000 0x00 0x10000>, /* vid2 */
2555		      <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
2556		      <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
2557		      <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
2558		      <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
2559		      <0x00 0x04a80000 0x00 0x10000>, /* vp1 */
2560		      <0x00 0x04aa0000 0x00 0x10000>, /* vp1 */
2561		      <0x00 0x04ac0000 0x00 0x10000>, /* vp1 */
2562		      <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
2563		      <0x00 0x04af0000 0x00 0x10000>; /* wb */
2564		reg-names = "common_m", "common_s0",
2565			    "common_s1", "common_s2",
2566			    "vidl1", "vidl2","vid1","vid2",
2567			    "ovr1", "ovr2", "ovr3", "ovr4",
2568			    "vp1", "vp2", "vp3", "vp4",
2569			    "wb";
2570		clocks = <&k3_clks 218 0>,
2571			 <&k3_clks 218 2>,
2572			 <&k3_clks 218 5>,
2573			 <&k3_clks 218 14>,
2574			 <&k3_clks 218 18>;
2575		clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
2576		power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>;
2577		interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
2578			     <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
2579			     <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
2580			     <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
2581		interrupt-names = "common_m",
2582				  "common_s0",
2583				  "common_s1",
2584				  "common_s2";
2585		status = "disabled";
2586
2587		dss_ports: ports {
2588			/* Ports that DSS drives are platform specific
2589			 * so they are defined in platform dt file.
2590			 */
2591		};
2592	};
2593
2594	mcasp0: mcasp@2b00000 {
2595		compatible = "ti,am33xx-mcasp-audio";
2596		reg = <0x00 0x02b00000 0x00 0x2000>,
2597		      <0x00 0x02b08000 0x00 0x1000>;
2598		reg-names = "mpu","dat";
2599		interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
2600			     <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
2601		interrupt-names = "tx", "rx";
2602		dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
2603		dma-names = "tx", "rx";
2604		clocks = <&k3_clks 265 0>;
2605		clock-names = "fck";
2606		assigned-clocks = <&k3_clks 265 0>;
2607		assigned-clock-parents = <&k3_clks 265 1>;
2608		power-domains = <&k3_pds 265 TI_SCI_PD_EXCLUSIVE>;
2609		status = "disabled";
2610	};
2611
2612	mcasp1: mcasp@2b10000 {
2613		compatible = "ti,am33xx-mcasp-audio";
2614		reg = <0x00 0x02b10000 0x00 0x2000>,
2615		      <0x00 0x02b18000 0x00 0x1000>;
2616		reg-names = "mpu","dat";
2617		interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>,
2618			     <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>;
2619		interrupt-names = "tx", "rx";
2620		dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
2621		dma-names = "tx", "rx";
2622		clocks = <&k3_clks 266 0>;
2623		clock-names = "fck";
2624		assigned-clocks = <&k3_clks 266 0>;
2625		assigned-clock-parents = <&k3_clks 266 1>;
2626		power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>;
2627		status = "disabled";
2628	};
2629
2630	mcasp2: mcasp@2b20000 {
2631		compatible = "ti,am33xx-mcasp-audio";
2632		reg = <0x00 0x02b20000 0x00 0x2000>,
2633		      <0x00 0x02b28000 0x00 0x1000>;
2634		reg-names = "mpu","dat";
2635		interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>,
2636			     <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>;
2637		interrupt-names = "tx", "rx";
2638		dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
2639		dma-names = "tx", "rx";
2640		clocks = <&k3_clks 267 0>;
2641		clock-names = "fck";
2642		assigned-clocks = <&k3_clks 267 0>;
2643		assigned-clock-parents = <&k3_clks 267 1>;
2644		power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>;
2645		status = "disabled";
2646	};
2647
2648	mcasp3: mcasp@2b30000 {
2649		compatible = "ti,am33xx-mcasp-audio";
2650		reg = <0x00 0x02b30000 0x00 0x2000>,
2651		      <0x00 0x02b38000 0x00 0x1000>;
2652		reg-names = "mpu","dat";
2653		interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>,
2654			     <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
2655		interrupt-names = "tx", "rx";
2656		dmas = <&main_udmap 0xc403>, <&main_udmap 0x4403>;
2657		dma-names = "tx", "rx";
2658		clocks = <&k3_clks 268 0>;
2659		clock-names = "fck";
2660		assigned-clocks = <&k3_clks 268 0>;
2661		assigned-clock-parents = <&k3_clks 268 1>;
2662		power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>;
2663		status = "disabled";
2664	};
2665
2666	mcasp4: mcasp@2b40000 {
2667		compatible = "ti,am33xx-mcasp-audio";
2668		reg = <0x00 0x02b40000 0x00 0x2000>,
2669		      <0x00 0x02b48000 0x00 0x1000>;
2670		reg-names = "mpu","dat";
2671		interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>,
2672			     <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
2673		interrupt-names = "tx", "rx";
2674		dmas = <&main_udmap 0xc404>, <&main_udmap 0x4404>;
2675		dma-names = "tx", "rx";
2676		clocks = <&k3_clks 269 0>;
2677		clock-names = "fck";
2678		assigned-clocks = <&k3_clks 269 0>;
2679		assigned-clock-parents = <&k3_clks 269 1>;
2680		power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>;
2681		status = "disabled";
2682	};
2683
2684	bist_main14: bist@33c0000 {
2685		compatible = "ti,j784s4-bist";
2686		reg = <0x00 0x033c0000 0x00 0x400>,
2687		      <0x00 0x0010c1a0 0x00 0x01c>;
2688		reg-names = "cfg", "ctrl_mmr";
2689		clocks = <&k3_clks 237 7>;
2690		power-domains = <&k3_pds 237 TI_SCI_PD_EXCLUSIVE>;
2691		bootph-pre-ram;
2692		ti,sci-dev-id = <234>;
2693	};
2694};
2695