1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/G3S SoC 4 * 5 * Copyright (C) 2023 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/r9a08g045-cpg.h> 10#include <dt-bindings/clock/renesas,r9a08g045-vbattb.h> 11 12/ { 13 compatible = "renesas,r9a08g045"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 interrupt-parent = <&gic>; 17 18 audio_clk1: audio1-clk { 19 compatible = "fixed-clock"; 20 #clock-cells = <0>; 21 /* This value must be overridden by boards that provide it. */ 22 clock-frequency = <0>; 23 }; 24 25 audio_clk2: audio2-clk { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 /* This value must be overridden by boards that provide it. */ 29 clock-frequency = <0>; 30 }; 31 32 cluster0_opp: opp-table-0 { 33 compatible = "operating-points-v2"; 34 opp-shared; 35 36 opp-137500000 { 37 opp-hz = /bits/ 64 <137500000>; 38 opp-microvolt = <940000>; 39 clock-latency-ns = <300000>; 40 }; 41 opp-275000000 { 42 opp-hz = /bits/ 64 <275000000>; 43 opp-microvolt = <940000>; 44 clock-latency-ns = <300000>; 45 }; 46 opp-550000000 { 47 opp-hz = /bits/ 64 <550000000>; 48 opp-microvolt = <940000>; 49 clock-latency-ns = <300000>; 50 }; 51 opp-1100000000 { 52 opp-hz = /bits/ 64 <1100000000>; 53 opp-microvolt = <940000>; 54 clock-latency-ns = <300000>; 55 opp-suspend; 56 }; 57 }; 58 59 cpus { 60 #address-cells = <1>; 61 #size-cells = <0>; 62 63 cpu0: cpu@0 { 64 compatible = "arm,cortex-a55"; 65 reg = <0>; 66 device_type = "cpu"; 67 #cooling-cells = <2>; 68 next-level-cache = <&L3_CA55>; 69 enable-method = "psci"; 70 clocks = <&cpg CPG_CORE R9A08G045_CLK_I>; 71 operating-points-v2 = <&cluster0_opp>; 72 }; 73 74 L3_CA55: cache-controller-0 { 75 compatible = "cache"; 76 cache-level = <3>; 77 cache-unified; 78 cache-size = <0x40000>; 79 }; 80 }; 81 82 extal_clk: extal-clk { 83 compatible = "fixed-clock"; 84 #clock-cells = <0>; 85 /* This value must be overridden by the board. */ 86 clock-frequency = <0>; 87 }; 88 89 psci { 90 compatible = "arm,psci-1.0", "arm,psci-0.2"; 91 method = "smc"; 92 }; 93 94 soc: soc { 95 compatible = "simple-bus"; 96 #address-cells = <2>; 97 #size-cells = <2>; 98 ranges; 99 100 scif0: serial@1004b800 { 101 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044"; 102 reg = <0 0x1004b800 0 0x400>; 103 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>; 109 interrupt-names = "eri", "rxi", "txi", 110 "bri", "dri", "tei"; 111 clocks = <&cpg CPG_MOD R9A08G045_SCIF0_CLK_PCK>; 112 clock-names = "fck"; 113 power-domains = <&cpg>; 114 resets = <&cpg R9A08G045_SCIF0_RST_SYSTEM_N>; 115 status = "disabled"; 116 }; 117 118 scif1: serial@1004bc00 { 119 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044"; 120 reg = <0 0x1004bc00 0 0x400>; 121 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 122 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 123 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 124 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 125 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 126 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 127 interrupt-names = "eri", "rxi", "txi", 128 "bri", "dri", "tei"; 129 clocks = <&cpg CPG_MOD R9A08G045_SCIF1_CLK_PCK>; 130 clock-names = "fck"; 131 power-domains = <&cpg>; 132 resets = <&cpg R9A08G045_SCIF1_RST_SYSTEM_N>; 133 status = "disabled"; 134 }; 135 136 scif2: serial@1004c000 { 137 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044"; 138 reg = <0 0x1004c000 0 0x400>; 139 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>; 145 interrupt-names = "eri", "rxi", "txi", 146 "bri", "dri", "tei"; 147 clocks = <&cpg CPG_MOD R9A08G045_SCIF2_CLK_PCK>; 148 clock-names = "fck"; 149 power-domains = <&cpg>; 150 resets = <&cpg R9A08G045_SCIF2_RST_SYSTEM_N>; 151 status = "disabled"; 152 }; 153 154 scif3: serial@1004c400 { 155 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044"; 156 reg = <0 0x1004c400 0 0x400>; 157 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; 163 interrupt-names = "eri", "rxi", "txi", 164 "bri", "dri", "tei"; 165 clocks = <&cpg CPG_MOD R9A08G045_SCIF3_CLK_PCK>; 166 clock-names = "fck"; 167 power-domains = <&cpg>; 168 resets = <&cpg R9A08G045_SCIF3_RST_SYSTEM_N>; 169 status = "disabled"; 170 }; 171 172 scif4: serial@1004c800 { 173 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044"; 174 reg = <0 0x1004c800 0 0x400>; 175 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 181 interrupt-names = "eri", "rxi", "txi", 182 "bri", "dri", "tei"; 183 clocks = <&cpg CPG_MOD R9A08G045_SCIF4_CLK_PCK>; 184 clock-names = "fck"; 185 power-domains = <&cpg>; 186 resets = <&cpg R9A08G045_SCIF4_RST_SYSTEM_N>; 187 status = "disabled"; 188 }; 189 190 scif5: serial@1004e000 { 191 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044"; 192 reg = <0 0x1004e000 0 0x400>; 193 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 199 interrupt-names = "eri", "rxi", "txi", 200 "bri", "dri", "tei"; 201 clocks = <&cpg CPG_MOD R9A08G045_SCIF5_CLK_PCK>; 202 clock-names = "fck"; 203 power-domains = <&cpg>; 204 resets = <&cpg R9A08G045_SCIF5_RST_SYSTEM_N>; 205 status = "disabled"; 206 }; 207 208 rtc: rtc@1004ec00 { 209 compatible = "renesas,r9a08g045-rtca3", "renesas,rz-rtca3"; 210 reg = <0 0x1004ec00 0 0x400>; 211 interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; 214 interrupt-names = "alarm", "period", "carry"; 215 clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb VBATTB_VBATTCLK>; 216 clock-names = "bus", "counter"; 217 power-domains = <&cpg>; 218 resets = <&cpg R9A08G045_VBAT_BRESETN>; 219 status = "disabled"; 220 }; 221 222 adc: adc@10058000 { 223 compatible = "renesas,r9a08g045-adc"; 224 reg = <0 0x10058000 0 0x1000>; 225 interrupts = <GIC_SPI 312 IRQ_TYPE_EDGE_RISING>; 226 clocks = <&cpg CPG_MOD R9A08G045_ADC_ADCLK>, 227 <&cpg CPG_MOD R9A08G045_ADC_PCLK>; 228 clock-names = "adclk", "pclk"; 229 resets = <&cpg R9A08G045_ADC_PRESETN>, 230 <&cpg R9A08G045_ADC_ADRST_N>; 231 reset-names = "presetn", "adrst-n"; 232 power-domains = <&cpg>; 233 #address-cells = <1>; 234 #size-cells = <0>; 235 #io-channel-cells = <1>; 236 237 channel@0 { 238 reg = <0>; 239 }; 240 241 channel@1 { 242 reg = <1>; 243 }; 244 245 channel@2 { 246 reg = <2>; 247 }; 248 249 channel@3 { 250 reg = <3>; 251 }; 252 253 channel@4 { 254 reg = <4>; 255 }; 256 257 channel@5 { 258 reg = <5>; 259 }; 260 261 channel@6 { 262 reg = <6>; 263 }; 264 265 channel@7 { 266 reg = <7>; 267 }; 268 269 channel@8 { 270 reg = <8>; 271 }; 272 }; 273 274 tsu: thermal@10059000 { 275 compatible = "renesas,r9a08g045-tsu"; 276 reg = <0 0x10059000 0 0x1000>; 277 clocks = <&cpg CPG_MOD R9A08G045_TSU_PCLK>; 278 resets = <&cpg R9A08G045_TSU_PRESETN>; 279 power-domains = <&cpg>; 280 #thermal-sensor-cells = <0>; 281 io-channels = <&adc 8>; 282 io-channel-names = "tsu"; 283 }; 284 285 i3c: i3c@1005b000 { 286 compatible = "renesas,r9a08g045-i3c"; 287 reg = <0 0x1005b000 0 0x1000>; 288 clocks = <&cpg CPG_MOD R9A08G045_I3C_PCLK>, 289 <&cpg CPG_MOD R9A08G045_I3C_TCLK>; 290 clock-names = "pclk", "tclk"; 291 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 294 IRQ_TYPE_EDGE_RISING>, 295 <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>, 296 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 297 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 298 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 299 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 300 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 306 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 307 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 308 interrupt-names = "ierr", "terr", "abort", "resp", 309 "cmd", "ibi", "rx", "tx", "rcv", 310 "st", "sp", "tend", "nack", "al", 311 "tmo", "wu", "exit"; 312 resets = <&cpg R9A08G045_I3C_PRESETN>, 313 <&cpg R9A08G045_I3C_TRESETN>; 314 reset-names = "presetn", "tresetn"; 315 power-domains = <&cpg>; 316 #address-cells = <3>; 317 #size-cells = <0>; 318 status = "disabled"; 319 }; 320 321 vbattb: clock-controller@1005c000 { 322 compatible = "renesas,r9a08g045-vbattb"; 323 reg = <0 0x1005c000 0 0x1000>; 324 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 325 clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>; 326 clock-names = "bclk", "rtx"; 327 #clock-cells = <1>; 328 power-domains = <&cpg>; 329 resets = <&cpg R9A08G045_VBAT_BRESETN>; 330 status = "disabled"; 331 }; 332 333 i2c0: i2c@10090000 { 334 compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057"; 335 reg = <0 0x10090000 0 0x400>; 336 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 337 <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>, 338 <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 339 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 340 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 341 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 342 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 343 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 344 interrupt-names = "tei", "ri", "ti", "spi", "sti", 345 "naki", "ali", "tmoi"; 346 clocks = <&cpg CPG_MOD R9A08G045_I2C0_PCLK>; 347 clock-frequency = <100000>; 348 resets = <&cpg R9A08G045_I2C0_MRST>; 349 power-domains = <&cpg>; 350 #address-cells = <1>; 351 #size-cells = <0>; 352 status = "disabled"; 353 }; 354 355 i2c1: i2c@10090400 { 356 compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057"; 357 reg = <0 0x10090400 0 0x400>; 358 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>, 360 <GIC_SPI 272 IRQ_TYPE_EDGE_RISING>, 361 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 362 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 363 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 364 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 365 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>; 366 interrupt-names = "tei", "ri", "ti", "spi", "sti", 367 "naki", "ali", "tmoi"; 368 clocks = <&cpg CPG_MOD R9A08G045_I2C1_PCLK>; 369 clock-frequency = <100000>; 370 resets = <&cpg R9A08G045_I2C1_MRST>; 371 power-domains = <&cpg>; 372 #address-cells = <1>; 373 #size-cells = <0>; 374 status = "disabled"; 375 }; 376 377 i2c2: i2c@10090800 { 378 compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057"; 379 reg = <0 0x10090800 0 0x400>; 380 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 381 <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>, 382 <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>, 383 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 384 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 385 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 386 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 387 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>; 388 interrupt-names = "tei", "ri", "ti", "spi", "sti", 389 "naki", "ali", "tmoi"; 390 clocks = <&cpg CPG_MOD R9A08G045_I2C2_PCLK>; 391 clock-frequency = <100000>; 392 resets = <&cpg R9A08G045_I2C2_MRST>; 393 power-domains = <&cpg>; 394 #address-cells = <1>; 395 #size-cells = <0>; 396 status = "disabled"; 397 }; 398 399 i2c3: i2c@10090c00 { 400 compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057"; 401 reg = <0 0x10090c00 0 0x400>; 402 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 403 <GIC_SPI 287 IRQ_TYPE_EDGE_RISING>, 404 <GIC_SPI 288 IRQ_TYPE_EDGE_RISING>, 405 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 406 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 407 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 408 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, 409 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 410 interrupt-names = "tei", "ri", "ti", "spi", "sti", 411 "naki", "ali", "tmoi"; 412 clocks = <&cpg CPG_MOD R9A08G045_I2C3_PCLK>; 413 clock-frequency = <100000>; 414 resets = <&cpg R9A08G045_I2C3_MRST>; 415 power-domains = <&cpg>; 416 #address-cells = <1>; 417 #size-cells = <0>; 418 status = "disabled"; 419 }; 420 421 ssi0: ssi@100a8000 { 422 compatible = "renesas,r9a08g045-ssi", 423 "renesas,rz-ssi"; 424 reg = <0 0x100a8000 0 0x400>; 425 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 241 IRQ_TYPE_EDGE_RISING>, 427 <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>; 428 interrupt-names = "int_req", "dma_rx", "dma_tx"; 429 clocks = <&cpg CPG_MOD R9A08G045_SSI0_PCLK2>, 430 <&cpg CPG_MOD R9A08G045_SSI0_PCLK_SFR>, 431 <&audio_clk1>, <&audio_clk2>; 432 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 433 resets = <&cpg R9A08G045_SSI0_RST_M2_REG>; 434 dmas = <&dmac 0x2665>, <&dmac 0x2666>; 435 dma-names = "tx", "rx"; 436 power-domains = <&cpg>; 437 #sound-dai-cells = <0>; 438 status = "disabled"; 439 }; 440 441 ssi1: ssi@100a8400 { 442 compatible = "renesas,r9a08g045-ssi", 443 "renesas,rz-ssi"; 444 reg = <0 0x100a8400 0 0x400>; 445 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>, 447 <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>; 448 interrupt-names = "int_req", "dma_rx", "dma_tx"; 449 clocks = <&cpg CPG_MOD R9A08G045_SSI1_PCLK2>, 450 <&cpg CPG_MOD R9A08G045_SSI1_PCLK_SFR>, 451 <&audio_clk1>, <&audio_clk2>; 452 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 453 resets = <&cpg R9A08G045_SSI1_RST_M2_REG>; 454 dmas = <&dmac 0x2669>, <&dmac 0x266a>; 455 dma-names = "tx", "rx"; 456 power-domains = <&cpg>; 457 #sound-dai-cells = <0>; 458 status = "disabled"; 459 }; 460 461 ssi2: ssi@100a8800 { 462 compatible = "renesas,r9a08g045-ssi", 463 "renesas,rz-ssi"; 464 reg = <0 0x100a8800 0 0x400>; 465 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>, 467 <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>; 468 interrupt-names = "int_req", "dma_rx", "dma_tx"; 469 clocks = <&cpg CPG_MOD R9A08G045_SSI2_PCLK2>, 470 <&cpg CPG_MOD R9A08G045_SSI2_PCLK_SFR>, 471 <&audio_clk1>, <&audio_clk2>; 472 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 473 resets = <&cpg R9A08G045_SSI2_RST_M2_REG>; 474 dmas = <&dmac 0x266d>, <&dmac 0x266e>; 475 dma-names = "tx", "rx"; 476 power-domains = <&cpg>; 477 #sound-dai-cells = <0>; 478 status = "disabled"; 479 }; 480 481 ssi3: ssi@100a8c00 { 482 compatible = "renesas,r9a08g045-ssi", 483 "renesas,rz-ssi"; 484 reg = <0 0x100a8c00 0 0x400>; 485 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, 487 <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>; 488 interrupt-names = "int_req", "dma_rx", "dma_tx"; 489 clocks = <&cpg CPG_MOD R9A08G045_SSI3_PCLK2>, 490 <&cpg CPG_MOD R9A08G045_SSI3_PCLK_SFR>, 491 <&audio_clk1>, <&audio_clk2>; 492 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 493 resets = <&cpg R9A08G045_SSI3_RST_M2_REG>; 494 dmas = <&dmac 0x2671>, <&dmac 0x2672>; 495 dma-names = "tx", "rx"; 496 power-domains = <&cpg>; 497 #sound-dai-cells = <0>; 498 status = "disabled"; 499 }; 500 501 cpg: clock-controller@11010000 { 502 compatible = "renesas,r9a08g045-cpg"; 503 reg = <0 0x11010000 0 0x10000>; 504 clocks = <&extal_clk>; 505 clock-names = "extal"; 506 #clock-cells = <2>; 507 #reset-cells = <1>; 508 #power-domain-cells = <0>; 509 }; 510 511 sysc: system-controller@11020000 { 512 compatible = "renesas,r9a08g045-sysc"; 513 reg = <0 0x11020000 0 0x10000>; 514 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 518 interrupt-names = "lpm_int", "ca55stbydone_int", 519 "cm33stbyr_int", "ca55_deny"; 520 }; 521 522 pinctrl: pinctrl@11030000 { 523 compatible = "renesas,r9a08g045-pinctrl"; 524 reg = <0 0x11030000 0 0x10000>; 525 gpio-controller; 526 #gpio-cells = <2>; 527 interrupt-controller; 528 #interrupt-cells = <2>; 529 interrupt-parent = <&irqc>; 530 gpio-ranges = <&pinctrl 0 0 152>; 531 clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>; 532 power-domains = <&cpg>; 533 resets = <&cpg R9A08G045_GPIO_RSTN>, 534 <&cpg R9A08G045_GPIO_PORT_RESETN>, 535 <&cpg R9A08G045_GPIO_SPARE_RESETN>; 536 }; 537 538 irqc: interrupt-controller@11050000 { 539 compatible = "renesas,r9a08g045-irqc", "renesas,rzg2l-irqc"; 540 #interrupt-cells = <2>; 541 #address-cells = <0>; 542 interrupt-controller; 543 reg = <0 0x11050000 0 0x10000>; 544 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 549 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 552 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, 564 <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, 565 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 589 interrupt-names = "nmi", 590 "irq0", "irq1", "irq2", "irq3", 591 "irq4", "irq5", "irq6", "irq7", 592 "tint0", "tint1", "tint2", "tint3", 593 "tint4", "tint5", "tint6", "tint7", 594 "tint8", "tint9", "tint10", "tint11", 595 "tint12", "tint13", "tint14", "tint15", 596 "tint16", "tint17", "tint18", "tint19", 597 "tint20", "tint21", "tint22", "tint23", 598 "tint24", "tint25", "tint26", "tint27", 599 "tint28", "tint29", "tint30", "tint31", 600 "bus-err", "ec7tie1-0", "ec7tie2-0", 601 "ec7tiovf-0"; 602 clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>, 603 <&cpg CPG_MOD R9A08G045_IA55_PCLK>; 604 clock-names = "clk", "pclk"; 605 power-domains = <&cpg>; 606 resets = <&cpg R9A08G045_IA55_RESETN>; 607 }; 608 609 dmac: dma-controller@11820000 { 610 compatible = "renesas,r9a08g045-dmac", 611 "renesas,rz-dmac"; 612 reg = <0 0x11820000 0 0x10000>, 613 <0 0x11830000 0 0x10000>; 614 interrupts = <GIC_SPI 111 IRQ_TYPE_EDGE_RISING>, 615 <GIC_SPI 112 IRQ_TYPE_EDGE_RISING>, 616 <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>, 617 <GIC_SPI 114 IRQ_TYPE_EDGE_RISING>, 618 <GIC_SPI 115 IRQ_TYPE_EDGE_RISING>, 619 <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>, 620 <GIC_SPI 117 IRQ_TYPE_EDGE_RISING>, 621 <GIC_SPI 118 IRQ_TYPE_EDGE_RISING>, 622 <GIC_SPI 119 IRQ_TYPE_EDGE_RISING>, 623 <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>, 624 <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>, 625 <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, 626 <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>, 627 <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>, 628 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>, 629 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>, 630 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>; 631 interrupt-names = "error", 632 "ch0", "ch1", "ch2", "ch3", 633 "ch4", "ch5", "ch6", "ch7", 634 "ch8", "ch9", "ch10", "ch11", 635 "ch12", "ch13", "ch14", "ch15"; 636 clocks = <&cpg CPG_MOD R9A08G045_DMAC_ACLK>, 637 <&cpg CPG_MOD R9A08G045_DMAC_PCLK>; 638 clock-names = "main", "register"; 639 power-domains = <&cpg>; 640 resets = <&cpg R9A08G045_DMAC_ARESETN>, 641 <&cpg R9A08G045_DMAC_RST_ASYNC>; 642 reset-names = "arst", "rst_async"; 643 #dma-cells = <1>; 644 dma-channels = <16>; 645 }; 646 647 sdhi0: mmc@11c00000 { 648 compatible = "renesas,sdhi-r9a08g045", "renesas,rzg2l-sdhi"; 649 reg = <0x0 0x11c00000 0 0x10000>; 650 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 651 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 652 clocks = <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK>, 653 <&cpg CPG_MOD R9A08G045_SDHI0_CLK_HS>, 654 <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK2>, 655 <&cpg CPG_MOD R9A08G045_SDHI0_ACLK>; 656 clock-names = "core", "clkh", "cd", "aclk"; 657 resets = <&cpg R9A08G045_SDHI0_IXRST>; 658 power-domains = <&cpg>; 659 status = "disabled"; 660 }; 661 662 sdhi1: mmc@11c10000 { 663 compatible = "renesas,sdhi-r9a08g045", "renesas,rzg2l-sdhi"; 664 reg = <0x0 0x11c10000 0 0x10000>; 665 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 666 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 667 clocks = <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK>, 668 <&cpg CPG_MOD R9A08G045_SDHI1_CLK_HS>, 669 <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK2>, 670 <&cpg CPG_MOD R9A08G045_SDHI1_ACLK>; 671 clock-names = "core", "clkh", "cd", "aclk"; 672 resets = <&cpg R9A08G045_SDHI1_IXRST>; 673 power-domains = <&cpg>; 674 status = "disabled"; 675 }; 676 677 sdhi2: mmc@11c20000 { 678 compatible = "renesas,sdhi-r9a08g045", "renesas,rzg2l-sdhi"; 679 reg = <0x0 0x11c20000 0 0x10000>; 680 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 681 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 682 clocks = <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK>, 683 <&cpg CPG_MOD R9A08G045_SDHI2_CLK_HS>, 684 <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK2>, 685 <&cpg CPG_MOD R9A08G045_SDHI2_ACLK>; 686 clock-names = "core", "clkh", "cd", "aclk"; 687 resets = <&cpg R9A08G045_SDHI2_IXRST>; 688 power-domains = <&cpg>; 689 status = "disabled"; 690 }; 691 692 eth0: ethernet@11c30000 { 693 compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth"; 694 reg = <0 0x11c30000 0 0x10000>; 695 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 696 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 697 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 698 interrupt-names = "mux", "fil", "arp_ns"; 699 phy-mode = "rgmii"; 700 clocks = <&cpg CPG_MOD R9A08G045_ETH0_CLK_AXI>, 701 <&cpg CPG_MOD R9A08G045_ETH0_CLK_CHI>, 702 <&cpg CPG_MOD R9A08G045_ETH0_REFCLK>; 703 clock-names = "axi", "chi", "refclk"; 704 resets = <&cpg R9A08G045_ETH0_RST_HW_N>; 705 power-domains = <&cpg>; 706 #address-cells = <1>; 707 #size-cells = <0>; 708 status = "disabled"; 709 }; 710 711 eth1: ethernet@11c40000 { 712 compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth"; 713 reg = <0 0x11c40000 0 0x10000>; 714 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 715 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 716 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 717 interrupt-names = "mux", "fil", "arp_ns"; 718 phy-mode = "rgmii"; 719 clocks = <&cpg CPG_MOD R9A08G045_ETH1_CLK_AXI>, 720 <&cpg CPG_MOD R9A08G045_ETH1_CLK_CHI>, 721 <&cpg CPG_MOD R9A08G045_ETH1_REFCLK>; 722 clock-names = "axi", "chi", "refclk"; 723 resets = <&cpg R9A08G045_ETH1_RST_HW_N>; 724 power-domains = <&cpg>; 725 #address-cells = <1>; 726 #size-cells = <0>; 727 status = "disabled"; 728 }; 729 730 phyrst: usbphy-ctrl@11e00000 { 731 compatible = "renesas,r9a08g045-usbphy-ctrl"; 732 reg = <0 0x11e00000 0 0x10000>; 733 clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>; 734 resets = <&cpg R9A08G045_USB_PRESETN>; 735 power-domains = <&cpg>; 736 #reset-cells = <1>; 737 renesas,sysc-pwrrdy = <&sysc 0xd70 0x1>; 738 status = "disabled"; 739 740 usb0_vbus_otg: regulator-vbus { 741 regulator-name = "vbus"; 742 }; 743 }; 744 745 ohci0: usb@11e10000 { 746 compatible = "generic-ohci"; 747 reg = <0 0x11e10000 0 0x100>; 748 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 749 clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>, 750 <&cpg CPG_MOD R9A08G045_USB_U2H0_HCLK>; 751 resets = <&phyrst 0>, 752 <&cpg R9A08G045_USB_U2H0_HRESETN>; 753 phys = <&usb2_phy0 1>; 754 phy-names = "usb"; 755 power-domains = <&cpg>; 756 status = "disabled"; 757 }; 758 759 ohci1: usb@11e30000 { 760 compatible = "generic-ohci"; 761 reg = <0 0x11e30000 0 0x100>; 762 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 763 clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>, 764 <&cpg CPG_MOD R9A08G045_USB_U2H1_HCLK>; 765 resets = <&phyrst 1>, 766 <&cpg R9A08G045_USB_U2H1_HRESETN>; 767 phys = <&usb2_phy1 1>; 768 phy-names = "usb"; 769 power-domains = <&cpg>; 770 status = "disabled"; 771 }; 772 773 ehci0: usb@11e10100 { 774 compatible = "generic-ehci"; 775 reg = <0 0x11e10100 0 0x100>; 776 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 777 clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>, 778 <&cpg CPG_MOD R9A08G045_USB_U2H0_HCLK>; 779 resets = <&phyrst 0>, 780 <&cpg R9A08G045_USB_U2H0_HRESETN>; 781 phys = <&usb2_phy0 2>; 782 phy-names = "usb"; 783 companion = <&ohci0>; 784 power-domains = <&cpg>; 785 status = "disabled"; 786 }; 787 788 ehci1: usb@11e30100 { 789 compatible = "generic-ehci"; 790 reg = <0 0x11e30100 0 0x100>; 791 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 792 clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>, 793 <&cpg CPG_MOD R9A08G045_USB_U2H1_HCLK>; 794 resets = <&phyrst 1>, 795 <&cpg R9A08G045_USB_U2H1_HRESETN>; 796 phys = <&usb2_phy1 2>; 797 phy-names = "usb"; 798 companion = <&ohci1>; 799 power-domains = <&cpg>; 800 status = "disabled"; 801 }; 802 803 usb2_phy0: usb-phy@11e10200 { 804 compatible = "renesas,usb2-phy-r9a08g045"; 805 reg = <0 0x11e10200 0 0x700>; 806 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 807 clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>, 808 <&cpg CPG_MOD R9A08G045_USB_U2H0_HCLK>; 809 resets = <&phyrst 0>, 810 <&cpg R9A08G045_USB_U2H0_HRESETN>; 811 #phy-cells = <1>; 812 power-domains = <&cpg>; 813 status = "disabled"; 814 }; 815 816 usb2_phy1: usb-phy@11e30200 { 817 compatible = "renesas,usb2-phy-r9a08g045"; 818 reg = <0 0x11e30200 0 0x700>; 819 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 820 clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>, 821 <&cpg CPG_MOD R9A08G045_USB_U2H1_HCLK>; 822 resets = <&phyrst 1>, 823 <&cpg R9A08G045_USB_U2H1_HRESETN>; 824 #phy-cells = <1>; 825 power-domains = <&cpg>; 826 status = "disabled"; 827 }; 828 829 hsusb: usb@11e20000 { 830 compatible = "renesas,usbhs-r9a08g045", 831 "renesas,rzg2l-usbhs"; 832 reg = <0 0x11e20000 0 0x10000>; 833 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>, 834 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 835 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 836 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 837 clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>, 838 <&cpg CPG_MOD R9A08G045_USB_U2P_EXR_CPUCLK>; 839 resets = <&phyrst 0>, 840 <&cpg R9A08G045_USB_U2P_EXL_SYSRST>; 841 renesas,buswait = <7>; 842 phys = <&usb2_phy0 3>; 843 phy-names = "usb"; 844 power-domains = <&cpg>; 845 status = "disabled"; 846 }; 847 848 pcie: pcie@11e40000 { 849 compatible = "renesas,r9a08g045-pcie"; 850 reg = <0 0x11e40000 0 0x10000>; 851 ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>; 852 /* Map all possible DRAM ranges (4 GB). */ 853 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 1 0x00000000>; 854 bus-range = <0x0 0xff>; 855 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 856 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 857 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 858 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 859 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 860 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 861 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 862 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 863 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 864 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 865 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 866 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 867 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 868 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 869 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 870 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>; 871 interrupt-names = "serr", "serr_cor", "serr_nonfatal", 872 "serr_fatal", "axi_err", "inta", 873 "intb", "intc", "intd", "msi", 874 "link_bandwidth", "pm_pme", "dma", 875 "pcie_evt", "msg", "all"; 876 #interrupt-cells = <1>; 877 interrupt-controller; 878 interrupt-map-mask = <0 0 0 7>; 879 interrupt-map = <0 0 0 1 &pcie 0 0 0 0>, /* INTA */ 880 <0 0 0 2 &pcie 0 0 0 1>, /* INTB */ 881 <0 0 0 3 &pcie 0 0 0 2>, /* INTC */ 882 <0 0 0 4 &pcie 0 0 0 3>; /* INTD */ 883 clocks = <&cpg CPG_MOD R9A08G045_PCI_ACLK>, 884 <&cpg CPG_MOD R9A08G045_PCI_CLKL1PM>; 885 clock-names = "aclk", "pm"; 886 resets = <&cpg R9A08G045_PCI_ARESETN>, 887 <&cpg R9A08G045_PCI_RST_B>, 888 <&cpg R9A08G045_PCI_RST_GP_B>, 889 <&cpg R9A08G045_PCI_RST_PS_B>, 890 <&cpg R9A08G045_PCI_RST_RSM_B>, 891 <&cpg R9A08G045_PCI_RST_CFG_B>, 892 <&cpg R9A08G045_PCI_RST_LOAD_B>; 893 reset-names = "aresetn", "rst_b", "rst_gp_b", "rst_ps_b", 894 "rst_rsm_b", "rst_cfg_b", "rst_load_b"; 895 power-domains = <&cpg>; 896 device_type = "pci"; 897 #address-cells = <3>; 898 #size-cells = <2>; 899 renesas,sysc = <&sysc>; 900 status = "disabled"; 901 902 pcie_port0: pcie@0,0 { 903 reg = <0x0 0x0 0x0 0x0 0x0>; 904 ranges; 905 device_type = "pci"; 906 vendor-id = <0x1912>; 907 device-id = <0x0033>; 908 #address-cells = <3>; 909 #size-cells = <2>; 910 }; 911 }; 912 913 gic: interrupt-controller@12400000 { 914 compatible = "arm,gic-v3"; 915 #interrupt-cells = <3>; 916 #address-cells = <0>; 917 interrupt-controller; 918 reg = <0x0 0x12400000 0 0x20000>, 919 <0x0 0x12440000 0 0x40000>; 920 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 921 }; 922 923 wdt0: watchdog@12800800 { 924 compatible = "renesas,r9a08g045-wdt", "renesas,rzg2l-wdt"; 925 reg = <0 0x12800800 0 0x400>; 926 clocks = <&cpg CPG_MOD R9A08G045_WDT0_PCLK>, 927 <&cpg CPG_MOD R9A08G045_WDT0_CLK>; 928 clock-names = "pclk", "oscclk"; 929 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 931 interrupt-names = "wdt", "perrout"; 932 resets = <&cpg R9A08G045_WDT0_PRESETN>; 933 power-domains = <&cpg>; 934 status = "disabled"; 935 }; 936 }; 937 938 timer { 939 compatible = "arm,armv8-timer"; 940 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 941 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 942 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 943 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 944 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 945 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", 946 "hyp-virt"; 947 }; 948 949 thermal-zones { 950 cpu_thermal: cpu-thermal { 951 polling-delay-passive = <250>; 952 polling-delay = <1000>; 953 thermal-sensors = <&tsu>; 954 sustainable-power = <423>; 955 956 cooling-maps { 957 map0 { 958 trip = <&cpu_alert0>; 959 cooling-device = <&cpu0 0 2>; 960 contribution = <1024>; 961 }; 962 }; 963 964 trips { 965 cpu_crit: cpu-critical { 966 temperature = <110000>; 967 hysteresis = <1000>; 968 type = "critical"; 969 }; 970 971 cpu_alert1: trip-point1 { 972 temperature = <90000>; 973 hysteresis = <1000>; 974 type = "passive"; 975 }; 976 977 cpu_alert0: trip-point0 { 978 temperature = <85000>; 979 hysteresis = <1000>; 980 type = "passive"; 981 }; 982 }; 983 }; 984 }; 985 986 vbattb_xtal: vbattb-xtal { 987 compatible = "fixed-clock"; 988 #clock-cells = <0>; 989 /* This value must be overridden by the board. */ 990 clock-frequency = <0>; 991 }; 992}; 993