1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * x86 instruction analysis 4 * 5 * Copyright (C) IBM Corporation, 2002, 2004, 2009 6 */ 7 8 #include <linux/kernel.h> 9 #ifdef __KERNEL__ 10 #include <linux/string.h> 11 #else 12 #include <string.h> 13 #endif 14 #include "../include/asm/inat.h" /* __ignore_sync_check__ */ 15 #include "../include/asm/insn.h" /* __ignore_sync_check__ */ 16 #include <linux/unaligned.h> /* __ignore_sync_check__ */ 17 18 #include <linux/errno.h> 19 #include <linux/kconfig.h> 20 21 #include "../include/asm/emulate_prefix.h" /* __ignore_sync_check__ */ 22 23 #define leXX_to_cpu(t, r) \ 24 ({ \ 25 __typeof__(t) v; \ 26 switch (sizeof(t)) { \ 27 case 4: v = le32_to_cpu(r); break; \ 28 case 2: v = le16_to_cpu(r); break; \ 29 case 1: v = r; break; \ 30 default: \ 31 BUILD_BUG(); break; \ 32 } \ 33 v; \ 34 }) 35 36 /* Verify next sizeof(t) bytes can be on the same instruction */ 37 #define validate_next(t, insn, n) \ 38 ((insn)->next_byte + sizeof(t) + n <= (insn)->end_kaddr) 39 40 #define __get_next(t, insn) \ 41 ({ t r = get_unaligned((t *)(insn)->next_byte); (insn)->next_byte += sizeof(t); leXX_to_cpu(t, r); }) 42 43 #define __peek_nbyte_next(t, insn, n) \ 44 ({ t r = get_unaligned((t *)(insn)->next_byte + n); leXX_to_cpu(t, r); }) 45 46 #define get_next(t, insn) \ 47 ({ if (unlikely(!validate_next(t, insn, 0))) goto err_out; __get_next(t, insn); }) 48 49 #define peek_nbyte_next(t, insn, n) \ 50 ({ if (unlikely(!validate_next(t, insn, n))) goto err_out; __peek_nbyte_next(t, insn, n); }) 51 52 #define peek_next(t, insn) peek_nbyte_next(t, insn, 0) 53 54 /** 55 * insn_init() - initialize struct insn 56 * @insn: &struct insn to be initialized 57 * @kaddr: address (in kernel memory) of instruction (or copy thereof) 58 * @buf_len: length of the insn buffer at @kaddr 59 * @x86_64: !0 for 64-bit kernel or 64-bit app 60 */ 61 void insn_init(struct insn *insn, const void *kaddr, int buf_len, int x86_64) 62 { 63 /* 64 * Instructions longer than MAX_INSN_SIZE (15 bytes) are invalid 65 * even if the input buffer is long enough to hold them. 66 */ 67 if (buf_len > MAX_INSN_SIZE) 68 buf_len = MAX_INSN_SIZE; 69 70 memset(insn, 0, sizeof(*insn)); 71 insn->kaddr = kaddr; 72 insn->end_kaddr = kaddr + buf_len; 73 insn->next_byte = kaddr; 74 insn->x86_64 = x86_64; 75 insn->opnd_bytes = 4; 76 if (x86_64) 77 insn->addr_bytes = 8; 78 else 79 insn->addr_bytes = 4; 80 } 81 82 static const insn_byte_t xen_prefix[] = { __XEN_EMULATE_PREFIX }; 83 static const insn_byte_t kvm_prefix[] = { __KVM_EMULATE_PREFIX }; 84 85 static int __insn_get_emulate_prefix(struct insn *insn, 86 const insn_byte_t *prefix, size_t len) 87 { 88 size_t i; 89 90 for (i = 0; i < len; i++) { 91 if (peek_nbyte_next(insn_byte_t, insn, i) != prefix[i]) 92 goto err_out; 93 } 94 95 insn->emulate_prefix_size = len; 96 insn->next_byte += len; 97 98 return 1; 99 100 err_out: 101 return 0; 102 } 103 104 static void insn_get_emulate_prefix(struct insn *insn) 105 { 106 if (__insn_get_emulate_prefix(insn, xen_prefix, sizeof(xen_prefix))) 107 return; 108 109 __insn_get_emulate_prefix(insn, kvm_prefix, sizeof(kvm_prefix)); 110 } 111 112 /** 113 * insn_get_prefixes - scan x86 instruction prefix bytes 114 * @insn: &struct insn containing instruction 115 * 116 * Populates the @insn->prefixes bitmap, and updates @insn->next_byte 117 * to point to the (first) opcode. No effect if @insn->prefixes.got 118 * is already set. 119 * 120 * * Returns: 121 * 0: on success 122 * < 0: on error 123 */ 124 int insn_get_prefixes(struct insn *insn) 125 { 126 struct insn_field *prefixes = &insn->prefixes; 127 insn_attr_t attr; 128 insn_byte_t b, lb; 129 int i, nb; 130 131 if (prefixes->got) 132 return 0; 133 134 insn_get_emulate_prefix(insn); 135 136 nb = 0; 137 lb = 0; 138 b = peek_next(insn_byte_t, insn); 139 attr = inat_get_opcode_attribute(b); 140 while (inat_is_legacy_prefix(attr)) { 141 /* Skip if same prefix */ 142 for (i = 0; i < nb; i++) 143 if (prefixes->bytes[i] == b) 144 goto found; 145 if (nb == 4) 146 /* Invalid instruction */ 147 break; 148 prefixes->bytes[nb++] = b; 149 if (inat_is_address_size_prefix(attr)) { 150 /* address size switches 2/4 or 4/8 */ 151 if (insn->x86_64) 152 insn->addr_bytes ^= 12; 153 else 154 insn->addr_bytes ^= 6; 155 } else if (inat_is_operand_size_prefix(attr)) { 156 /* oprand size switches 2/4 */ 157 insn->opnd_bytes ^= 6; 158 } 159 found: 160 prefixes->nbytes++; 161 insn->next_byte++; 162 lb = b; 163 b = peek_next(insn_byte_t, insn); 164 attr = inat_get_opcode_attribute(b); 165 } 166 /* Set the last prefix */ 167 if (lb && lb != insn->prefixes.bytes[3]) { 168 if (unlikely(insn->prefixes.bytes[3])) { 169 /* Swap the last prefix */ 170 b = insn->prefixes.bytes[3]; 171 for (i = 0; i < nb; i++) 172 if (prefixes->bytes[i] == lb) 173 insn_set_byte(prefixes, i, b); 174 } 175 insn_set_byte(&insn->prefixes, 3, lb); 176 } 177 178 /* Decode REX prefix */ 179 if (insn->x86_64) { 180 b = peek_next(insn_byte_t, insn); 181 attr = inat_get_opcode_attribute(b); 182 if (inat_is_rex_prefix(attr)) { 183 insn_field_set(&insn->rex_prefix, b, 1); 184 insn->next_byte++; 185 if (X86_REX_W(b)) 186 /* REX.W overrides opnd_size */ 187 insn->opnd_bytes = 8; 188 } else if (inat_is_rex2_prefix(attr)) { 189 insn_set_byte(&insn->rex_prefix, 0, b); 190 b = peek_nbyte_next(insn_byte_t, insn, 1); 191 insn_set_byte(&insn->rex_prefix, 1, b); 192 insn->rex_prefix.nbytes = 2; 193 insn->next_byte += 2; 194 if (X86_REX_W(b)) 195 /* REX.W overrides opnd_size */ 196 insn->opnd_bytes = 8; 197 insn->rex_prefix.got = 1; 198 goto vex_end; 199 } 200 } 201 insn->rex_prefix.got = 1; 202 203 /* Decode VEX prefix */ 204 b = peek_next(insn_byte_t, insn); 205 attr = inat_get_opcode_attribute(b); 206 if (inat_is_vex_prefix(attr)) { 207 insn_byte_t b2 = peek_nbyte_next(insn_byte_t, insn, 1); 208 if (!insn->x86_64) { 209 /* 210 * In 32-bits mode, if the [7:6] bits (mod bits of 211 * ModRM) on the second byte are not 11b, it is 212 * LDS or LES or BOUND. 213 */ 214 if (X86_MODRM_MOD(b2) != 3) 215 goto vex_end; 216 } 217 insn_set_byte(&insn->vex_prefix, 0, b); 218 insn_set_byte(&insn->vex_prefix, 1, b2); 219 if (inat_is_evex_prefix(attr)) { 220 b2 = peek_nbyte_next(insn_byte_t, insn, 2); 221 insn_set_byte(&insn->vex_prefix, 2, b2); 222 b2 = peek_nbyte_next(insn_byte_t, insn, 3); 223 insn_set_byte(&insn->vex_prefix, 3, b2); 224 insn->vex_prefix.nbytes = 4; 225 insn->next_byte += 4; 226 if (insn->x86_64 && X86_VEX_W(b2)) 227 /* VEX.W overrides opnd_size */ 228 insn->opnd_bytes = 8; 229 } else if (inat_is_vex3_prefix(attr)) { 230 b2 = peek_nbyte_next(insn_byte_t, insn, 2); 231 insn_set_byte(&insn->vex_prefix, 2, b2); 232 insn->vex_prefix.nbytes = 3; 233 insn->next_byte += 3; 234 if (insn->x86_64 && X86_VEX_W(b2)) 235 /* VEX.W overrides opnd_size */ 236 insn->opnd_bytes = 8; 237 } else { 238 /* 239 * For VEX2, fake VEX3-like byte#2. 240 * Makes it easier to decode vex.W, vex.vvvv, 241 * vex.L and vex.pp. Masking with 0x7f sets vex.W == 0. 242 */ 243 insn_set_byte(&insn->vex_prefix, 2, b2 & 0x7f); 244 insn->vex_prefix.nbytes = 2; 245 insn->next_byte += 2; 246 } 247 } 248 vex_end: 249 insn->vex_prefix.got = 1; 250 251 prefixes->got = 1; 252 253 return 0; 254 255 err_out: 256 return -ENODATA; 257 } 258 259 /** 260 * insn_get_opcode - collect opcode(s) 261 * @insn: &struct insn containing instruction 262 * 263 * Populates @insn->opcode, updates @insn->next_byte to point past the 264 * opcode byte(s), and set @insn->attr (except for groups). 265 * If necessary, first collects any preceding (prefix) bytes. 266 * Sets @insn->opcode.value = opcode1. No effect if @insn->opcode.got 267 * is already 1. 268 * 269 * Returns: 270 * 0: on success 271 * < 0: on error 272 */ 273 int insn_get_opcode(struct insn *insn) 274 { 275 struct insn_field *opcode = &insn->opcode; 276 int pfx_id, ret; 277 insn_byte_t op; 278 279 if (opcode->got) 280 return 0; 281 282 ret = insn_get_prefixes(insn); 283 if (ret) 284 return ret; 285 286 /* Get first opcode */ 287 op = get_next(insn_byte_t, insn); 288 insn_set_byte(opcode, 0, op); 289 opcode->nbytes = 1; 290 291 /* Check if there is VEX prefix or not */ 292 if (insn_is_avx(insn)) { 293 insn_byte_t m, p; 294 m = insn_vex_m_bits(insn); 295 p = insn_vex_p_bits(insn); 296 insn->attr = inat_get_avx_attribute(op, m, p); 297 /* SCALABLE EVEX uses p bits to encode operand size */ 298 if (inat_evex_scalable(insn->attr) && !insn_vex_w_bit(insn) && 299 p == INAT_PFX_OPNDSZ) 300 insn->opnd_bytes = 2; 301 if ((inat_must_evex(insn->attr) && !insn_is_evex(insn)) || 302 (!inat_accept_vex(insn->attr) && 303 !inat_is_group(insn->attr))) { 304 /* This instruction is bad */ 305 insn->attr = 0; 306 return -EINVAL; 307 } 308 /* VEX has only 1 byte for opcode */ 309 goto end; 310 } 311 312 /* Check if there is REX2 prefix or not */ 313 if (insn_is_rex2(insn)) { 314 if (insn_rex2_m_bit(insn)) { 315 /* map 1 is escape 0x0f */ 316 insn_attr_t esc_attr = inat_get_opcode_attribute(0x0f); 317 318 pfx_id = insn_last_prefix_id(insn); 319 insn->attr = inat_get_escape_attribute(op, pfx_id, esc_attr); 320 } else { 321 insn->attr = inat_get_opcode_attribute(op); 322 } 323 goto end; 324 } 325 326 insn->attr = inat_get_opcode_attribute(op); 327 if (insn->x86_64 && inat_is_invalid64(insn->attr)) { 328 /* This instruction is invalid, like UD2. Stop decoding. */ 329 insn->attr &= INAT_INV64; 330 } 331 332 while (inat_is_escape(insn->attr)) { 333 /* Get escaped opcode */ 334 op = get_next(insn_byte_t, insn); 335 opcode->bytes[opcode->nbytes++] = op; 336 pfx_id = insn_last_prefix_id(insn); 337 insn->attr = inat_get_escape_attribute(op, pfx_id, insn->attr); 338 } 339 340 if (inat_must_vex(insn->attr)) { 341 /* This instruction is bad */ 342 insn->attr = 0; 343 return -EINVAL; 344 } 345 346 end: 347 opcode->got = 1; 348 return 0; 349 350 err_out: 351 return -ENODATA; 352 } 353 354 /** 355 * insn_get_modrm - collect ModRM byte, if any 356 * @insn: &struct insn containing instruction 357 * 358 * Populates @insn->modrm and updates @insn->next_byte to point past the 359 * ModRM byte, if any. If necessary, first collects the preceding bytes 360 * (prefixes and opcode(s)). No effect if @insn->modrm.got is already 1. 361 * 362 * Returns: 363 * 0: on success 364 * < 0: on error 365 */ 366 int insn_get_modrm(struct insn *insn) 367 { 368 struct insn_field *modrm = &insn->modrm; 369 insn_byte_t pfx_id, mod; 370 int ret; 371 372 if (modrm->got) 373 return 0; 374 375 ret = insn_get_opcode(insn); 376 if (ret) 377 return ret; 378 379 if (inat_has_modrm(insn->attr)) { 380 mod = get_next(insn_byte_t, insn); 381 insn_field_set(modrm, mod, 1); 382 if (inat_is_group(insn->attr)) { 383 pfx_id = insn_last_prefix_id(insn); 384 insn->attr = inat_get_group_attribute(mod, pfx_id, 385 insn->attr); 386 if (insn_is_avx(insn) && !inat_accept_vex(insn->attr)) { 387 /* Bad insn */ 388 insn->attr = 0; 389 return -EINVAL; 390 } 391 } 392 } 393 394 if (insn->x86_64 && inat_is_force64(insn->attr)) 395 insn->opnd_bytes = 8; 396 397 modrm->got = 1; 398 return 0; 399 400 err_out: 401 return -ENODATA; 402 } 403 404 405 /** 406 * insn_rip_relative() - Does instruction use RIP-relative addressing mode? 407 * @insn: &struct insn containing instruction 408 * 409 * If necessary, first collects the instruction up to and including the 410 * ModRM byte. No effect if @insn->x86_64 is 0. 411 */ 412 int insn_rip_relative(struct insn *insn) 413 { 414 struct insn_field *modrm = &insn->modrm; 415 int ret; 416 417 if (!insn->x86_64) 418 return 0; 419 420 ret = insn_get_modrm(insn); 421 if (ret) 422 return 0; 423 /* 424 * For rip-relative instructions, the mod field (top 2 bits) 425 * is zero and the r/m field (bottom 3 bits) is 0x5. 426 */ 427 return (modrm->nbytes && (modrm->bytes[0] & 0xc7) == 0x5); 428 } 429 430 /** 431 * insn_get_sib() - Get the SIB byte of instruction 432 * @insn: &struct insn containing instruction 433 * 434 * If necessary, first collects the instruction up to and including the 435 * ModRM byte. 436 * 437 * Returns: 438 * 0: if decoding succeeded 439 * < 0: otherwise. 440 */ 441 int insn_get_sib(struct insn *insn) 442 { 443 insn_byte_t modrm; 444 int ret; 445 446 if (insn->sib.got) 447 return 0; 448 449 ret = insn_get_modrm(insn); 450 if (ret) 451 return ret; 452 453 if (insn->modrm.nbytes) { 454 modrm = insn->modrm.bytes[0]; 455 if (insn->addr_bytes != 2 && 456 X86_MODRM_MOD(modrm) != 3 && X86_MODRM_RM(modrm) == 4) { 457 insn_field_set(&insn->sib, 458 get_next(insn_byte_t, insn), 1); 459 } 460 } 461 insn->sib.got = 1; 462 463 return 0; 464 465 err_out: 466 return -ENODATA; 467 } 468 469 470 /** 471 * insn_get_displacement() - Get the displacement of instruction 472 * @insn: &struct insn containing instruction 473 * 474 * If necessary, first collects the instruction up to and including the 475 * SIB byte. 476 * Displacement value is sign-expanded. 477 * 478 * * Returns: 479 * 0: if decoding succeeded 480 * < 0: otherwise. 481 */ 482 int insn_get_displacement(struct insn *insn) 483 { 484 insn_byte_t mod, rm, base; 485 int ret; 486 487 if (insn->displacement.got) 488 return 0; 489 490 ret = insn_get_sib(insn); 491 if (ret) 492 return ret; 493 494 if (insn->modrm.nbytes) { 495 /* 496 * Interpreting the modrm byte: 497 * mod = 00 - no displacement fields (exceptions below) 498 * mod = 01 - 1-byte displacement field 499 * mod = 10 - displacement field is 4 bytes, or 2 bytes if 500 * address size = 2 (0x67 prefix in 32-bit mode) 501 * mod = 11 - no memory operand 502 * 503 * If address size = 2... 504 * mod = 00, r/m = 110 - displacement field is 2 bytes 505 * 506 * If address size != 2... 507 * mod != 11, r/m = 100 - SIB byte exists 508 * mod = 00, SIB base = 101 - displacement field is 4 bytes 509 * mod = 00, r/m = 101 - rip-relative addressing, displacement 510 * field is 4 bytes 511 */ 512 mod = X86_MODRM_MOD(insn->modrm.value); 513 rm = X86_MODRM_RM(insn->modrm.value); 514 base = X86_SIB_BASE(insn->sib.value); 515 if (mod == 3) 516 goto out; 517 if (mod == 1) { 518 insn_field_set(&insn->displacement, 519 get_next(signed char, insn), 1); 520 } else if (insn->addr_bytes == 2) { 521 if ((mod == 0 && rm == 6) || mod == 2) { 522 insn_field_set(&insn->displacement, 523 get_next(short, insn), 2); 524 } 525 } else { 526 if ((mod == 0 && rm == 5) || mod == 2 || 527 (mod == 0 && base == 5)) { 528 insn_field_set(&insn->displacement, 529 get_next(int, insn), 4); 530 } 531 } 532 } 533 out: 534 insn->displacement.got = 1; 535 return 0; 536 537 err_out: 538 return -ENODATA; 539 } 540 541 /* Decode moffset16/32/64. Return 0 if failed */ 542 static int __get_moffset(struct insn *insn) 543 { 544 switch (insn->addr_bytes) { 545 case 2: 546 insn_field_set(&insn->moffset1, get_next(short, insn), 2); 547 break; 548 case 4: 549 insn_field_set(&insn->moffset1, get_next(int, insn), 4); 550 break; 551 case 8: 552 insn_field_set(&insn->moffset1, get_next(int, insn), 4); 553 insn_field_set(&insn->moffset2, get_next(int, insn), 4); 554 break; 555 default: /* opnd_bytes must be modified manually */ 556 goto err_out; 557 } 558 insn->moffset1.got = insn->moffset2.got = 1; 559 560 return 1; 561 562 err_out: 563 return 0; 564 } 565 566 /* Decode imm v32(Iz). Return 0 if failed */ 567 static int __get_immv32(struct insn *insn) 568 { 569 switch (insn->opnd_bytes) { 570 case 2: 571 insn_field_set(&insn->immediate, get_next(short, insn), 2); 572 break; 573 case 4: 574 case 8: 575 insn_field_set(&insn->immediate, get_next(int, insn), 4); 576 break; 577 default: /* opnd_bytes must be modified manually */ 578 goto err_out; 579 } 580 581 return 1; 582 583 err_out: 584 return 0; 585 } 586 587 /* Decode imm v64(Iv/Ov), Return 0 if failed */ 588 static int __get_immv(struct insn *insn) 589 { 590 switch (insn->opnd_bytes) { 591 case 2: 592 insn_field_set(&insn->immediate1, get_next(short, insn), 2); 593 break; 594 case 4: 595 insn_field_set(&insn->immediate1, get_next(int, insn), 4); 596 insn->immediate1.nbytes = 4; 597 break; 598 case 8: 599 insn_field_set(&insn->immediate1, get_next(int, insn), 4); 600 insn_field_set(&insn->immediate2, get_next(int, insn), 4); 601 break; 602 default: /* opnd_bytes must be modified manually */ 603 goto err_out; 604 } 605 insn->immediate1.got = insn->immediate2.got = 1; 606 607 return 1; 608 err_out: 609 return 0; 610 } 611 612 /* Decode ptr16:16/32(Ap) */ 613 static int __get_immptr(struct insn *insn) 614 { 615 switch (insn->opnd_bytes) { 616 case 2: 617 insn_field_set(&insn->immediate1, get_next(short, insn), 2); 618 break; 619 case 4: 620 insn_field_set(&insn->immediate1, get_next(int, insn), 4); 621 break; 622 case 8: 623 /* ptr16:64 is not exist (no segment) */ 624 return 0; 625 default: /* opnd_bytes must be modified manually */ 626 goto err_out; 627 } 628 insn_field_set(&insn->immediate2, get_next(unsigned short, insn), 2); 629 insn->immediate1.got = insn->immediate2.got = 1; 630 631 return 1; 632 err_out: 633 return 0; 634 } 635 636 /** 637 * insn_get_immediate() - Get the immediate in an instruction 638 * @insn: &struct insn containing instruction 639 * 640 * If necessary, first collects the instruction up to and including the 641 * displacement bytes. 642 * Basically, most of immediates are sign-expanded. Unsigned-value can be 643 * computed by bit masking with ((1 << (nbytes * 8)) - 1) 644 * 645 * Returns: 646 * 0: on success 647 * < 0: on error 648 */ 649 int insn_get_immediate(struct insn *insn) 650 { 651 int ret; 652 653 if (insn->immediate.got) 654 return 0; 655 656 ret = insn_get_displacement(insn); 657 if (ret) 658 return ret; 659 660 if (inat_has_moffset(insn->attr)) { 661 if (!__get_moffset(insn)) 662 goto err_out; 663 goto done; 664 } 665 666 if (!inat_has_immediate(insn->attr)) 667 goto done; 668 669 switch (inat_immediate_size(insn->attr)) { 670 case INAT_IMM_BYTE: 671 insn_field_set(&insn->immediate, get_next(signed char, insn), 1); 672 break; 673 case INAT_IMM_WORD: 674 insn_field_set(&insn->immediate, get_next(short, insn), 2); 675 break; 676 case INAT_IMM_DWORD: 677 insn_field_set(&insn->immediate, get_next(int, insn), 4); 678 break; 679 case INAT_IMM_QWORD: 680 insn_field_set(&insn->immediate1, get_next(int, insn), 4); 681 insn_field_set(&insn->immediate2, get_next(int, insn), 4); 682 break; 683 case INAT_IMM_PTR: 684 if (!__get_immptr(insn)) 685 goto err_out; 686 break; 687 case INAT_IMM_VWORD32: 688 if (!__get_immv32(insn)) 689 goto err_out; 690 break; 691 case INAT_IMM_VWORD: 692 if (!__get_immv(insn)) 693 goto err_out; 694 break; 695 default: 696 /* Here, insn must have an immediate, but failed */ 697 goto err_out; 698 } 699 if (inat_has_second_immediate(insn->attr)) { 700 insn_field_set(&insn->immediate2, get_next(signed char, insn), 1); 701 } 702 done: 703 insn->immediate.got = 1; 704 return 0; 705 706 err_out: 707 return -ENODATA; 708 } 709 710 /** 711 * insn_get_length() - Get the length of instruction 712 * @insn: &struct insn containing instruction 713 * 714 * If necessary, first collects the instruction up to and including the 715 * immediates bytes. 716 * 717 * Returns: 718 * - 0 on success 719 * - < 0 on error 720 */ 721 int insn_get_length(struct insn *insn) 722 { 723 int ret; 724 725 if (insn->length) 726 return 0; 727 728 ret = insn_get_immediate(insn); 729 if (ret) 730 return ret; 731 732 insn->length = (unsigned char)((unsigned long)insn->next_byte 733 - (unsigned long)insn->kaddr); 734 735 return 0; 736 } 737 738 /* Ensure this instruction is decoded completely */ 739 static inline int insn_complete(struct insn *insn) 740 { 741 return insn->opcode.got && insn->modrm.got && insn->sib.got && 742 insn->displacement.got && insn->immediate.got; 743 } 744 745 /** 746 * insn_decode() - Decode an x86 instruction 747 * @insn: &struct insn to be initialized 748 * @kaddr: address (in kernel memory) of instruction (or copy thereof) 749 * @buf_len: length of the insn buffer at @kaddr 750 * @m: insn mode, see enum insn_mode 751 * 752 * Returns: 753 * 0: if decoding succeeded 754 * < 0: otherwise. 755 */ 756 int insn_decode(struct insn *insn, const void *kaddr, int buf_len, enum insn_mode m) 757 { 758 int ret; 759 760 #define INSN_MODE_KERN (enum insn_mode)-1 /* __ignore_sync_check__ mode is only valid in the kernel */ 761 762 if (m == INSN_MODE_KERN) 763 insn_init(insn, kaddr, buf_len, IS_ENABLED(CONFIG_X86_64)); 764 else 765 insn_init(insn, kaddr, buf_len, m == INSN_MODE_64); 766 767 ret = insn_get_length(insn); 768 if (ret) 769 return ret; 770 771 if (insn_complete(insn)) 772 return 0; 773 774 return -EINVAL; 775 } 776