1 /*-
2 * Copyright (c) 2014 Andrew Turner
3 * Copyright (c) 2014 The FreeBSD Foundation
4 * All rights reserved.
5 *
6 * Portions of this software were developed by Semihalf
7 * under sponsorship of the FreeBSD Foundation.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 */
31
32 #include <sys/param.h>
33 #include <sys/kernel.h>
34 #include <sys/malloc.h>
35 #include <sys/proc.h>
36 #include <sys/pcpu.h>
37 #include <sys/sbuf.h>
38 #include <sys/smp.h>
39 #include <sys/sysctl.h>
40 #include <sys/sysent.h>
41 #include <sys/systm.h>
42
43 #include <machine/atomic.h>
44 #include <machine/cpu.h>
45 #include <machine/cpu_feat.h>
46 #include <machine/cpufunc.h>
47 #include <machine/elf.h>
48 #include <machine/md_var.h>
49 #include <machine/undefined.h>
50
51 static MALLOC_DEFINE(M_IDENTCPU, "CPU ID", "arm64 CPU identification memory");
52
53 struct cpu_desc;
54 #ifdef INVARIANTS
55 static bool hwcaps_set = false;
56 #endif
57
58 static void print_cpu_midr(struct sbuf *sb, u_int cpu);
59 static void print_cpu_features(u_int cpu, struct cpu_desc *desc,
60 struct cpu_desc *prev_desc);
61 static void print_cpu_caches(struct sbuf *sb, struct cpu_desc *desc);
62 #ifdef COMPAT_FREEBSD32
63 static u_long parse_cpu_features_hwcap32(void);
64 #endif
65
66 const char machine[] = "arm64";
67
68 #ifdef SCTL_MASK32
69 extern int adaptive_machine_arch;
70 #endif
71
72 static SYSCTL_NODE(_machdep, OID_AUTO, cache, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
73 "Cache management tuning");
74
75 static int allow_dic = 1;
76 SYSCTL_INT(_machdep_cache, OID_AUTO, allow_dic, CTLFLAG_RDTUN, &allow_dic, 0,
77 "Allow optimizations based on the DIC cache bit");
78
79 static int allow_idc = 1;
80 SYSCTL_INT(_machdep_cache, OID_AUTO, allow_idc, CTLFLAG_RDTUN, &allow_idc, 0,
81 "Allow optimizations based on the IDC cache bit");
82
83 static bool emulate_ctr = false;
84
85 static void check_cpu_regs(u_int cpu, struct cpu_desc *desc,
86 struct cpu_desc *prev_desc);
87 static uint64_t update_special_reg_field(uint64_t user_reg, u_int type,
88 uint64_t value, u_int width, u_int shift, bool sign);
89
90 /*
91 * The default implementation of I-cache sync assumes we have an
92 * aliasing cache until we know otherwise.
93 */
94 void (*arm64_icache_sync_range)(void *, vm_size_t) =
95 &arm64_aliasing_icache_sync_range;
96
97 static int
sysctl_hw_machine(SYSCTL_HANDLER_ARGS)98 sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
99 {
100 #ifdef SCTL_MASK32
101 static const char machine32[] = "arm";
102 #endif
103 int error;
104
105 #ifdef SCTL_MASK32
106 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
107 error = SYSCTL_OUT(req, machine32, sizeof(machine32));
108 else
109 #endif
110 error = SYSCTL_OUT(req, machine, sizeof(machine));
111 return (error);
112 }
113
114 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD |
115 CTLFLAG_CAPRD | CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A",
116 "Machine class");
117
118 static char cpu_model[64];
119 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_CAPRD,
120 cpu_model, sizeof(cpu_model), "Machine model");
121
122 #define MAX_CACHES 8 /* Maximum number of caches supported
123 architecturally. */
124 /*
125 * Per-CPU affinity as provided in MPIDR_EL1
126 * Indexed by CPU number in logical order selected by the system.
127 * Relevant fields can be extracted using CPU_AFFn macros,
128 * Aff3.Aff2.Aff1.Aff0 construct a unique CPU address in the system.
129 *
130 * Fields used by us:
131 * Aff1 - Cluster number
132 * Aff0 - CPU number in Aff1 cluster
133 */
134 uint64_t __cpu_affinity[MAXCPU];
135 static u_int cpu_aff_levels;
136
137 struct cpu_desc {
138 uint64_t mpidr;
139 uint64_t id_aa64afr0;
140 uint64_t id_aa64afr1;
141 uint64_t id_aa64dfr0;
142 uint64_t id_aa64dfr1;
143 uint64_t id_aa64isar0;
144 uint64_t id_aa64isar1;
145 uint64_t id_aa64isar2;
146 uint64_t id_aa64mmfr0;
147 uint64_t id_aa64mmfr1;
148 uint64_t id_aa64mmfr2;
149 uint64_t id_aa64mmfr3;
150 uint64_t id_aa64mmfr4;
151 uint64_t id_aa64pfr0;
152 uint64_t id_aa64pfr1;
153 uint64_t id_aa64pfr2;
154 uint64_t id_aa64zfr0;
155 uint64_t ctr;
156 #ifdef COMPAT_FREEBSD32
157 uint64_t id_isar5;
158 uint64_t mvfr0;
159 uint64_t mvfr1;
160 #endif
161 uint64_t clidr;
162 uint32_t ccsidr[MAX_CACHES][2]; /* 2 possible types. */
163 bool have_sve;
164 };
165
166 static struct cpu_desc cpu_desc0;
167 static struct cpu_desc *cpu_desc;
168 static struct cpu_desc kern_cpu_desc;
169 static struct cpu_desc user_cpu_desc;
170 static struct cpu_desc l_user_cpu_desc;
171
172 static struct cpu_desc *
get_cpu_desc(u_int cpu)173 get_cpu_desc(u_int cpu)
174 {
175 /* The cpu_desc for CPU 0 is used before the allocator is ready. */
176 if (cpu == 0)
177 return (&cpu_desc0);
178
179 MPASS(cpu_desc != NULL);
180 return (&cpu_desc[cpu - 1]);
181 }
182
183 struct cpu_parts {
184 u_int part_id;
185 const char *part_name;
186 };
187 #define CPU_PART_NONE { 0, NULL }
188
189 struct cpu_implementers {
190 u_int impl_id;
191 const char *impl_name;
192 /*
193 * Part number is implementation defined
194 * so each vendor will have its own set of values and names.
195 */
196 const struct cpu_parts *cpu_parts;
197 };
198 #define CPU_IMPLEMENTER_NONE { 0, NULL, NULL }
199
200 /*
201 * Per-implementer table of (PartNum, CPU Name) pairs.
202 */
203 /* ARM Ltd. */
204 static const struct cpu_parts cpu_parts_arm[] = {
205 { CPU_PART_AEM_V8, "AEMv8" },
206 { CPU_PART_FOUNDATION, "Foundation-Model" },
207 { CPU_PART_CORTEX_A34, "Cortex-A34" },
208 { CPU_PART_CORTEX_A35, "Cortex-A35" },
209 { CPU_PART_CORTEX_A53, "Cortex-A53" },
210 { CPU_PART_CORTEX_A55, "Cortex-A55" },
211 { CPU_PART_CORTEX_A57, "Cortex-A57" },
212 { CPU_PART_CORTEX_A65, "Cortex-A65" },
213 { CPU_PART_CORTEX_A65AE, "Cortex-A65AE" },
214 { CPU_PART_CORTEX_A72, "Cortex-A72" },
215 { CPU_PART_CORTEX_A73, "Cortex-A73" },
216 { CPU_PART_CORTEX_A75, "Cortex-A75" },
217 { CPU_PART_CORTEX_A76, "Cortex-A76" },
218 { CPU_PART_CORTEX_A76AE, "Cortex-A76AE" },
219 { CPU_PART_CORTEX_A77, "Cortex-A77" },
220 { CPU_PART_CORTEX_A78, "Cortex-A78" },
221 { CPU_PART_CORTEX_A78AE, "Cortex-A78AE" },
222 { CPU_PART_CORTEX_A78C, "Cortex-A78C" },
223 { CPU_PART_CORTEX_A510, "Cortex-A510" },
224 { CPU_PART_CORTEX_A520, "Cortex-A520" },
225 { CPU_PART_CORTEX_A710, "Cortex-A710" },
226 { CPU_PART_CORTEX_A715, "Cortex-A715" },
227 { CPU_PART_CORTEX_A720, "Cortex-A720" },
228 { CPU_PART_CORTEX_A725, "Cortex-A725" },
229 { CPU_PART_CORTEX_X925, "Cortex-A925" },
230 { CPU_PART_CORTEX_X1, "Cortex-X1" },
231 { CPU_PART_CORTEX_X1C, "Cortex-X1C" },
232 { CPU_PART_CORTEX_X2, "Cortex-X2" },
233 { CPU_PART_CORTEX_X3, "Cortex-X3" },
234 { CPU_PART_CORTEX_X4, "Cortex-X4" },
235 { CPU_PART_C1_NANO, "C1-Nano" },
236 { CPU_PART_C1_PRO, "C1-Pro" },
237 { CPU_PART_C1_PREMIUM, "C1-Premium" },
238 { CPU_PART_C1_ULTRA, "C1-Ultra" },
239 { CPU_PART_NEOVERSE_E1, "Neoverse-E1" },
240 { CPU_PART_NEOVERSE_N1, "Neoverse-N1" },
241 { CPU_PART_NEOVERSE_N2, "Neoverse-N2" },
242 { CPU_PART_NEOVERSE_N3, "Neoverse-N3" },
243 { CPU_PART_NEOVERSE_V1, "Neoverse-V1" },
244 { CPU_PART_NEOVERSE_V2, "Neoverse-V2" },
245 { CPU_PART_NEOVERSE_V3, "Neoverse-V3" },
246 { CPU_PART_NEOVERSE_V3AE, "Neoverse-V3AE" },
247 CPU_PART_NONE,
248 };
249
250 /* Cavium */
251 static const struct cpu_parts cpu_parts_cavium[] = {
252 { CPU_PART_THUNDERX, "ThunderX" },
253 { CPU_PART_THUNDERX2, "ThunderX2" },
254 CPU_PART_NONE,
255 };
256
257 /* APM (now Ampere) */
258 static const struct cpu_parts cpu_parts_apm[] = {
259 { CPU_PART_EMAG8180, "eMAG 8180" },
260 CPU_PART_NONE,
261 };
262
263 /* Ampere */
264 static const struct cpu_parts cpu_parts_ampere[] = {
265 { CPU_PART_AMPERE1, "AmpereOne AC03" },
266 { CPU_PART_AMPERE1A, "AmpereOne AC04" },
267 CPU_PART_NONE,
268 };
269
270 /* Microsoft */
271 static const struct cpu_parts cpu_parts_microsoft[] = {
272 { CPU_PART_AZURE_COBALT_100, "Azure Cobalt 100" },
273 CPU_PART_NONE,
274 };
275
276 /* Qualcomm */
277 static const struct cpu_parts cpu_parts_qcom[] = {
278 { CPU_PART_KRYO400_GOLD, "Kryo 400 Gold" },
279 { CPU_PART_KRYO400_SILVER, "Kryo 400 Silver" },
280 CPU_PART_NONE,
281 };
282
283 /* Apple */
284 static const struct cpu_parts cpu_parts_apple[] = {
285 { CPU_PART_M1_ICESTORM, "M1 Icestorm" },
286 { CPU_PART_M1_FIRESTORM, "M1 Firestorm" },
287 { CPU_PART_M1_ICESTORM_PRO, "M1 Pro Icestorm" },
288 { CPU_PART_M1_FIRESTORM_PRO, "M1 Pro Firestorm" },
289 { CPU_PART_M1_ICESTORM_MAX, "M1 Max Icestorm" },
290 { CPU_PART_M1_FIRESTORM_MAX, "M1 Max Firestorm" },
291 { CPU_PART_M2_BLIZZARD, "M2 Blizzard" },
292 { CPU_PART_M2_AVALANCHE, "M2 Avalanche" },
293 { CPU_PART_M2_BLIZZARD_PRO, "M2 Pro Blizzard" },
294 { CPU_PART_M2_AVALANCHE_PRO, "M2 Pro Avalanche" },
295 { CPU_PART_M2_BLIZZARD_MAX, "M2 Max Blizzard" },
296 { CPU_PART_M2_AVALANCHE_MAX, "M2 Max Avalanche" },
297 CPU_PART_NONE,
298 };
299
300 /* Unknown */
301 static const struct cpu_parts cpu_parts_none[] = {
302 CPU_PART_NONE,
303 };
304
305 /*
306 * Implementers table.
307 */
308 const struct cpu_implementers cpu_implementers[] = {
309 { CPU_IMPL_AMPERE, "Ampere", cpu_parts_ampere },
310 { CPU_IMPL_APPLE, "Apple", cpu_parts_apple },
311 { CPU_IMPL_APM, "APM", cpu_parts_apm },
312 { CPU_IMPL_ARM, "ARM", cpu_parts_arm },
313 { CPU_IMPL_BROADCOM, "Broadcom", cpu_parts_none },
314 { CPU_IMPL_CAVIUM, "Cavium", cpu_parts_cavium },
315 { CPU_IMPL_DEC, "DEC", cpu_parts_none },
316 { CPU_IMPL_FREESCALE, "Freescale", cpu_parts_none },
317 { CPU_IMPL_FUJITSU, "Fujitsu", cpu_parts_none },
318 { CPU_IMPL_HISILICON, "HiSilicon", cpu_parts_none },
319 { CPU_IMPL_INFINEON, "IFX", cpu_parts_none },
320 { CPU_IMPL_INTEL, "Intel", cpu_parts_none },
321 { CPU_IMPL_MARVELL, "Marvell", cpu_parts_none },
322 { CPU_IMPL_MICROSOFT, "Microsoft", cpu_parts_microsoft },
323 { CPU_IMPL_NVIDIA, "NVIDIA", cpu_parts_none },
324 { CPU_IMPL_QUALCOMM, "Qualcomm", cpu_parts_qcom },
325 CPU_IMPLEMENTER_NONE,
326 };
327
328 #define MRS_TYPE_MASK 0xf
329 #define MRS_INVALID 0
330 #define MRS_EXACT 1
331 #define MRS_EXACT_IF_DIFFERENT 2
332 #define MRS_LOWER 3
333 #define MRS_HIGHER_OR_ZERO 4
334 #define MRS_HIGHER 5
335 #define MRS_SAFE_SHIFT 4
336 #define MRS_SAFE_MASK (0xfu << MRS_SAFE_SHIFT)
337 #define MRS_SAFE(x) (((x) << MRS_SAFE_SHIFT) & MRS_SAFE_MASK)
338 #define MRS_SAFE_VAL(x) (((x) & MRS_SAFE_MASK) >> MRS_SAFE_SHIFT)
339 #define MRS_FREEBSD (1u << 8)
340 #define MRS_LINUX (1u << 9)
341 #define MRS_USERSPACE (MRS_FREEBSD | MRS_LINUX)
342
343 struct mrs_field_value {
344 uint64_t value;
345 const char *desc;
346 };
347
348 #define MRS_FIELD_VALUE(_value, _desc) \
349 { \
350 .value = (_value), \
351 .desc = (_desc), \
352 }
353
354 #define MRS_FIELD_VALUE_NONE_IMPL(_reg, _field, _none, _impl) \
355 MRS_FIELD_VALUE(_reg ## _ ## _field ## _ ## _none, ""), \
356 MRS_FIELD_VALUE(_reg ## _ ## _field ## _ ## _impl, #_field)
357
358 #define MRS_FIELD_VALUE_COUNT(_reg, _field, _desc) \
359 MRS_FIELD_VALUE(0ul << _reg ## _ ## _field ## _SHIFT, "1 " _desc), \
360 MRS_FIELD_VALUE(1ul << _reg ## _ ## _field ## _SHIFT, "2 " _desc "s"), \
361 MRS_FIELD_VALUE(2ul << _reg ## _ ## _field ## _SHIFT, "3 " _desc "s"), \
362 MRS_FIELD_VALUE(3ul << _reg ## _ ## _field ## _SHIFT, "4 " _desc "s"), \
363 MRS_FIELD_VALUE(4ul << _reg ## _ ## _field ## _SHIFT, "5 " _desc "s"), \
364 MRS_FIELD_VALUE(5ul << _reg ## _ ## _field ## _SHIFT, "6 " _desc "s"), \
365 MRS_FIELD_VALUE(6ul << _reg ## _ ## _field ## _SHIFT, "7 " _desc "s"), \
366 MRS_FIELD_VALUE(7ul << _reg ## _ ## _field ## _SHIFT, "8 " _desc "s"), \
367 MRS_FIELD_VALUE(8ul << _reg ## _ ## _field ## _SHIFT, "9 " _desc "s"), \
368 MRS_FIELD_VALUE(9ul << _reg ## _ ## _field ## _SHIFT, "10 "_desc "s"), \
369 MRS_FIELD_VALUE(10ul<< _reg ## _ ## _field ## _SHIFT, "11 "_desc "s"), \
370 MRS_FIELD_VALUE(11ul<< _reg ## _ ## _field ## _SHIFT, "12 "_desc "s"), \
371 MRS_FIELD_VALUE(12ul<< _reg ## _ ## _field ## _SHIFT, "13 "_desc "s"), \
372 MRS_FIELD_VALUE(13ul<< _reg ## _ ## _field ## _SHIFT, "14 "_desc "s"), \
373 MRS_FIELD_VALUE(14ul<< _reg ## _ ## _field ## _SHIFT, "15 "_desc "s"), \
374 MRS_FIELD_VALUE(15ul<< _reg ## _ ## _field ## _SHIFT, "16 "_desc "s")
375
376 /*
377 * Used for printing I/D cache line sizes & CWG/ERG, as 0 is a special case
378 * in some cases the decoded string needs to be passed in.
379 */
380 #define MRS_FIELD_VALUE_CACHE(_reg, _field, _0desc, _desc) \
381 MRS_FIELD_VALUE(0ul << _reg ## _ ## _field ## _SHIFT, _0desc), \
382 MRS_FIELD_VALUE(1ul << _reg ## _ ## _field ## _SHIFT, "8 " _desc), \
383 MRS_FIELD_VALUE(2ul << _reg ## _ ## _field ## _SHIFT, "16 " _desc), \
384 MRS_FIELD_VALUE(3ul << _reg ## _ ## _field ## _SHIFT, "32 " _desc), \
385 MRS_FIELD_VALUE(4ul << _reg ## _ ## _field ## _SHIFT, "64 " _desc), \
386 MRS_FIELD_VALUE(5ul << _reg ## _ ## _field ## _SHIFT, "128 " _desc), \
387 MRS_FIELD_VALUE(6ul << _reg ## _ ## _field ## _SHIFT, "256 " _desc), \
388 MRS_FIELD_VALUE(7ul << _reg ## _ ## _field ## _SHIFT, "512 " _desc), \
389 MRS_FIELD_VALUE(8ul << _reg ## _ ## _field ## _SHIFT, "1k " _desc), \
390 MRS_FIELD_VALUE(9ul << _reg ## _ ## _field ## _SHIFT, "2k " _desc), \
391 MRS_FIELD_VALUE(10ul<< _reg ## _ ## _field ## _SHIFT, "4k " _desc), \
392 MRS_FIELD_VALUE(11ul<< _reg ## _ ## _field ## _SHIFT, "8k " _desc), \
393 MRS_FIELD_VALUE(12ul<< _reg ## _ ## _field ## _SHIFT, "16k " _desc), \
394 MRS_FIELD_VALUE(13ul<< _reg ## _ ## _field ## _SHIFT, "32k " _desc), \
395 MRS_FIELD_VALUE(14ul<< _reg ## _ ## _field ## _SHIFT, "64k " _desc), \
396 MRS_FIELD_VALUE(15ul<< _reg ## _ ## _field ## _SHIFT, "128k "_desc)
397
398 #define MRS_FIELD_VALUE_END { .desc = NULL }
399
400 struct mrs_field_hwcap {
401 uint64_t min;
402 u_long hwcap_val;
403 u_int hwcap_id;
404 };
405
406 #define MRS_HWCAP(_hwcap_id, _val, _min) \
407 { \
408 .hwcap_id = (_hwcap_id), \
409 .hwcap_val = (_val), \
410 .min = (_min), \
411 }
412
413 #define MRS_HWCAP_END { .hwcap_id = 0 }
414
415 struct mrs_field {
416 const char *name;
417 const struct mrs_field_value *values;
418 const struct mrs_field_hwcap *hwcaps;
419 uint64_t mask;
420 bool sign;
421 u_int type;
422 u_int width;
423 u_int shift;
424 };
425
426 #define MRS_FIELD_RES1(_width, _shift) \
427 { \
428 .sign = false, \
429 .type = MRS_EXACT | MRS_SAFE((1u << (_width)) - 1) | \
430 MRS_USERSPACE, \
431 .width = (_width), \
432 .shift = (_shift), \
433 }
434
435 #define MRS_FIELD_HWCAP(_register, _name, _sign, _type, _visibility, \
436 _values, _hwcap) \
437 { \
438 .name = #_name, \
439 .sign = (_sign), \
440 .type = ((_type) | (_visibility)), \
441 .width = _register ## _ ## _name ## _WIDTH, \
442 .shift = _register ## _ ## _name ## _SHIFT, \
443 .mask = _register ## _ ## _name ## _MASK, \
444 .values = (_values), \
445 .hwcaps = (_hwcap), \
446 }
447
448 #define MRS_FIELD(_register, _name, _sign, _type, _visibility, _values) \
449 MRS_FIELD_HWCAP(_register, _name, _sign, _type, _visibility, \
450 _values, NULL)
451
452 #define MRS_FIELD_END { .type = MRS_INVALID, }
453
454 /* CTR_EL0 */
455 static const struct mrs_field_value ctr_dic[] = {
456 MRS_FIELD_VALUE_NONE_IMPL(CTR, DIC, NONE, IMPL),
457 MRS_FIELD_VALUE_END,
458 };
459
460 static const struct mrs_field_value ctr_idc[] = {
461 MRS_FIELD_VALUE_NONE_IMPL(CTR, IDC, NONE, IMPL),
462 MRS_FIELD_VALUE_END,
463 };
464
465 static const struct mrs_field_value ctr_cwg[] = {
466 MRS_FIELD_VALUE_CACHE(CTR, CWG, "Unknown CWG",
467 "byte CWG"),
468 MRS_FIELD_VALUE_END,
469 };
470
471 static const struct mrs_field_value ctr_erg[] = {
472 MRS_FIELD_VALUE_CACHE(CTR, ERG, "Unknown ERG",
473 "byte ERG"),
474 MRS_FIELD_VALUE_END,
475 };
476
477 static const struct mrs_field_value ctr_dline[] = {
478 MRS_FIELD_VALUE_CACHE(CTR, DLINE, "4 byte D-cacheline",
479 "byte D-cacheline"),
480 MRS_FIELD_VALUE_END,
481 };
482
483 static const struct mrs_field_value ctr_l1ip[] = {
484 MRS_FIELD_VALUE(CTR_L1IP_VIPT, "VIPT I-cache"),
485 MRS_FIELD_VALUE(CTR_L1IP_PIPT, "PIPT I-cache"),
486 MRS_FIELD_VALUE_END,
487 };
488
489 static const struct mrs_field_value ctr_iline[] = {
490 MRS_FIELD_VALUE_CACHE(CTR, ILINE, "4 byte I-cacheline",
491 "byte I-cacheline"),
492 MRS_FIELD_VALUE_END,
493 };
494
495 static const struct mrs_field ctr_fields[] = {
496 /* Bit 31 is RES1 */
497 MRS_FIELD_RES1(1, 31),
498 MRS_FIELD(CTR, DIC, false, MRS_LOWER, MRS_USERSPACE, ctr_dic),
499 MRS_FIELD(CTR, IDC, false, MRS_LOWER, MRS_USERSPACE, ctr_idc),
500 MRS_FIELD(CTR, CWG, false, MRS_HIGHER_OR_ZERO, MRS_USERSPACE, ctr_cwg),
501 MRS_FIELD(CTR, ERG, false, MRS_HIGHER_OR_ZERO, MRS_USERSPACE, ctr_erg),
502 MRS_FIELD(CTR, DLINE, false, MRS_LOWER, MRS_USERSPACE, ctr_dline),
503 /* If the ICache types are different report the safe option */
504 MRS_FIELD(CTR, L1IP, false, MRS_EXACT_IF_DIFFERENT |
505 MRS_SAFE(CTR_L1IP_VIPT >> CTR_L1IP_SHIFT), MRS_USERSPACE,
506 ctr_l1ip),
507 MRS_FIELD(CTR, ILINE, false, MRS_LOWER, MRS_USERSPACE, ctr_iline),
508 MRS_FIELD_END,
509 };
510
511 /* ID_AA64AFR0_EL1 */
512 static const struct mrs_field id_aa64afr0_fields[] = {
513 MRS_FIELD_END,
514 };
515
516
517 /* ID_AA64AFR1_EL1 */
518 static const struct mrs_field id_aa64afr1_fields[] = {
519 MRS_FIELD_END,
520 };
521
522
523 /* ID_AA64DFR0_EL1 */
524 static const struct mrs_field_value id_aa64dfr0_hpmn0[] = {
525 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64DFR0, HPMN0, CONSTR, DEFINED),
526 MRS_FIELD_VALUE_END,
527 };
528
529 static const struct mrs_field_value id_aa64dfr0_brbe[] = {
530 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64DFR0, BRBE, NONE, IMPL),
531 MRS_FIELD_VALUE(ID_AA64DFR0_BRBE_EL3, "BRBE EL3"),
532 MRS_FIELD_VALUE_END,
533 };
534
535 static const struct mrs_field_value id_aa64dfr0_mtpmu[] = {
536 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64DFR0, MTPMU, NONE, IMPL),
537 MRS_FIELD_VALUE(ID_AA64DFR0_MTPMU_NONE_MT_RES0, "MTPMU res0"),
538 MRS_FIELD_VALUE_END,
539 };
540
541 static const struct mrs_field_value id_aa64dfr0_tracebuffer[] = {
542 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64DFR0, TraceBuffer, NONE, IMPL),
543 MRS_FIELD_VALUE_END,
544 };
545
546 static const struct mrs_field_value id_aa64dfr0_tracefilt[] = {
547 MRS_FIELD_VALUE(ID_AA64DFR0_TraceFilt_NONE, ""),
548 MRS_FIELD_VALUE(ID_AA64DFR0_TraceFilt_8_4, "Trace v8.4"),
549 MRS_FIELD_VALUE_END,
550 };
551
552 static const struct mrs_field_value id_aa64dfr0_doublelock[] = {
553 MRS_FIELD_VALUE(ID_AA64DFR0_DoubleLock_IMPL, "DoubleLock"),
554 MRS_FIELD_VALUE(ID_AA64DFR0_DoubleLock_NONE, ""),
555 MRS_FIELD_VALUE_END,
556 };
557
558 static const struct mrs_field_value id_aa64dfr0_pmsver[] = {
559 MRS_FIELD_VALUE(ID_AA64DFR0_PMSVer_NONE, ""),
560 MRS_FIELD_VALUE(ID_AA64DFR0_PMSVer_SPE, "SPE"),
561 MRS_FIELD_VALUE(ID_AA64DFR0_PMSVer_SPE_1_1, "SPEv1p1"),
562 MRS_FIELD_VALUE(ID_AA64DFR0_PMSVer_SPE_1_2, "SPEv1p2"),
563 MRS_FIELD_VALUE(ID_AA64DFR0_PMSVer_SPE_1_3, "SPEv1p3"),
564 MRS_FIELD_VALUE(ID_AA64DFR0_PMSVer_SPE_1_4, "SPEv1p4"),
565 MRS_FIELD_VALUE_END,
566 };
567
568 static const struct mrs_field_value id_aa64dfr0_ctx_cmps[] = {
569 MRS_FIELD_VALUE_COUNT(ID_AA64DFR0, CTX_CMPs, "CTX BKPT"),
570 MRS_FIELD_VALUE_END,
571 };
572
573 static const struct mrs_field_value id_aa64dfr0_wrps[] = {
574 MRS_FIELD_VALUE_COUNT(ID_AA64DFR0, WRPs, "Watchpoint"),
575 MRS_FIELD_VALUE_END,
576 };
577
578 static const struct mrs_field_value id_aa64dfr0_pmss[] = {
579 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64DFR0, PMSS, NONE, IMPL),
580 MRS_FIELD_VALUE_END,
581 };
582
583 static const struct mrs_field_value id_aa64dfr0_brps[] = {
584 MRS_FIELD_VALUE_COUNT(ID_AA64DFR0, BRPs, "Breakpoint"),
585 MRS_FIELD_VALUE_END,
586 };
587
588 static const struct mrs_field_value id_aa64dfr0_pmuver[] = {
589 MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_NONE, ""),
590 MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3, "PMUv3"),
591 MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3_1, "PMUv3p1"),
592 MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3_4, "PMUv3p4"),
593 MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3_5, "PMUv3p5"),
594 MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3_7, "PMUv3p7"),
595 MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3_8, "PMUv3p8"),
596 MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3_9, "PMUv3p9"),
597 MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_IMPL, "IMPL PMU"),
598 MRS_FIELD_VALUE_END,
599 };
600
601 static const struct mrs_field_value id_aa64dfr0_tracever[] = {
602 MRS_FIELD_VALUE(ID_AA64DFR0_TraceVer_NONE, ""),
603 MRS_FIELD_VALUE(ID_AA64DFR0_TraceVer_IMPL, "Trace"),
604 MRS_FIELD_VALUE_END,
605 };
606
607 static const struct mrs_field_value id_aa64dfr0_debugver[] = {
608 MRS_FIELD_VALUE(ID_AA64DFR0_DebugVer_8, "Debugv8"),
609 MRS_FIELD_VALUE(ID_AA64DFR0_DebugVer_8_VHE, "Debugv8_VHE"),
610 MRS_FIELD_VALUE(ID_AA64DFR0_DebugVer_8_2, "Debugv8p2"),
611 MRS_FIELD_VALUE(ID_AA64DFR0_DebugVer_8_4, "Debugv8p4"),
612 MRS_FIELD_VALUE(ID_AA64DFR0_DebugVer_8_8, "Debugv8p8"),
613 MRS_FIELD_VALUE(ID_AA64DFR0_DebugVer_8_9, "Debugv8p9"),
614 MRS_FIELD_VALUE_END,
615 };
616
617 static const struct mrs_field id_aa64dfr0_fields[] = {
618 MRS_FIELD(ID_AA64DFR0, HPMN0, false, MRS_LOWER, 0, id_aa64dfr0_hpmn0),
619 MRS_FIELD(ID_AA64DFR0, BRBE, false, MRS_LOWER, 0, id_aa64dfr0_brbe),
620 MRS_FIELD(ID_AA64DFR0, MTPMU, true, MRS_LOWER, 0, id_aa64dfr0_mtpmu),
621 MRS_FIELD(ID_AA64DFR0, TraceBuffer, false, MRS_LOWER, 0,
622 id_aa64dfr0_tracebuffer),
623 MRS_FIELD(ID_AA64DFR0, TraceFilt, false, MRS_LOWER, 0,
624 id_aa64dfr0_tracefilt),
625 MRS_FIELD(ID_AA64DFR0, DoubleLock, true, MRS_LOWER, 0,
626 id_aa64dfr0_doublelock),
627 MRS_FIELD(ID_AA64DFR0, PMSVer, false, MRS_LOWER, 0, id_aa64dfr0_pmsver),
628 MRS_FIELD(ID_AA64DFR0, CTX_CMPs, false, MRS_LOWER, 0,
629 id_aa64dfr0_ctx_cmps),
630 MRS_FIELD(ID_AA64DFR0, WRPs, false, MRS_LOWER, MRS_USERSPACE,
631 id_aa64dfr0_wrps),
632 MRS_FIELD(ID_AA64DFR0, PMSS, false, MRS_LOWER, 0, id_aa64dfr0_pmss),
633 MRS_FIELD(ID_AA64DFR0, BRPs, false, MRS_LOWER, MRS_USERSPACE,
634 id_aa64dfr0_brps),
635 MRS_FIELD(ID_AA64DFR0, PMUVer, true, MRS_LOWER, 0, id_aa64dfr0_pmuver),
636 MRS_FIELD(ID_AA64DFR0, TraceVer, false, MRS_LOWER, 0,
637 id_aa64dfr0_tracever),
638 MRS_FIELD(ID_AA64DFR0, DebugVer, false, MRS_LOWER | MRS_SAFE(0x6), 0,
639 id_aa64dfr0_debugver),
640 MRS_FIELD_END,
641 };
642
643
644 /* ID_AA64DFR1_EL1 */
645 static const struct mrs_field_value id_aa64dfr1_dpfzs[] = {
646 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64DFR1, DPFZS, NONE, IMPL),
647 MRS_FIELD_VALUE_END,
648 };
649
650 static const struct mrs_field_value id_aa64dfr1_pmicntr[] = {
651 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64DFR1, PMICNTR, NONE, IMPL),
652 MRS_FIELD_VALUE_END,
653 };
654
655 static const struct mrs_field_value id_aa64dfr1_spmu[] = {
656 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64DFR1, SPMU, NONE, IMPL),
657 MRS_FIELD_VALUE_END,
658 };
659
660 static const struct mrs_field id_aa64dfr1_fields[] = {
661 MRS_FIELD(ID_AA64DFR1, DPFZS, false, MRS_LOWER, 0, id_aa64dfr1_dpfzs),
662 MRS_FIELD(ID_AA64DFR1, PMICNTR, false, MRS_LOWER, 0, id_aa64dfr1_pmicntr),
663 MRS_FIELD(ID_AA64DFR1, SPMU, false, MRS_LOWER, 0, id_aa64dfr1_spmu),
664 MRS_FIELD_END,
665 };
666
667
668 /* ID_AA64ISAR0_EL1 */
669 static const struct mrs_field_value id_aa64isar0_rndr[] = {
670 MRS_FIELD_VALUE(ID_AA64ISAR0_RNDR_NONE, ""),
671 MRS_FIELD_VALUE(ID_AA64ISAR0_RNDR_IMPL, "RNG"),
672 MRS_FIELD_VALUE_END,
673 };
674
675 static const struct mrs_field_hwcap id_aa64isar0_rndr_caps[] = {
676 MRS_HWCAP(2, HWCAP2_RNG, ID_AA64ISAR0_RNDR_IMPL),
677 MRS_HWCAP_END
678 };
679
680 static const struct mrs_field_value id_aa64isar0_tlb[] = {
681 MRS_FIELD_VALUE(ID_AA64ISAR0_TLB_NONE, ""),
682 MRS_FIELD_VALUE(ID_AA64ISAR0_TLB_TLBIOS, "TLBI-OS"),
683 MRS_FIELD_VALUE(ID_AA64ISAR0_TLB_TLBIOSR, "TLBI-OSR"),
684 MRS_FIELD_VALUE_END,
685 };
686
687 static const struct mrs_field_value id_aa64isar0_ts[] = {
688 MRS_FIELD_VALUE(ID_AA64ISAR0_TS_NONE, ""),
689 MRS_FIELD_VALUE(ID_AA64ISAR0_TS_CondM_8_4, "CondM-8.4"),
690 MRS_FIELD_VALUE(ID_AA64ISAR0_TS_CondM_8_5, "CondM-8.5"),
691 MRS_FIELD_VALUE_END,
692 };
693
694 static const struct mrs_field_hwcap id_aa64isar0_ts_caps[] = {
695 MRS_HWCAP(1, HWCAP_FLAGM, ID_AA64ISAR0_TS_CondM_8_4),
696 MRS_HWCAP(2, HWCAP2_FLAGM2, ID_AA64ISAR0_TS_CondM_8_5),
697 MRS_HWCAP_END
698 };
699
700 static const struct mrs_field_value id_aa64isar0_fhm[] = {
701 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, FHM, NONE, IMPL),
702 MRS_FIELD_VALUE_END,
703 };
704
705 static const struct mrs_field_hwcap id_aa64isar0_fhm_caps[] = {
706 MRS_HWCAP(1, HWCAP_ASIMDFHM, ID_AA64ISAR0_FHM_IMPL),
707 MRS_HWCAP_END
708 };
709
710 static const struct mrs_field_value id_aa64isar0_dp[] = {
711 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, DP, NONE, IMPL),
712 MRS_FIELD_VALUE_END,
713 };
714
715 static const struct mrs_field_hwcap id_aa64isar0_dp_caps[] = {
716 MRS_HWCAP(1, HWCAP_ASIMDDP, ID_AA64ISAR0_DP_IMPL),
717 MRS_HWCAP_END
718 };
719
720 static const struct mrs_field_value id_aa64isar0_sm4[] = {
721 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, SM4, NONE, IMPL),
722 MRS_FIELD_VALUE_END,
723 };
724
725 static const struct mrs_field_hwcap id_aa64isar0_sm4_caps[] = {
726 MRS_HWCAP(1, HWCAP_SM4, ID_AA64ISAR0_SM4_IMPL),
727 MRS_HWCAP_END
728 };
729
730 static const struct mrs_field_value id_aa64isar0_sm3[] = {
731 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, SM3, NONE, IMPL),
732 MRS_FIELD_VALUE_END,
733 };
734
735 static const struct mrs_field_hwcap id_aa64isar0_sm3_caps[] = {
736 MRS_HWCAP(1, HWCAP_SM3, ID_AA64ISAR0_SM3_IMPL),
737 MRS_HWCAP_END
738 };
739
740 static const struct mrs_field_value id_aa64isar0_sha3[] = {
741 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, SHA3, NONE, IMPL),
742 MRS_FIELD_VALUE_END,
743 };
744
745 static const struct mrs_field_hwcap id_aa64isar0_sha3_caps[] = {
746 MRS_HWCAP(1, HWCAP_SHA3, ID_AA64ISAR0_SHA3_IMPL),
747 MRS_HWCAP_END
748 };
749
750 static const struct mrs_field_value id_aa64isar0_rdm[] = {
751 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, RDM, NONE, IMPL),
752 MRS_FIELD_VALUE_END,
753 };
754
755 static const struct mrs_field_hwcap id_aa64isar0_rdm_caps[] = {
756 MRS_HWCAP(1, HWCAP_ASIMDRDM, ID_AA64ISAR0_RDM_IMPL),
757 MRS_HWCAP_END
758 };
759
760 static const struct mrs_field_value id_aa64isar0_tme[] = {
761 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, TME, NONE, IMPL),
762 MRS_FIELD_VALUE_END,
763 };
764
765 static const struct mrs_field_value id_aa64isar0_atomic[] = {
766 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, Atomic, NONE, IMPL),
767 MRS_FIELD_VALUE_END,
768 };
769
770 static const struct mrs_field_hwcap id_aa64isar0_atomic_caps[] = {
771 MRS_HWCAP(1, HWCAP_ATOMICS, ID_AA64ISAR0_Atomic_IMPL),
772 MRS_HWCAP_END
773 };
774
775 static const struct mrs_field_value id_aa64isar0_crc32[] = {
776 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, CRC32, NONE, BASE),
777 MRS_FIELD_VALUE_END,
778 };
779
780 static const struct mrs_field_hwcap id_aa64isar0_crc32_caps[] = {
781 MRS_HWCAP(1, HWCAP_CRC32, ID_AA64ISAR0_CRC32_BASE),
782 MRS_HWCAP_END
783 };
784
785 static const struct mrs_field_value id_aa64isar0_sha2[] = {
786 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, SHA2, NONE, BASE),
787 MRS_FIELD_VALUE(ID_AA64ISAR0_SHA2_512, "SHA2+SHA512"),
788 MRS_FIELD_VALUE_END,
789 };
790
791 static const struct mrs_field_hwcap id_aa64isar0_sha2_caps[] = {
792 MRS_HWCAP(1, HWCAP_SHA2, ID_AA64ISAR0_SHA2_BASE),
793 MRS_HWCAP(1, HWCAP_SHA512, ID_AA64ISAR0_SHA2_512),
794 MRS_HWCAP_END
795 };
796
797 static const struct mrs_field_value id_aa64isar0_sha1[] = {
798 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, SHA1, NONE, BASE),
799 MRS_FIELD_VALUE_END,
800 };
801
802 static const struct mrs_field_hwcap id_aa64isar0_sha1_caps[] = {
803 MRS_HWCAP(1, HWCAP_SHA1, ID_AA64ISAR0_SHA1_BASE),
804 MRS_HWCAP_END
805 };
806
807 static const struct mrs_field_value id_aa64isar0_aes[] = {
808 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, AES, NONE, BASE),
809 MRS_FIELD_VALUE(ID_AA64ISAR0_AES_PMULL, "AES+PMULL"),
810 MRS_FIELD_VALUE_END,
811 };
812
813 static const struct mrs_field_hwcap id_aa64isar0_aes_caps[] = {
814 MRS_HWCAP(1, HWCAP_AES, ID_AA64ISAR0_AES_BASE),
815 MRS_HWCAP(1, HWCAP_PMULL, ID_AA64ISAR0_AES_PMULL),
816 MRS_HWCAP_END
817 };
818
819 static const struct mrs_field id_aa64isar0_fields[] = {
820 MRS_FIELD_HWCAP(ID_AA64ISAR0, RNDR, false, MRS_LOWER, MRS_USERSPACE,
821 id_aa64isar0_rndr, id_aa64isar0_rndr_caps),
822 MRS_FIELD(ID_AA64ISAR0, TLB, false, MRS_LOWER, 0, id_aa64isar0_tlb),
823 MRS_FIELD_HWCAP(ID_AA64ISAR0, TS, false, MRS_LOWER, MRS_USERSPACE,
824 id_aa64isar0_ts, id_aa64isar0_ts_caps),
825 MRS_FIELD_HWCAP(ID_AA64ISAR0, FHM, false, MRS_LOWER, MRS_USERSPACE,
826 id_aa64isar0_fhm, id_aa64isar0_fhm_caps),
827 MRS_FIELD_HWCAP(ID_AA64ISAR0, DP, false, MRS_LOWER, MRS_USERSPACE,
828 id_aa64isar0_dp, id_aa64isar0_dp_caps),
829 MRS_FIELD_HWCAP(ID_AA64ISAR0, SM4, false, MRS_LOWER, MRS_USERSPACE,
830 id_aa64isar0_sm4, id_aa64isar0_sm4_caps),
831 MRS_FIELD_HWCAP(ID_AA64ISAR0, SM3, false, MRS_LOWER, MRS_USERSPACE,
832 id_aa64isar0_sm3, id_aa64isar0_sm3_caps),
833 MRS_FIELD_HWCAP(ID_AA64ISAR0, SHA3, false, MRS_LOWER, MRS_USERSPACE,
834 id_aa64isar0_sha3, id_aa64isar0_sha3_caps),
835 MRS_FIELD_HWCAP(ID_AA64ISAR0, RDM, false, MRS_LOWER, MRS_USERSPACE,
836 id_aa64isar0_rdm, id_aa64isar0_rdm_caps),
837 MRS_FIELD(ID_AA64ISAR0, TME, false, MRS_LOWER, 0, id_aa64isar0_tme),
838 MRS_FIELD_HWCAP(ID_AA64ISAR0, Atomic, false, MRS_LOWER, MRS_USERSPACE,
839 id_aa64isar0_atomic, id_aa64isar0_atomic_caps),
840 MRS_FIELD_HWCAP(ID_AA64ISAR0, CRC32, false, MRS_LOWER, MRS_USERSPACE,
841 id_aa64isar0_crc32, id_aa64isar0_crc32_caps),
842 MRS_FIELD_HWCAP(ID_AA64ISAR0, SHA2, false, MRS_LOWER, MRS_USERSPACE,
843 id_aa64isar0_sha2, id_aa64isar0_sha2_caps),
844 MRS_FIELD_HWCAP(ID_AA64ISAR0, SHA1, false, MRS_LOWER, MRS_USERSPACE,
845 id_aa64isar0_sha1, id_aa64isar0_sha1_caps),
846 MRS_FIELD_HWCAP(ID_AA64ISAR0, AES, false, MRS_LOWER, MRS_USERSPACE,
847 id_aa64isar0_aes, id_aa64isar0_aes_caps),
848 MRS_FIELD_END,
849 };
850
851
852 /* ID_AA64ISAR1_EL1 */
853 static const struct mrs_field_value id_aa64isar1_ls64[] = {
854 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, LS64, NONE, IMPL),
855 MRS_FIELD_VALUE(ID_AA64ISAR1_LS64_V, "LS64v"),
856 MRS_FIELD_VALUE(ID_AA64ISAR1_LS64_ACCDATA, "LS64+ACCDATA"),
857 MRS_FIELD_VALUE_END,
858 };
859
860 static const struct mrs_field_value id_aa64isar1_xs[] = {
861 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, XS, NONE, IMPL),
862 MRS_FIELD_VALUE_END,
863 };
864
865 static const struct mrs_field_value id_aa64isar1_i8mm[] = {
866 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, I8MM, NONE, IMPL),
867 MRS_FIELD_VALUE_END,
868 };
869
870 static const struct mrs_field_hwcap id_aa64isar1_i8mm_caps[] = {
871 MRS_HWCAP(2, HWCAP2_I8MM, ID_AA64ISAR1_I8MM_IMPL),
872 MRS_HWCAP_END
873 };
874
875 static const struct mrs_field_value id_aa64isar1_dgh[] = {
876 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, DGH, NONE, IMPL),
877 MRS_FIELD_VALUE_END,
878 };
879
880 static const struct mrs_field_hwcap id_aa64isar1_dgh_caps[] = {
881 MRS_HWCAP(2, HWCAP2_DGH, ID_AA64ISAR1_DGH_IMPL),
882 MRS_HWCAP_END
883 };
884
885 static const struct mrs_field_value id_aa64isar1_bf16[] = {
886 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, BF16, NONE, IMPL),
887 MRS_FIELD_VALUE(ID_AA64ISAR1_BF16_EBF, "EBF16"),
888 MRS_FIELD_VALUE_END,
889 };
890
891 static const struct mrs_field_hwcap id_aa64isar1_bf16_caps[] = {
892 MRS_HWCAP(2, HWCAP2_BF16, ID_AA64ISAR1_BF16_IMPL),
893 MRS_HWCAP_END
894 };
895
896 static const struct mrs_field_value id_aa64isar1_specres[] = {
897 MRS_FIELD_VALUE(ID_AA64ISAR1_SPECRES_NONE, ""),
898 MRS_FIELD_VALUE(ID_AA64ISAR1_SPECRES_8_5, "PredInv v8.5"),
899 MRS_FIELD_VALUE(ID_AA64ISAR1_SPECRES_8_9, "PredInv v8.9"),
900 MRS_FIELD_VALUE_END,
901 };
902
903 static const struct mrs_field_value id_aa64isar1_sb[] = {
904 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, SB, NONE, IMPL),
905 MRS_FIELD_VALUE_END,
906 };
907
908 static const struct mrs_field_hwcap id_aa64isar1_sb_caps[] = {
909 MRS_HWCAP(1, HWCAP_SB, ID_AA64ISAR1_SB_IMPL),
910 MRS_HWCAP_END
911 };
912
913 static const struct mrs_field_value id_aa64isar1_frintts[] = {
914 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, FRINTTS, NONE, IMPL),
915 MRS_FIELD_VALUE_END,
916 };
917
918 static const struct mrs_field_hwcap id_aa64isar1_frintts_caps[] = {
919 MRS_HWCAP(2, HWCAP2_FRINT, ID_AA64ISAR1_FRINTTS_IMPL),
920 MRS_HWCAP_END
921 };
922
923 static const struct mrs_field_value id_aa64isar1_gpi[] = {
924 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, GPI, NONE, IMPL),
925 MRS_FIELD_VALUE_END,
926 };
927
928 static const struct mrs_field_hwcap id_aa64isar1_gpi_caps[] = {
929 MRS_HWCAP(1, HWCAP_PACG, ID_AA64ISAR1_GPI_IMPL),
930 MRS_HWCAP_END
931 };
932
933 static const struct mrs_field_value id_aa64isar1_gpa[] = {
934 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, GPA, NONE, IMPL),
935 MRS_FIELD_VALUE_END,
936 };
937
938 static const struct mrs_field_hwcap id_aa64isar1_gpa_caps[] = {
939 MRS_HWCAP(1, HWCAP_PACG, ID_AA64ISAR1_GPA_IMPL),
940 MRS_HWCAP_END
941 };
942
943 static const struct mrs_field_value id_aa64isar1_lrcpc[] = {
944 MRS_FIELD_VALUE(ID_AA64ISAR1_LRCPC_NONE, ""),
945 MRS_FIELD_VALUE(ID_AA64ISAR1_LRCPC_RCPC_8_3, "RCPC-8.3"),
946 MRS_FIELD_VALUE(ID_AA64ISAR1_LRCPC_RCPC_8_4, "RCPC-8.4"),
947 MRS_FIELD_VALUE_END,
948 };
949
950 static const struct mrs_field_hwcap id_aa64isar1_lrcpc_caps[] = {
951 MRS_HWCAP(1, HWCAP_LRCPC, ID_AA64ISAR1_LRCPC_RCPC_8_3),
952 MRS_HWCAP(1, HWCAP_ILRCPC, ID_AA64ISAR1_LRCPC_RCPC_8_4),
953 MRS_HWCAP_END
954 };
955
956 static const struct mrs_field_value id_aa64isar1_fcma[] = {
957 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, FCMA, NONE, IMPL),
958 MRS_FIELD_VALUE_END,
959 };
960
961 static const struct mrs_field_hwcap id_aa64isar1_fcma_caps[] = {
962 MRS_HWCAP(1, HWCAP_FCMA, ID_AA64ISAR1_FCMA_IMPL),
963 MRS_HWCAP_END
964 };
965
966 static const struct mrs_field_value id_aa64isar1_jscvt[] = {
967 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, JSCVT, NONE, IMPL),
968 MRS_FIELD_VALUE_END,
969 };
970
971 static const struct mrs_field_hwcap id_aa64isar1_jscvt_caps[] = {
972 MRS_HWCAP(1, HWCAP_JSCVT, ID_AA64ISAR1_JSCVT_IMPL),
973 MRS_HWCAP_END
974 };
975
976 static const struct mrs_field_value id_aa64isar1_api[] = {
977 MRS_FIELD_VALUE(ID_AA64ISAR1_API_NONE, ""),
978 MRS_FIELD_VALUE(ID_AA64ISAR1_API_PAC, "API PAC"),
979 MRS_FIELD_VALUE(ID_AA64ISAR1_API_EPAC, "API EPAC"),
980 MRS_FIELD_VALUE(ID_AA64ISAR1_API_EPAC2, "Impl PAuth+EPAC2"),
981 MRS_FIELD_VALUE(ID_AA64ISAR1_API_FPAC, "Impl PAuth+FPAC"),
982 MRS_FIELD_VALUE(ID_AA64ISAR1_API_FPAC_COMBINED,
983 "Impl PAuth+FPAC+Combined"),
984 MRS_FIELD_VALUE_END,
985 };
986
987 static const struct mrs_field_hwcap id_aa64isar1_api_caps[] = {
988 MRS_HWCAP(1, HWCAP_PACA, ID_AA64ISAR1_API_PAC),
989 MRS_HWCAP_END
990 };
991
992 static const struct mrs_field_value id_aa64isar1_apa[] = {
993 MRS_FIELD_VALUE(ID_AA64ISAR1_APA_NONE, ""),
994 MRS_FIELD_VALUE(ID_AA64ISAR1_APA_PAC, "APA PAC"),
995 MRS_FIELD_VALUE(ID_AA64ISAR1_APA_EPAC, "APA EPAC"),
996 MRS_FIELD_VALUE(ID_AA64ISAR1_APA_EPAC2, "APA EPAC2"),
997 MRS_FIELD_VALUE(ID_AA64ISAR1_APA_FPAC, "APA FPAC"),
998 MRS_FIELD_VALUE(ID_AA64ISAR1_APA_FPAC_COMBINED,
999 "APA FPAC+Combined"),
1000 MRS_FIELD_VALUE_END,
1001 };
1002
1003 static const struct mrs_field_hwcap id_aa64isar1_apa_caps[] = {
1004 MRS_HWCAP(1, HWCAP_PACA, ID_AA64ISAR1_APA_PAC),
1005 MRS_HWCAP_END
1006 };
1007
1008 static const struct mrs_field_value id_aa64isar1_dpb[] = {
1009 MRS_FIELD_VALUE(ID_AA64ISAR1_DPB_NONE, ""),
1010 MRS_FIELD_VALUE(ID_AA64ISAR1_DPB_DCCVAP, "DCPoP"),
1011 MRS_FIELD_VALUE(ID_AA64ISAR1_DPB_DCCVADP, "DCCVADP"),
1012 MRS_FIELD_VALUE_END,
1013 };
1014
1015 static const struct mrs_field_hwcap id_aa64isar1_dpb_caps[] = {
1016 MRS_HWCAP(1, HWCAP_DCPOP, ID_AA64ISAR1_DPB_DCCVAP),
1017 MRS_HWCAP(2, HWCAP2_DCPODP, ID_AA64ISAR1_DPB_DCCVADP),
1018 MRS_HWCAP_END
1019 };
1020
1021 static const struct mrs_field id_aa64isar1_fields[] = {
1022 MRS_FIELD(ID_AA64ISAR1, LS64, false, MRS_LOWER, 0, id_aa64isar1_ls64),
1023 MRS_FIELD(ID_AA64ISAR1, XS, false, MRS_LOWER, 0, id_aa64isar1_xs),
1024 MRS_FIELD_HWCAP(ID_AA64ISAR1, I8MM, false, MRS_LOWER, MRS_USERSPACE,
1025 id_aa64isar1_i8mm, id_aa64isar1_i8mm_caps),
1026 MRS_FIELD_HWCAP(ID_AA64ISAR1, DGH, false, MRS_LOWER, MRS_USERSPACE,
1027 id_aa64isar1_dgh, id_aa64isar1_dgh_caps),
1028 MRS_FIELD_HWCAP(ID_AA64ISAR1, BF16, false, MRS_LOWER, MRS_USERSPACE,
1029 id_aa64isar1_bf16, id_aa64isar1_bf16_caps),
1030 MRS_FIELD(ID_AA64ISAR1, SPECRES, false, MRS_LOWER, 0,
1031 id_aa64isar1_specres),
1032 MRS_FIELD_HWCAP(ID_AA64ISAR1, SB, false, MRS_LOWER, MRS_USERSPACE,
1033 id_aa64isar1_sb, id_aa64isar1_sb_caps),
1034 MRS_FIELD_HWCAP(ID_AA64ISAR1, FRINTTS, false, MRS_LOWER, MRS_USERSPACE,
1035 id_aa64isar1_frintts, id_aa64isar1_frintts_caps),
1036 MRS_FIELD_HWCAP(ID_AA64ISAR1, GPI, false, MRS_LOWER, MRS_USERSPACE,
1037 id_aa64isar1_gpi, id_aa64isar1_gpi_caps),
1038 MRS_FIELD_HWCAP(ID_AA64ISAR1, GPA, false, MRS_LOWER, MRS_USERSPACE,
1039 id_aa64isar1_gpa, id_aa64isar1_gpa_caps),
1040 MRS_FIELD_HWCAP(ID_AA64ISAR1, LRCPC, false, MRS_LOWER, MRS_USERSPACE,
1041 id_aa64isar1_lrcpc, id_aa64isar1_lrcpc_caps),
1042 MRS_FIELD_HWCAP(ID_AA64ISAR1, FCMA, false, MRS_LOWER, MRS_USERSPACE,
1043 id_aa64isar1_fcma, id_aa64isar1_fcma_caps),
1044 MRS_FIELD_HWCAP(ID_AA64ISAR1, JSCVT, false, MRS_LOWER, MRS_USERSPACE,
1045 id_aa64isar1_jscvt, id_aa64isar1_jscvt_caps),
1046 MRS_FIELD_HWCAP(ID_AA64ISAR1, API, false, MRS_LOWER, MRS_USERSPACE,
1047 id_aa64isar1_api, id_aa64isar1_api_caps),
1048 MRS_FIELD_HWCAP(ID_AA64ISAR1, APA, false, MRS_LOWER, MRS_USERSPACE,
1049 id_aa64isar1_apa, id_aa64isar1_apa_caps),
1050 MRS_FIELD_HWCAP(ID_AA64ISAR1, DPB, false, MRS_LOWER, MRS_USERSPACE,
1051 id_aa64isar1_dpb, id_aa64isar1_dpb_caps),
1052 MRS_FIELD_END,
1053 };
1054
1055
1056 /* ID_AA64ISAR2_EL1 */
1057 static const struct mrs_field_value id_aa64isar2_ats1a[] = {
1058 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, ATS1A, NONE, IMPL),
1059 MRS_FIELD_VALUE_END,
1060 };
1061
1062 static const struct mrs_field_value id_aa64isar2_cssc[] = {
1063 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, CSSC, NONE, IMPL),
1064 MRS_FIELD_VALUE_END,
1065 };
1066
1067 static const struct mrs_field_value id_aa64isar2_rprfm[] = {
1068 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, RPRFM, NONE, IMPL),
1069 MRS_FIELD_VALUE_END,
1070 };
1071
1072 static const struct mrs_field_value id_aa64isar2_prfmslc[] = {
1073 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, PRFMSLC, NONE, IMPL),
1074 MRS_FIELD_VALUE_END,
1075 };
1076
1077 static const struct mrs_field_value id_aa64isar2_clrbhb[] = {
1078 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, CLRBHB, NONE, IMPL),
1079 MRS_FIELD_VALUE_END,
1080 };
1081
1082 static const struct mrs_field_value id_aa64isar2_pac_frac[] = {
1083 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, PAC_frac, NONE, IMPL),
1084 MRS_FIELD_VALUE_END,
1085 };
1086
1087 static const struct mrs_field_value id_aa64isar2_bc[] = {
1088 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, BC, NONE, IMPL),
1089 MRS_FIELD_VALUE_END,
1090 };
1091
1092 static const struct mrs_field_value id_aa64isar2_mops[] = {
1093 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, MOPS, NONE, IMPL),
1094 MRS_FIELD_VALUE_END,
1095 };
1096
1097 static const struct mrs_field_value id_aa64isar2_apa3[] = {
1098 MRS_FIELD_VALUE(ID_AA64ISAR2_APA3_NONE, ""),
1099 MRS_FIELD_VALUE(ID_AA64ISAR2_APA3_PAC, "APA3 PAC"),
1100 MRS_FIELD_VALUE(ID_AA64ISAR2_APA3_EPAC, "APA3 EPAC"),
1101 MRS_FIELD_VALUE(ID_AA64ISAR2_APA3_EPAC2, "APA3 EPAC2"),
1102 MRS_FIELD_VALUE(ID_AA64ISAR2_APA3_FPAC, "APA3 FPAC"),
1103 MRS_FIELD_VALUE(ID_AA64ISAR2_APA3_FPAC_COMBINED,
1104 "APA3 FPAC+Combined"),
1105 MRS_FIELD_VALUE_END,
1106 };
1107
1108 static const struct mrs_field_hwcap id_aa64isar2_apa3_caps[] = {
1109 MRS_HWCAP(1, HWCAP_PACA, ID_AA64ISAR2_APA3_PAC),
1110 MRS_HWCAP_END
1111 };
1112
1113 static const struct mrs_field_value id_aa64isar2_gpa3[] = {
1114 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, GPA3, NONE, IMPL),
1115 MRS_FIELD_VALUE_END,
1116 };
1117
1118 static const struct mrs_field_hwcap id_aa64isar2_gpa3_caps[] = {
1119 MRS_HWCAP(1, HWCAP_PACG, ID_AA64ISAR2_GPA3_IMPL),
1120 MRS_HWCAP_END
1121 };
1122
1123 static const struct mrs_field_value id_aa64isar2_rpres[] = {
1124 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, RPRES, NONE, IMPL),
1125 MRS_FIELD_VALUE_END,
1126 };
1127
1128 static const struct mrs_field_hwcap id_aa64isar2_rpres_caps[] = {
1129 MRS_HWCAP(2, HWCAP2_RPRES, ID_AA64ISAR2_RPRES_IMPL),
1130 MRS_HWCAP_END
1131 };
1132
1133 static const struct mrs_field_value id_aa64isar2_wfxt[] = {
1134 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, WFxT, NONE, IMPL),
1135 MRS_FIELD_VALUE_END,
1136 };
1137
1138 static const struct mrs_field_hwcap id_aa64isar2_wfxt_caps[] = {
1139 MRS_HWCAP(2, HWCAP2_WFXT, ID_AA64ISAR2_WFxT_IMPL),
1140 MRS_HWCAP_END
1141 };
1142
1143 static const struct mrs_field id_aa64isar2_fields[] = {
1144 MRS_FIELD(ID_AA64ISAR2, ATS1A, false, MRS_LOWER, 0, id_aa64isar2_ats1a),
1145 MRS_FIELD(ID_AA64ISAR2, CSSC, false, MRS_LOWER, 0, id_aa64isar2_cssc),
1146 MRS_FIELD(ID_AA64ISAR2, RPRFM, false, MRS_LOWER, 0, id_aa64isar2_rprfm),
1147 MRS_FIELD(ID_AA64ISAR2, PRFMSLC, false, MRS_LOWER, 0, id_aa64isar2_prfmslc),
1148 MRS_FIELD(ID_AA64ISAR2, CLRBHB, false, MRS_LOWER, 0, id_aa64isar2_clrbhb),
1149 MRS_FIELD(ID_AA64ISAR2, PAC_frac, false, MRS_LOWER, 0,
1150 id_aa64isar2_pac_frac),
1151 MRS_FIELD(ID_AA64ISAR2, BC, false, MRS_LOWER, 0, id_aa64isar2_bc),
1152 MRS_FIELD(ID_AA64ISAR2, MOPS, false, MRS_LOWER, 0, id_aa64isar2_mops),
1153 MRS_FIELD_HWCAP(ID_AA64ISAR2, APA3, false, MRS_LOWER, MRS_USERSPACE,
1154 id_aa64isar2_apa3, id_aa64isar2_apa3_caps),
1155 MRS_FIELD_HWCAP(ID_AA64ISAR2, GPA3, false, MRS_LOWER, MRS_USERSPACE,
1156 id_aa64isar2_gpa3, id_aa64isar2_gpa3_caps),
1157 MRS_FIELD_HWCAP(ID_AA64ISAR2, RPRES, false, MRS_LOWER, MRS_USERSPACE,
1158 id_aa64isar2_rpres, id_aa64isar2_rpres_caps),
1159 MRS_FIELD_HWCAP(ID_AA64ISAR2, WFxT, false, MRS_LOWER, 0,
1160 id_aa64isar2_wfxt, id_aa64isar2_wfxt_caps),
1161 MRS_FIELD_END,
1162 };
1163
1164
1165 /* ID_AA64MMFR0_EL1 */
1166 static const struct mrs_field_value id_aa64mmfr0_ecv[] = {
1167 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, ECV, NONE, IMPL),
1168 MRS_FIELD_VALUE(ID_AA64MMFR0_ECV_POFF, "ECV POFF"),
1169 MRS_FIELD_VALUE_END,
1170 };
1171
1172 static const struct mrs_field_value id_aa64mmfr0_fgt[] = {
1173 MRS_FIELD_VALUE(ID_AA64MMFR0_FGT_NONE, ""),
1174 MRS_FIELD_VALUE(ID_AA64MMFR0_FGT_8_6, "FGT v8.6"),
1175 MRS_FIELD_VALUE(ID_AA64MMFR0_FGT_8_9, "FGT v8.9"),
1176 MRS_FIELD_VALUE_END,
1177 };
1178
1179 static const struct mrs_field_value id_aa64mmfr0_exs[] = {
1180 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, ExS, ALL, IMPL),
1181 MRS_FIELD_VALUE_END,
1182 };
1183
1184 static const struct mrs_field_value id_aa64mmfr0_tgran4_2[] = {
1185 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_2_TGran4, ""),
1186 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_2_NONE, "No S2 TGran4"),
1187 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_2_IMPL, "S2 TGran4"),
1188 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_2_LPA2, "S2 TGran4+LPA2"),
1189 MRS_FIELD_VALUE_END,
1190 };
1191
1192 static const struct mrs_field_value id_aa64mmfr0_tgran64_2[] = {
1193 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran64_2_TGran64, ""),
1194 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran64_2_NONE, "No S2 TGran64"),
1195 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran64_2_IMPL, "S2 TGran64"),
1196 MRS_FIELD_VALUE_END,
1197 };
1198
1199 static const struct mrs_field_value id_aa64mmfr0_tgran16_2[] = {
1200 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_2_TGran16, ""),
1201 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_2_NONE, "No S2 TGran16"),
1202 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_2_IMPL, "S2 TGran16"),
1203 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_2_LPA2, "S2 TGran16+LPA2"),
1204 MRS_FIELD_VALUE_END,
1205 };
1206
1207 static const struct mrs_field_value id_aa64mmfr0_tgran4[] = {
1208 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, TGran4, NONE, IMPL),
1209 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_LPA2, "TGran4+LPA2"),
1210 MRS_FIELD_VALUE_END,
1211 };
1212
1213 static const struct mrs_field_value id_aa64mmfr0_tgran64[] = {
1214 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, TGran64, NONE, IMPL),
1215 MRS_FIELD_VALUE_END,
1216 };
1217
1218 static const struct mrs_field_value id_aa64mmfr0_tgran16[] = {
1219 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, TGran16, NONE, IMPL),
1220 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_LPA2, "TGran16+LPA2"),
1221 MRS_FIELD_VALUE_END,
1222 };
1223
1224 static const struct mrs_field_value id_aa64mmfr0_bigendel0[] = {
1225 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, BigEndEL0, FIXED, MIXED),
1226 MRS_FIELD_VALUE_END,
1227 };
1228
1229 static const struct mrs_field_value id_aa64mmfr0_snsmem[] = {
1230 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, SNSMem, NONE, DISTINCT),
1231 MRS_FIELD_VALUE_END,
1232 };
1233
1234 static const struct mrs_field_value id_aa64mmfr0_bigend[] = {
1235 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, BigEnd, FIXED, MIXED),
1236 MRS_FIELD_VALUE_END,
1237 };
1238
1239 static const struct mrs_field_value id_aa64mmfr0_asidbits[] = {
1240 MRS_FIELD_VALUE(ID_AA64MMFR0_ASIDBits_8, "8bit ASID"),
1241 MRS_FIELD_VALUE(ID_AA64MMFR0_ASIDBits_16, "16bit ASID"),
1242 MRS_FIELD_VALUE_END,
1243 };
1244
1245 static const struct mrs_field_value id_aa64mmfr0_parange[] = {
1246 MRS_FIELD_VALUE(ID_AA64MMFR0_PARange_4G, "4GB PA"),
1247 MRS_FIELD_VALUE(ID_AA64MMFR0_PARange_64G, "64GB PA"),
1248 MRS_FIELD_VALUE(ID_AA64MMFR0_PARange_1T, "1TB PA"),
1249 MRS_FIELD_VALUE(ID_AA64MMFR0_PARange_4T, "4TB PA"),
1250 MRS_FIELD_VALUE(ID_AA64MMFR0_PARange_16T, "16TB PA"),
1251 MRS_FIELD_VALUE(ID_AA64MMFR0_PARange_256T, "256TB PA"),
1252 MRS_FIELD_VALUE(ID_AA64MMFR0_PARange_4P, "4PB PA"),
1253 MRS_FIELD_VALUE_END,
1254 };
1255
1256 static const struct mrs_field id_aa64mmfr0_fields[] = {
1257 MRS_FIELD(ID_AA64MMFR0, ECV, false, MRS_LOWER, 0, id_aa64mmfr0_ecv),
1258 MRS_FIELD(ID_AA64MMFR0, FGT, false, MRS_LOWER, 0, id_aa64mmfr0_fgt),
1259 MRS_FIELD(ID_AA64MMFR0, ExS, false, MRS_LOWER, 0, id_aa64mmfr0_exs),
1260 MRS_FIELD(ID_AA64MMFR0, TGran4_2, false, MRS_LOWER, 0,
1261 id_aa64mmfr0_tgran4_2),
1262 MRS_FIELD(ID_AA64MMFR0, TGran64_2, false, MRS_LOWER, 0,
1263 id_aa64mmfr0_tgran64_2),
1264 MRS_FIELD(ID_AA64MMFR0, TGran16_2, false, MRS_LOWER, 0,
1265 id_aa64mmfr0_tgran16_2),
1266 MRS_FIELD(ID_AA64MMFR0, TGran4, true, MRS_LOWER, 0,
1267 id_aa64mmfr0_tgran4),
1268 MRS_FIELD(ID_AA64MMFR0, TGran64, true, MRS_LOWER, 0,
1269 id_aa64mmfr0_tgran64),
1270 MRS_FIELD(ID_AA64MMFR0, TGran16, false, MRS_LOWER, 0,
1271 id_aa64mmfr0_tgran16),
1272 MRS_FIELD(ID_AA64MMFR0, BigEndEL0, false, MRS_LOWER, 0,
1273 id_aa64mmfr0_bigendel0),
1274 MRS_FIELD(ID_AA64MMFR0, SNSMem, false, MRS_LOWER, 0,
1275 id_aa64mmfr0_snsmem),
1276 MRS_FIELD(ID_AA64MMFR0, BigEnd, false, MRS_LOWER, 0,
1277 id_aa64mmfr0_bigend),
1278 MRS_FIELD(ID_AA64MMFR0, ASIDBits, false, MRS_LOWER, 0,
1279 id_aa64mmfr0_asidbits),
1280 MRS_FIELD(ID_AA64MMFR0, PARange, false, MRS_LOWER, 0,
1281 id_aa64mmfr0_parange),
1282 MRS_FIELD_END,
1283 };
1284
1285
1286 /* ID_AA64MMFR1_EL1 */
1287 static const struct mrs_field_value id_aa64mmfr1_ecbhb[] = {
1288 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, ECBHB, NONE, IMPL),
1289 MRS_FIELD_VALUE_END,
1290 };
1291
1292 static const struct mrs_field_value id_aa64mmfr1_cmovw[] = {
1293 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, CMOVW, NONE, IMPL),
1294 MRS_FIELD_VALUE_END,
1295 };
1296
1297 static const struct mrs_field_value id_aa64mmfr1_tidcp1[] = {
1298 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, TIDCP1, NONE, IMPL),
1299 MRS_FIELD_VALUE_END,
1300 };
1301
1302 static const struct mrs_field_value id_aa64mmfr1_ntlbpa[] = {
1303 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, nTLBPA, NONE, IMPL),
1304 MRS_FIELD_VALUE_END,
1305 };
1306
1307 static const struct mrs_field_value id_aa64mmfr1_afp[] = {
1308 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, AFP, NONE, IMPL),
1309 MRS_FIELD_VALUE_END,
1310 };
1311
1312 static const struct mrs_field_hwcap id_aa64mmfr1_afp_caps[] = {
1313 MRS_HWCAP(2, HWCAP2_AFP, ID_AA64MMFR1_AFP_IMPL),
1314 MRS_HWCAP_END
1315 };
1316
1317 static const struct mrs_field_value id_aa64mmfr1_hcx[] = {
1318 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, HCX, NONE, IMPL),
1319 MRS_FIELD_VALUE_END,
1320 };
1321
1322 static const struct mrs_field_value id_aa64mmfr1_ets[] = {
1323 MRS_FIELD_VALUE(ID_AA64MMFR1_ETS_NONE, ""),
1324 MRS_FIELD_VALUE(ID_AA64MMFR1_ETS_NONE2, ""),
1325 MRS_FIELD_VALUE(ID_AA64MMFR1_ETS_IMPL, "ETS2"),
1326 MRS_FIELD_VALUE_END,
1327 };
1328
1329 static const struct mrs_field_value id_aa64mmfr1_twed[] = {
1330 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, TWED, NONE, IMPL),
1331 MRS_FIELD_VALUE_END,
1332 };
1333
1334 static const struct mrs_field_value id_aa64mmfr1_xnx[] = {
1335 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, XNX, NONE, IMPL),
1336 MRS_FIELD_VALUE_END,
1337 };
1338
1339 static const struct mrs_field_value id_aa64mmfr1_specsei[] = {
1340 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, SpecSEI, NONE, IMPL),
1341 MRS_FIELD_VALUE_END,
1342 };
1343
1344 static const struct mrs_field_value id_aa64mmfr1_pan[] = {
1345 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, PAN, NONE, IMPL),
1346 MRS_FIELD_VALUE(ID_AA64MMFR1_PAN_ATS1E1, "PAN+ATS1E1"),
1347 MRS_FIELD_VALUE(ID_AA64MMFR1_PAN_EPAN, "EPAN"),
1348 MRS_FIELD_VALUE_END,
1349 };
1350
1351 static const struct mrs_field_value id_aa64mmfr1_lo[] = {
1352 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, LO, NONE, IMPL),
1353 MRS_FIELD_VALUE_END,
1354 };
1355
1356 static const struct mrs_field_value id_aa64mmfr1_hpds[] = {
1357 MRS_FIELD_VALUE(ID_AA64MMFR1_HPDS_NONE, ""),
1358 MRS_FIELD_VALUE(ID_AA64MMFR1_HPDS_HPD, "HPD"),
1359 MRS_FIELD_VALUE(ID_AA64MMFR1_HPDS_TTPBHA, "HPD+TTPBHA"),
1360 MRS_FIELD_VALUE_END,
1361 };
1362
1363 static const struct mrs_field_value id_aa64mmfr1_vh[] = {
1364 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, VH, NONE, IMPL),
1365 MRS_FIELD_VALUE_END,
1366 };
1367
1368 static const struct mrs_field_value id_aa64mmfr1_vmidbits[] = {
1369 MRS_FIELD_VALUE(ID_AA64MMFR1_VMIDBits_8, "8bit VMID"),
1370 MRS_FIELD_VALUE(ID_AA64MMFR1_VMIDBits_16, "16bit VMID"),
1371 MRS_FIELD_VALUE_END,
1372 };
1373
1374 static const struct mrs_field_value id_aa64mmfr1_hafdbs[] = {
1375 MRS_FIELD_VALUE(ID_AA64MMFR1_HAFDBS_NONE, ""),
1376 MRS_FIELD_VALUE(ID_AA64MMFR1_HAFDBS_AF, "HAF"),
1377 MRS_FIELD_VALUE(ID_AA64MMFR1_HAFDBS_AF_DBS, "HAF+DS"),
1378 MRS_FIELD_VALUE_END,
1379 };
1380
1381 static const struct mrs_field id_aa64mmfr1_fields[] = {
1382 MRS_FIELD(ID_AA64MMFR1, ECBHB, false, MRS_LOWER, 0, id_aa64mmfr1_ecbhb),
1383 MRS_FIELD(ID_AA64MMFR1, CMOVW, false, MRS_LOWER, 0, id_aa64mmfr1_cmovw),
1384 MRS_FIELD(ID_AA64MMFR1, TIDCP1, false, MRS_LOWER, 0,
1385 id_aa64mmfr1_tidcp1),
1386 MRS_FIELD(ID_AA64MMFR1, nTLBPA, false, MRS_LOWER, 0,
1387 id_aa64mmfr1_ntlbpa),
1388 MRS_FIELD_HWCAP(ID_AA64MMFR1, AFP, false, MRS_LOWER, 0,
1389 id_aa64mmfr1_afp, id_aa64mmfr1_afp_caps),
1390 MRS_FIELD(ID_AA64MMFR1, HCX, false, MRS_LOWER, 0, id_aa64mmfr1_hcx),
1391 MRS_FIELD(ID_AA64MMFR1, ETS, false, MRS_LOWER, 0, id_aa64mmfr1_ets),
1392 MRS_FIELD(ID_AA64MMFR1, TWED, false, MRS_LOWER, 0, id_aa64mmfr1_twed),
1393 MRS_FIELD(ID_AA64MMFR1, XNX, false, MRS_LOWER, 0, id_aa64mmfr1_xnx),
1394 /*
1395 * SpecSEI != 0 indicates the CPU might generate an external abort
1396 * under speculation, while 0 indicates it can't happen. It's safer
1397 * to incorrectly indicate it might happen when it can't rather than
1398 * say it can't happen when it could. As such use the largest value
1399 * found in the system.
1400 */
1401 MRS_FIELD(ID_AA64MMFR1, SpecSEI, false, MRS_HIGHER, 0,
1402 id_aa64mmfr1_specsei),
1403 MRS_FIELD(ID_AA64MMFR1, PAN, false, MRS_LOWER, 0, id_aa64mmfr1_pan),
1404 MRS_FIELD(ID_AA64MMFR1, LO, false, MRS_LOWER, 0, id_aa64mmfr1_lo),
1405 MRS_FIELD(ID_AA64MMFR1, HPDS, false, MRS_LOWER, 0, id_aa64mmfr1_hpds),
1406 MRS_FIELD(ID_AA64MMFR1, VH, false, MRS_LOWER, 0, id_aa64mmfr1_vh),
1407 MRS_FIELD(ID_AA64MMFR1, VMIDBits, false, MRS_LOWER, 0,
1408 id_aa64mmfr1_vmidbits),
1409 MRS_FIELD(ID_AA64MMFR1, HAFDBS, false, MRS_LOWER, 0, id_aa64mmfr1_hafdbs),
1410 MRS_FIELD_END,
1411 };
1412
1413
1414 /* ID_AA64MMFR2_EL1 */
1415 static const struct mrs_field_value id_aa64mmfr2_e0pd[] = {
1416 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, E0PD, NONE, IMPL),
1417 MRS_FIELD_VALUE_END,
1418 };
1419
1420 static const struct mrs_field_value id_aa64mmfr2_evt[] = {
1421 MRS_FIELD_VALUE(ID_AA64MMFR2_EVT_NONE, ""),
1422 MRS_FIELD_VALUE(ID_AA64MMFR2_EVT_8_2, "EVT-8.2"),
1423 MRS_FIELD_VALUE(ID_AA64MMFR2_EVT_8_5, "EVT-8.5"),
1424 MRS_FIELD_VALUE_END,
1425 };
1426
1427 static const struct mrs_field_value id_aa64mmfr2_bbm[] = {
1428 MRS_FIELD_VALUE(ID_AA64MMFR2_BBM_LEVEL0, ""),
1429 MRS_FIELD_VALUE(ID_AA64MMFR2_BBM_LEVEL1, "BBM level 1"),
1430 MRS_FIELD_VALUE(ID_AA64MMFR2_BBM_LEVEL2, "BBM level 2"),
1431 MRS_FIELD_VALUE_END,
1432 };
1433
1434 static const struct mrs_field_value id_aa64mmfr2_ttl[] = {
1435 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, TTL, NONE, IMPL),
1436 MRS_FIELD_VALUE_END,
1437 };
1438
1439 static const struct mrs_field_value id_aa64mmfr2_fwb[] = {
1440 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, FWB, NONE, IMPL),
1441 MRS_FIELD_VALUE_END,
1442 };
1443
1444 static const struct mrs_field_value id_aa64mmfr2_ids[] = {
1445 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, IDS, NONE, IMPL),
1446 MRS_FIELD_VALUE_END,
1447 };
1448
1449 static const struct mrs_field_value id_aa64mmfr2_at[] = {
1450 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, AT, NONE, IMPL),
1451 MRS_FIELD_VALUE_END,
1452 };
1453
1454 static const struct mrs_field_hwcap id_aa64mmfr2_at_caps[] = {
1455 MRS_HWCAP(1, HWCAP_USCAT, ID_AA64MMFR2_AT_IMPL),
1456 MRS_HWCAP_END
1457 };
1458
1459 static const struct mrs_field_value id_aa64mmfr2_st[] = {
1460 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, ST, NONE, IMPL),
1461 MRS_FIELD_VALUE_END,
1462 };
1463
1464 static const struct mrs_field_value id_aa64mmfr2_nv[] = {
1465 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, NV, NONE, 8_3),
1466 MRS_FIELD_VALUE(ID_AA64MMFR2_NV_8_4, "NV v8.4"),
1467 MRS_FIELD_VALUE_END,
1468 };
1469
1470 static const struct mrs_field_value id_aa64mmfr2_ccidx[] = {
1471 MRS_FIELD_VALUE(ID_AA64MMFR2_CCIDX_32, "32bit CCIDX"),
1472 MRS_FIELD_VALUE(ID_AA64MMFR2_CCIDX_64, "64bit CCIDX"),
1473 MRS_FIELD_VALUE_END,
1474 };
1475
1476 static const struct mrs_field_value id_aa64mmfr2_varange[] = {
1477 MRS_FIELD_VALUE(ID_AA64MMFR2_VARange_48, "48bit VA"),
1478 MRS_FIELD_VALUE(ID_AA64MMFR2_VARange_52, "52bit VA"),
1479 MRS_FIELD_VALUE_END,
1480 };
1481
1482 static const struct mrs_field_value id_aa64mmfr2_iesb[] = {
1483 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, IESB, NONE, IMPL),
1484 MRS_FIELD_VALUE_END,
1485 };
1486
1487 static const struct mrs_field_value id_aa64mmfr2_lsm[] = {
1488 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, LSM, NONE, IMPL),
1489 MRS_FIELD_VALUE_END,
1490 };
1491
1492 static const struct mrs_field_value id_aa64mmfr2_uao[] = {
1493 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, UAO, NONE, IMPL),
1494 MRS_FIELD_VALUE_END,
1495 };
1496
1497 static const struct mrs_field_value id_aa64mmfr2_cnp[] = {
1498 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, CnP, NONE, IMPL),
1499 MRS_FIELD_VALUE_END,
1500 };
1501
1502 static const struct mrs_field id_aa64mmfr2_fields[] = {
1503 MRS_FIELD(ID_AA64MMFR2, E0PD, false, MRS_LOWER, 0, id_aa64mmfr2_e0pd),
1504 MRS_FIELD(ID_AA64MMFR2, EVT, false, MRS_LOWER, 0, id_aa64mmfr2_evt),
1505 MRS_FIELD(ID_AA64MMFR2, BBM, false, MRS_LOWER, 0, id_aa64mmfr2_bbm),
1506 MRS_FIELD(ID_AA64MMFR2, TTL, false, MRS_LOWER, 0, id_aa64mmfr2_ttl),
1507 MRS_FIELD(ID_AA64MMFR2, FWB, false, MRS_LOWER, 0, id_aa64mmfr2_fwb),
1508 MRS_FIELD(ID_AA64MMFR2, IDS, false, MRS_LOWER, 0, id_aa64mmfr2_ids),
1509 MRS_FIELD_HWCAP(ID_AA64MMFR2, AT, false, MRS_LOWER, MRS_USERSPACE,
1510 id_aa64mmfr2_at, id_aa64mmfr2_at_caps),
1511 MRS_FIELD(ID_AA64MMFR2, ST, false, MRS_LOWER, 0, id_aa64mmfr2_st),
1512 MRS_FIELD(ID_AA64MMFR2, NV, false, MRS_LOWER, 0, id_aa64mmfr2_nv),
1513 MRS_FIELD(ID_AA64MMFR2, CCIDX, false, MRS_LOWER, 0, id_aa64mmfr2_ccidx),
1514 MRS_FIELD(ID_AA64MMFR2, VARange, false, MRS_LOWER, 0,
1515 id_aa64mmfr2_varange),
1516 MRS_FIELD(ID_AA64MMFR2, IESB, false, MRS_LOWER, 0, id_aa64mmfr2_iesb),
1517 MRS_FIELD(ID_AA64MMFR2, LSM, false, MRS_LOWER, 0, id_aa64mmfr2_lsm),
1518 MRS_FIELD(ID_AA64MMFR2, UAO, false, MRS_LOWER, 0, id_aa64mmfr2_uao),
1519 MRS_FIELD(ID_AA64MMFR2, CnP, false, MRS_LOWER, 0, id_aa64mmfr2_cnp),
1520 MRS_FIELD_END,
1521 };
1522
1523
1524 /* ID_AA64MMFR2_EL1 */
1525 static const struct mrs_field_value id_aa64mmfr3_spec_fpacc[] = {
1526 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR3, Spec_FPACC, NONE, IMPL),
1527 MRS_FIELD_VALUE_END,
1528 };
1529
1530 static const struct mrs_field_value id_aa64mmfr3_aderr[] = {
1531 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR3, ADERR, NONE, SOME),
1532 MRS_FIELD_VALUE_END,
1533 };
1534
1535 static const struct mrs_field_value id_aa64mmfr3_sderr[] = {
1536 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR3, SDERR, NONE, ALL),
1537 MRS_FIELD_VALUE_END,
1538 };
1539
1540 static const struct mrs_field_value id_aa64mmfr3_anerr[] = {
1541 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR3, ANERR, NONE, SOME),
1542 MRS_FIELD_VALUE_END,
1543 };
1544
1545 static const struct mrs_field_value id_aa64mmfr3_snerr[] = {
1546 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR3, SNERR, NONE, ALL),
1547 MRS_FIELD_VALUE_END,
1548 };
1549
1550 static const struct mrs_field_value id_aa64mmfr3_mec[] = {
1551 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR3, MEC, NONE, IMPL),
1552 MRS_FIELD_VALUE_END,
1553 };
1554
1555 static const struct mrs_field_value id_aa64mmfr3_aie[] = {
1556 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR3, AIE, NONE, IMPL),
1557 MRS_FIELD_VALUE_END,
1558 };
1559
1560 static const struct mrs_field_value id_aa64mmfr3_s2poe[] = {
1561 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR3, S2POE, NONE, IMPL),
1562 MRS_FIELD_VALUE_END,
1563 };
1564
1565 static const struct mrs_field_value id_aa64mmfr3_s1poe[] = {
1566 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR3, S1POE, NONE, IMPL),
1567 MRS_FIELD_VALUE_END,
1568 };
1569
1570 static const struct mrs_field_value id_aa64mmfr3_s2pie[] = {
1571 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR3, S2PIE, NONE, IMPL),
1572 MRS_FIELD_VALUE_END,
1573 };
1574
1575 static const struct mrs_field_value id_aa64mmfr3_s1pie[] = {
1576 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR3, S1PIE, NONE, IMPL),
1577 MRS_FIELD_VALUE_END,
1578 };
1579
1580 static const struct mrs_field_value id_aa64mmfr3_sctlrx[] = {
1581 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR3, SCTLRX, NONE, IMPL),
1582 MRS_FIELD_VALUE_END,
1583 };
1584
1585 static const struct mrs_field_value id_aa64mmfr3_tcrx[] = {
1586 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR3, TCRX, NONE, IMPL),
1587 MRS_FIELD_VALUE_END,
1588 };
1589
1590 static const struct mrs_field id_aa64mmfr3_fields[] = {
1591 MRS_FIELD(ID_AA64MMFR3, Spec_FPACC, false, MRS_LOWER, 0,
1592 id_aa64mmfr3_spec_fpacc),
1593 MRS_FIELD(ID_AA64MMFR3, ADERR, false, MRS_LOWER, 0, id_aa64mmfr3_aderr),
1594 MRS_FIELD(ID_AA64MMFR3, SDERR, false, MRS_LOWER, 0, id_aa64mmfr3_sderr),
1595 MRS_FIELD(ID_AA64MMFR3, ANERR, false, MRS_LOWER, 0, id_aa64mmfr3_anerr),
1596 MRS_FIELD(ID_AA64MMFR3, SNERR, false, MRS_LOWER, 0, id_aa64mmfr3_snerr),
1597 MRS_FIELD(ID_AA64MMFR3, MEC, false, MRS_LOWER, 0, id_aa64mmfr3_mec),
1598 MRS_FIELD(ID_AA64MMFR3, AIE, false, MRS_LOWER, 0, id_aa64mmfr3_aie),
1599 MRS_FIELD(ID_AA64MMFR3, S2POE, false, MRS_LOWER, 0, id_aa64mmfr3_s2poe),
1600 MRS_FIELD(ID_AA64MMFR3, S1POE, false, MRS_LOWER, 0, id_aa64mmfr3_s1poe),
1601 MRS_FIELD(ID_AA64MMFR3, S2PIE, false, MRS_LOWER, 0, id_aa64mmfr3_s2pie),
1602 MRS_FIELD(ID_AA64MMFR3, S1PIE, false, MRS_LOWER, 0, id_aa64mmfr3_s1pie),
1603 MRS_FIELD(ID_AA64MMFR3, SCTLRX, false, MRS_LOWER, 0,
1604 id_aa64mmfr3_sctlrx),
1605 MRS_FIELD(ID_AA64MMFR3, TCRX, false, MRS_LOWER, 0, id_aa64mmfr3_tcrx),
1606 MRS_FIELD_END,
1607 };
1608
1609
1610 /* ID_AA64MMFR4_EL1 */
1611 static const struct mrs_field id_aa64mmfr4_fields[] = {
1612 MRS_FIELD_END,
1613 };
1614
1615
1616 /* ID_AA64PFR0_EL1 */
1617 static const struct mrs_field_value id_aa64pfr0_csv3[] = {
1618 MRS_FIELD_VALUE(ID_AA64PFR0_CSV3_NONE, ""),
1619 MRS_FIELD_VALUE(ID_AA64PFR0_CSV3_ISOLATED, "CSV3"),
1620 MRS_FIELD_VALUE_END,
1621 };
1622
1623 static const struct mrs_field_value id_aa64pfr0_csv2[] = {
1624 MRS_FIELD_VALUE(ID_AA64PFR0_CSV2_NONE, ""),
1625 MRS_FIELD_VALUE(ID_AA64PFR0_CSV2_ISOLATED, "CSV2"),
1626 MRS_FIELD_VALUE(ID_AA64PFR0_CSV2_SCXTNUM, "CSV2_2"),
1627 MRS_FIELD_VALUE(ID_AA64PFR0_CSV2_3, "CSV2_3"),
1628 MRS_FIELD_VALUE_END,
1629 };
1630
1631 static const struct mrs_field_value id_aa64pfr0_rme[] = {
1632 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, RME, NONE, IMPL),
1633 MRS_FIELD_VALUE_END,
1634 };
1635
1636 static const struct mrs_field_value id_aa64pfr0_dit[] = {
1637 MRS_FIELD_VALUE(ID_AA64PFR0_DIT_NONE, ""),
1638 MRS_FIELD_VALUE(ID_AA64PFR0_DIT_PSTATE, "PSTATE.DIT"),
1639 MRS_FIELD_VALUE_END,
1640 };
1641
1642 static const struct mrs_field_hwcap id_aa64pfr0_dit_caps[] = {
1643 MRS_HWCAP(1, HWCAP_DIT, ID_AA64PFR0_DIT_PSTATE),
1644 MRS_HWCAP_END
1645 };
1646
1647 static const struct mrs_field_value id_aa64pfr0_amu[] = {
1648 MRS_FIELD_VALUE(ID_AA64PFR0_AMU_NONE, ""),
1649 MRS_FIELD_VALUE(ID_AA64PFR0_AMU_V1, "AMUv1"),
1650 MRS_FIELD_VALUE(ID_AA64PFR0_AMU_V1_1, "AMUv1p1"),
1651 MRS_FIELD_VALUE_END,
1652 };
1653
1654 static const struct mrs_field_value id_aa64pfr0_mpam[] = {
1655 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, MPAM, NONE, IMPL),
1656 MRS_FIELD_VALUE_END,
1657 };
1658
1659 static const struct mrs_field_value id_aa64pfr0_sel2[] = {
1660 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, SEL2, NONE, IMPL),
1661 MRS_FIELD_VALUE_END,
1662 };
1663
1664 static const struct mrs_field_value id_aa64pfr0_sve[] = {
1665 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, SVE, NONE, IMPL),
1666 MRS_FIELD_VALUE_END,
1667 };
1668
1669 static const struct mrs_field_hwcap id_aa64pfr0_sve_caps[] = {
1670 MRS_HWCAP(1, HWCAP_SVE, ID_AA64PFR0_SVE_IMPL),
1671 MRS_HWCAP_END
1672 };
1673
1674 static const struct mrs_field_value id_aa64pfr0_ras[] = {
1675 MRS_FIELD_VALUE(ID_AA64PFR0_RAS_NONE, ""),
1676 MRS_FIELD_VALUE(ID_AA64PFR0_RAS_IMPL, "RAS"),
1677 MRS_FIELD_VALUE(ID_AA64PFR0_RAS_8_4, "RAS v8.4"),
1678 MRS_FIELD_VALUE(ID_AA64PFR0_RAS_8_9, "RAS v8.9"),
1679 MRS_FIELD_VALUE_END,
1680 };
1681
1682 static const struct mrs_field_value id_aa64pfr0_gic[] = {
1683 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, GIC, CPUIF_NONE, CPUIF_EN),
1684 MRS_FIELD_VALUE(ID_AA64PFR0_GIC_CPUIF_NONE, ""),
1685 MRS_FIELD_VALUE(ID_AA64PFR0_GIC_CPUIF_EN, "GIC"),
1686 MRS_FIELD_VALUE(ID_AA64PFR0_GIC_CPUIF_4_1, "GIC 4.1"),
1687 MRS_FIELD_VALUE_END,
1688 };
1689
1690 static const struct mrs_field_value id_aa64pfr0_advsimd[] = {
1691 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, AdvSIMD, NONE, IMPL),
1692 MRS_FIELD_VALUE(ID_AA64PFR0_AdvSIMD_HP, "AdvSIMD+HP"),
1693 MRS_FIELD_VALUE_END,
1694 };
1695
1696 static const struct mrs_field_hwcap id_aa64pfr0_advsimd_caps[] = {
1697 MRS_HWCAP(1, HWCAP_ASIMD, ID_AA64PFR0_AdvSIMD_IMPL),
1698 MRS_HWCAP(1, HWCAP_ASIMDHP, ID_AA64PFR0_AdvSIMD_HP),
1699 MRS_HWCAP_END
1700 };
1701
1702 static const struct mrs_field_value id_aa64pfr0_fp[] = {
1703 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, FP, NONE, IMPL),
1704 MRS_FIELD_VALUE(ID_AA64PFR0_FP_HP, "FP+HP"),
1705 MRS_FIELD_VALUE_END,
1706 };
1707
1708 static const struct mrs_field_hwcap id_aa64pfr0_fp_caps[] = {
1709 MRS_HWCAP(1, HWCAP_FP, ID_AA64PFR0_FP_IMPL),
1710 MRS_HWCAP(1, HWCAP_FPHP, ID_AA64PFR0_FP_HP),
1711 MRS_HWCAP_END
1712 };
1713
1714 static const struct mrs_field_value id_aa64pfr0_el3[] = {
1715 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, EL3, NONE, 64),
1716 MRS_FIELD_VALUE(ID_AA64PFR0_EL3_64_32, "EL3 32"),
1717 MRS_FIELD_VALUE_END,
1718 };
1719
1720 static const struct mrs_field_value id_aa64pfr0_el2[] = {
1721 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, EL2, NONE, 64),
1722 MRS_FIELD_VALUE(ID_AA64PFR0_EL2_64_32, "EL2 32"),
1723 MRS_FIELD_VALUE_END,
1724 };
1725
1726 static const struct mrs_field_value id_aa64pfr0_el1[] = {
1727 MRS_FIELD_VALUE(ID_AA64PFR0_EL1_64, "EL1"),
1728 MRS_FIELD_VALUE(ID_AA64PFR0_EL1_64_32, "EL1 32"),
1729 MRS_FIELD_VALUE_END,
1730 };
1731
1732 static const struct mrs_field_value id_aa64pfr0_el0[] = {
1733 MRS_FIELD_VALUE(ID_AA64PFR0_EL0_64, "EL0"),
1734 MRS_FIELD_VALUE(ID_AA64PFR0_EL0_64_32, "EL0 32"),
1735 MRS_FIELD_VALUE_END,
1736 };
1737
1738 static const struct mrs_field id_aa64pfr0_fields[] = {
1739 MRS_FIELD(ID_AA64PFR0, CSV3, false, MRS_LOWER, 0, id_aa64pfr0_csv3),
1740 MRS_FIELD(ID_AA64PFR0, CSV2, false, MRS_LOWER, 0, id_aa64pfr0_csv2),
1741 MRS_FIELD(ID_AA64PFR0, RME, false, MRS_LOWER, 0, id_aa64pfr0_rme),
1742 MRS_FIELD_HWCAP(ID_AA64PFR0, DIT, false, MRS_LOWER, MRS_USERSPACE,
1743 id_aa64pfr0_dit, id_aa64pfr0_dit_caps),
1744 MRS_FIELD(ID_AA64PFR0, AMU, false, MRS_LOWER, 0, id_aa64pfr0_amu),
1745 MRS_FIELD(ID_AA64PFR0, MPAM, false, MRS_LOWER, 0, id_aa64pfr0_mpam),
1746 MRS_FIELD(ID_AA64PFR0, SEL2, false, MRS_LOWER, 0, id_aa64pfr0_sel2),
1747 MRS_FIELD_HWCAP(ID_AA64PFR0, SVE, false, MRS_LOWER,
1748 MRS_FREEBSD, id_aa64pfr0_sve, id_aa64pfr0_sve_caps),
1749 MRS_FIELD(ID_AA64PFR0, RAS, false, MRS_LOWER, 0, id_aa64pfr0_ras),
1750 MRS_FIELD(ID_AA64PFR0, GIC, false, MRS_LOWER, 0, id_aa64pfr0_gic),
1751 MRS_FIELD_HWCAP(ID_AA64PFR0, AdvSIMD, true, MRS_LOWER, MRS_USERSPACE,
1752 id_aa64pfr0_advsimd, id_aa64pfr0_advsimd_caps),
1753 MRS_FIELD_HWCAP(ID_AA64PFR0, FP, true, MRS_LOWER, MRS_USERSPACE,
1754 id_aa64pfr0_fp, id_aa64pfr0_fp_caps),
1755 MRS_FIELD(ID_AA64PFR0, EL3, false, MRS_LOWER, 0, id_aa64pfr0_el3),
1756 MRS_FIELD(ID_AA64PFR0, EL2, false, MRS_LOWER, 0, id_aa64pfr0_el2),
1757 MRS_FIELD(ID_AA64PFR0, EL1, false, MRS_LOWER, MRS_USERSPACE,
1758 id_aa64pfr0_el1),
1759 MRS_FIELD(ID_AA64PFR0, EL0, false, MRS_LOWER, MRS_USERSPACE,
1760 id_aa64pfr0_el0),
1761 MRS_FIELD_END,
1762 };
1763
1764
1765 /* ID_AA64PFR1_EL1 */
1766 static const struct mrs_field_value id_aa64pfr1_pfar[] = {
1767 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR1, PFAR, NONE, IMPL),
1768 MRS_FIELD_VALUE_END,
1769 };
1770
1771 static const struct mrs_field_value id_aa64pfr1_df2[] = {
1772 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR1, DF2, NONE, IMPL),
1773 MRS_FIELD_VALUE_END,
1774 };
1775
1776 static const struct mrs_field_value id_aa64pfr1_mtex[] = {
1777 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR1, MTEX, NONE, IMPL),
1778 MRS_FIELD_VALUE_END,
1779 };
1780
1781 static const struct mrs_field_value id_aa64pfr1_the[] = {
1782 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR1, THE, NONE, IMPL),
1783 MRS_FIELD_VALUE_END,
1784 };
1785
1786 static const struct mrs_field_value id_aa64pfr1_mtefrac[] = {
1787 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR1, MTE_frac, NONE, IMPL),
1788 MRS_FIELD_VALUE_END,
1789 };
1790
1791 static const struct mrs_field_value id_aa64pfr1_nmi[] = {
1792 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR1, NMI, NONE, IMPL),
1793 MRS_FIELD_VALUE_END,
1794 };
1795
1796 static const struct mrs_field_value id_aa64pfr1_csv2_frac[] = {
1797 MRS_FIELD_VALUE(ID_AA64PFR1_CSV2_frac_p0, ""),
1798 MRS_FIELD_VALUE(ID_AA64PFR1_CSV2_frac_p1, "CSV2 p1"),
1799 MRS_FIELD_VALUE(ID_AA64PFR1_CSV2_frac_p2, "CSV2 p2"),
1800 MRS_FIELD_VALUE_END,
1801 };
1802
1803 static const struct mrs_field_value id_aa64pfr1_rndr_trap[] = {
1804 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR1, RNDR_trap, NONE, IMPL),
1805 MRS_FIELD_VALUE_END,
1806 };
1807
1808 static const struct mrs_field_value id_aa64pfr1_sme[] = {
1809 MRS_FIELD_VALUE(ID_AA64PFR1_SME_NONE, ""),
1810 MRS_FIELD_VALUE(ID_AA64PFR1_SME_SME, "SME"),
1811 MRS_FIELD_VALUE(ID_AA64PFR1_SME_SME2, "SME2"),
1812 MRS_FIELD_VALUE_END,
1813 };
1814
1815 static const struct mrs_field_value id_aa64pfr1_mpam_frac[] = {
1816 MRS_FIELD_VALUE(ID_AA64PFR1_MPAM_frac_p0, ""),
1817 MRS_FIELD_VALUE(ID_AA64PFR1_MPAM_frac_p1, "MPAM p1"),
1818 MRS_FIELD_VALUE_END,
1819 };
1820
1821 static const struct mrs_field_value id_aa64pfr1_ras_frac[] = {
1822 MRS_FIELD_VALUE(ID_AA64PFR1_RAS_frac_p0, ""),
1823 MRS_FIELD_VALUE(ID_AA64PFR1_RAS_frac_p1, "RAS p1"),
1824 MRS_FIELD_VALUE_END,
1825 };
1826
1827 static const struct mrs_field_value id_aa64pfr1_mte[] = {
1828 MRS_FIELD_VALUE(ID_AA64PFR1_MTE_NONE, ""),
1829 MRS_FIELD_VALUE(ID_AA64PFR1_MTE_MTE, "MTE"),
1830 MRS_FIELD_VALUE(ID_AA64PFR1_MTE_MTE2, "MTE2"),
1831 MRS_FIELD_VALUE(ID_AA64PFR1_MTE_MTE3, "MTE3"),
1832 MRS_FIELD_VALUE_END,
1833 };
1834
1835 static const struct mrs_field_value id_aa64pfr1_ssbs[] = {
1836 MRS_FIELD_VALUE(ID_AA64PFR1_SSBS_NONE, ""),
1837 MRS_FIELD_VALUE(ID_AA64PFR1_SSBS_PSTATE, "PSTATE.SSBS"),
1838 MRS_FIELD_VALUE(ID_AA64PFR1_SSBS_PSTATE_MSR, "PSTATE.SSBS MSR"),
1839 MRS_FIELD_VALUE_END,
1840 };
1841
1842 static const struct mrs_field_hwcap id_aa64pfr1_ssbs_caps[] = {
1843 MRS_HWCAP(1, HWCAP_SSBS, ID_AA64PFR1_SSBS_PSTATE),
1844 MRS_HWCAP_END
1845 };
1846
1847 static const struct mrs_field_value id_aa64pfr1_bt[] = {
1848 MRS_FIELD_VALUE(ID_AA64PFR1_BT_NONE, ""),
1849 MRS_FIELD_VALUE(ID_AA64PFR1_BT_IMPL, "BTI"),
1850 MRS_FIELD_VALUE_END,
1851 };
1852
1853 static const struct mrs_field_hwcap id_aa64pfr1_bt_caps[] = {
1854 MRS_HWCAP(2, HWCAP2_BTI, ID_AA64PFR1_BT_IMPL),
1855 MRS_HWCAP_END
1856 };
1857
1858 static const struct mrs_field id_aa64pfr1_fields[] = {
1859 MRS_FIELD(ID_AA64PFR1, PFAR, false, MRS_LOWER, 0, id_aa64pfr1_pfar),
1860 MRS_FIELD(ID_AA64PFR1, DF2, false, MRS_LOWER, 0, id_aa64pfr1_df2),
1861 MRS_FIELD(ID_AA64PFR1, MTEX, false, MRS_LOWER, 0, id_aa64pfr1_mtex),
1862 MRS_FIELD(ID_AA64PFR1, THE, false, MRS_LOWER, 0, id_aa64pfr1_the),
1863 MRS_FIELD(ID_AA64PFR1, MTE_frac, true, MRS_LOWER, 0,
1864 id_aa64pfr1_mtefrac),
1865 MRS_FIELD(ID_AA64PFR1, NMI, false, MRS_LOWER, 0, id_aa64pfr1_nmi),
1866 MRS_FIELD(ID_AA64PFR1, CSV2_frac, false, MRS_LOWER, 0,
1867 id_aa64pfr1_csv2_frac),
1868 MRS_FIELD(ID_AA64PFR1, RNDR_trap, false, MRS_LOWER, 0,
1869 id_aa64pfr1_rndr_trap),
1870 MRS_FIELD(ID_AA64PFR1, SME, false, MRS_LOWER, 0, id_aa64pfr1_sme),
1871 MRS_FIELD(ID_AA64PFR1, MPAM_frac, false, MRS_LOWER, 0,
1872 id_aa64pfr1_mpam_frac),
1873 MRS_FIELD(ID_AA64PFR1, RAS_frac, false, MRS_LOWER, 0,
1874 id_aa64pfr1_ras_frac),
1875 MRS_FIELD(ID_AA64PFR1, MTE, false, MRS_LOWER, 0, id_aa64pfr1_mte),
1876 MRS_FIELD_HWCAP(ID_AA64PFR1, SSBS, false, MRS_LOWER, MRS_USERSPACE,
1877 id_aa64pfr1_ssbs, id_aa64pfr1_ssbs_caps),
1878 MRS_FIELD_HWCAP(ID_AA64PFR1, BT, false, MRS_LOWER,
1879 MRS_FREEBSD, id_aa64pfr1_bt, id_aa64pfr1_bt_caps),
1880 MRS_FIELD_END,
1881 };
1882
1883
1884 /* ID_AA64PFR2_EL1 */
1885 static const struct mrs_field id_aa64pfr2_fields[] = {
1886 MRS_FIELD_END,
1887 };
1888
1889
1890 /* ID_AA64ZFR0_EL1 */
1891 static const struct mrs_field_value id_aa64zfr0_f64mm[] = {
1892 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ZFR0, F64MM, NONE, IMPL),
1893 MRS_FIELD_VALUE_END,
1894 };
1895
1896 static const struct mrs_field_hwcap id_aa64zfr0_f64mm_caps[] = {
1897 MRS_HWCAP(2, HWCAP2_SVEF64MM, ID_AA64ZFR0_F64MM_IMPL),
1898 MRS_HWCAP_END,
1899 };
1900
1901 static const struct mrs_field_value id_aa64zfr0_f32mm[] = {
1902 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ZFR0, F32MM, NONE, IMPL),
1903 MRS_FIELD_VALUE_END,
1904 };
1905
1906 static const struct mrs_field_hwcap id_aa64zfr0_f32mm_caps[] = {
1907 MRS_HWCAP(2, HWCAP2_SVEF32MM, ID_AA64ZFR0_F32MM_IMPL),
1908 MRS_HWCAP_END,
1909 };
1910
1911 static const struct mrs_field_value id_aa64zfr0_i8mm[] = {
1912 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ZFR0, I8MM, NONE, IMPL),
1913 MRS_FIELD_VALUE_END,
1914 };
1915
1916 static const struct mrs_field_hwcap id_aa64zfr0_i8mm_caps[] = {
1917 MRS_HWCAP(2, HWCAP2_SVEI8MM, ID_AA64ZFR0_I8MM_IMPL),
1918 MRS_HWCAP_END,
1919 };
1920
1921 static const struct mrs_field_value id_aa64zfr0_sm4[] = {
1922 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ZFR0, SM4, NONE, IMPL),
1923 MRS_FIELD_VALUE_END,
1924 };
1925
1926 static const struct mrs_field_hwcap id_aa64zfr0_sm4_caps[] = {
1927 MRS_HWCAP(2, HWCAP2_SVESM4, ID_AA64ZFR0_SM4_IMPL),
1928 MRS_HWCAP_END,
1929 };
1930
1931 static const struct mrs_field_value id_aa64zfr0_sha3[] = {
1932 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ZFR0, SHA3, NONE, IMPL),
1933 MRS_FIELD_VALUE_END,
1934 };
1935
1936 static const struct mrs_field_hwcap id_aa64zfr0_sha3_caps[] = {
1937 MRS_HWCAP(2, HWCAP2_SVESHA3, ID_AA64ZFR0_SHA3_IMPL),
1938 MRS_HWCAP_END,
1939 };
1940
1941 static const struct mrs_field_value id_aa64zfr0_bf16[] = {
1942 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ZFR0, BF16, NONE, BASE),
1943 MRS_FIELD_VALUE(ID_AA64ZFR0_BF16_EBF, "BF16+EBF"),
1944 MRS_FIELD_VALUE_END,
1945 };
1946
1947 static const struct mrs_field_hwcap id_aa64zfr0_bf16_caps[] = {
1948 MRS_HWCAP(2, HWCAP2_SVEBF16, ID_AA64ZFR0_BF16_BASE),
1949 MRS_HWCAP(2, HWCAP2_SVE_EBF16, ID_AA64ZFR0_BF16_EBF),
1950 MRS_HWCAP_END,
1951 };
1952
1953 static const struct mrs_field_value id_aa64zfr0_bitperm[] = {
1954 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ZFR0, BitPerm, NONE, IMPL),
1955 MRS_FIELD_VALUE_END,
1956 };
1957
1958 static const struct mrs_field_hwcap id_aa64zfr0_bitperm_caps[] = {
1959 MRS_HWCAP(2, HWCAP2_SVEBITPERM, ID_AA64ZFR0_BitPerm_IMPL),
1960 MRS_HWCAP_END,
1961 };
1962
1963 static const struct mrs_field_value id_aa64zfr0_aes[] = {
1964 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ZFR0, AES, NONE, BASE),
1965 MRS_FIELD_VALUE(ID_AA64ZFR0_AES_PMULL, "AES+PMULL"),
1966 MRS_FIELD_VALUE_END,
1967 };
1968
1969 static const struct mrs_field_hwcap id_aa64zfr0_aes_caps[] = {
1970 MRS_HWCAP(2, HWCAP2_SVEAES, ID_AA64ZFR0_AES_BASE),
1971 MRS_HWCAP(2, HWCAP2_SVEPMULL, ID_AA64ZFR0_AES_PMULL),
1972 MRS_HWCAP_END,
1973 };
1974
1975 static const struct mrs_field_value id_aa64zfr0_svever[] = {
1976 MRS_FIELD_VALUE(ID_AA64ZFR0_SVEver_SVE1, "SVE1"),
1977 MRS_FIELD_VALUE(ID_AA64ZFR0_SVEver_SVE2, "SVE2"),
1978 MRS_FIELD_VALUE(ID_AA64ZFR0_SVEver_SVE2P1, "SVE2P1"),
1979 MRS_FIELD_VALUE_END,
1980 };
1981
1982 static const struct mrs_field_hwcap id_aa64zfr0_svever_caps[] = {
1983 MRS_HWCAP(2, HWCAP2_SVE2, ID_AA64ZFR0_SVEver_SVE2),
1984 MRS_HWCAP(2, HWCAP2_SVE2P1, ID_AA64ZFR0_SVEver_SVE2P1),
1985 MRS_HWCAP_END,
1986 };
1987
1988 static const struct mrs_field id_aa64zfr0_fields[] = {
1989 MRS_FIELD_HWCAP(ID_AA64ZFR0, F64MM, false, MRS_LOWER, MRS_USERSPACE,
1990 id_aa64zfr0_f64mm, id_aa64zfr0_f64mm_caps),
1991 MRS_FIELD_HWCAP(ID_AA64ZFR0, F32MM, false, MRS_LOWER, MRS_USERSPACE,
1992 id_aa64zfr0_f32mm, id_aa64zfr0_f32mm_caps),
1993 MRS_FIELD_HWCAP(ID_AA64ZFR0, I8MM, false, MRS_LOWER, MRS_USERSPACE,
1994 id_aa64zfr0_i8mm, id_aa64zfr0_i8mm_caps),
1995 MRS_FIELD_HWCAP(ID_AA64ZFR0, SM4, false, MRS_LOWER, MRS_USERSPACE,
1996 id_aa64zfr0_sm4, id_aa64zfr0_sm4_caps),
1997 MRS_FIELD_HWCAP(ID_AA64ZFR0, SHA3, false, MRS_LOWER, MRS_USERSPACE,
1998 id_aa64zfr0_sha3, id_aa64zfr0_sha3_caps),
1999 MRS_FIELD_HWCAP(ID_AA64ZFR0, BF16, false, MRS_LOWER, MRS_USERSPACE,
2000 id_aa64zfr0_bf16, id_aa64zfr0_bf16_caps),
2001 MRS_FIELD_HWCAP(ID_AA64ZFR0, BitPerm, false, MRS_LOWER, MRS_USERSPACE,
2002 id_aa64zfr0_bitperm, id_aa64zfr0_bitperm_caps),
2003 MRS_FIELD_HWCAP(ID_AA64ZFR0, AES, false, MRS_LOWER, MRS_USERSPACE,
2004 id_aa64zfr0_aes, id_aa64zfr0_aes_caps),
2005 MRS_FIELD_HWCAP(ID_AA64ZFR0, SVEver, false, MRS_LOWER, MRS_USERSPACE,
2006 id_aa64zfr0_svever, id_aa64zfr0_svever_caps),
2007 MRS_FIELD_END,
2008 };
2009
2010
2011 #ifdef COMPAT_FREEBSD32
2012 /* ID_ISAR5_EL1 */
2013 static const struct mrs_field_value id_isar5_vcma[] = {
2014 MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, VCMA, NONE, IMPL),
2015 MRS_FIELD_VALUE_END,
2016 };
2017
2018 static const struct mrs_field_value id_isar5_rdm[] = {
2019 MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, RDM, NONE, IMPL),
2020 MRS_FIELD_VALUE_END,
2021 };
2022
2023 static const struct mrs_field_value id_isar5_crc32[] = {
2024 MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, CRC32, NONE, IMPL),
2025 MRS_FIELD_VALUE_END,
2026 };
2027
2028 static const struct mrs_field_hwcap id_isar5_crc32_caps[] = {
2029 MRS_HWCAP(2, HWCAP32_2_CRC32, ID_ISAR5_CRC32_IMPL),
2030 MRS_HWCAP_END
2031 };
2032
2033 static const struct mrs_field_value id_isar5_sha2[] = {
2034 MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, SHA2, NONE, IMPL),
2035 MRS_FIELD_VALUE_END,
2036 };
2037
2038 static const struct mrs_field_hwcap id_isar5_sha2_caps[] = {
2039 MRS_HWCAP(2, HWCAP32_2_SHA2, ID_ISAR5_SHA2_IMPL),
2040 MRS_HWCAP_END
2041 };
2042
2043 static const struct mrs_field_value id_isar5_sha1[] = {
2044 MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, SHA1, NONE, IMPL),
2045 MRS_FIELD_VALUE_END,
2046 };
2047
2048 static const struct mrs_field_hwcap id_isar5_sha1_caps[] = {
2049 MRS_HWCAP(2, HWCAP32_2_SHA1, ID_ISAR5_SHA1_IMPL),
2050 MRS_HWCAP_END
2051 };
2052
2053 static const struct mrs_field_value id_isar5_aes[] = {
2054 MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, AES, NONE, BASE),
2055 MRS_FIELD_VALUE(ID_ISAR5_AES_VMULL, "AES+VMULL"),
2056 MRS_FIELD_VALUE_END,
2057 };
2058
2059 static const struct mrs_field_hwcap id_isar5_aes_caps[] = {
2060 MRS_HWCAP(2, HWCAP32_2_AES, ID_ISAR5_AES_BASE),
2061 MRS_HWCAP(2, HWCAP32_2_PMULL, ID_ISAR5_AES_VMULL),
2062 MRS_HWCAP_END
2063 };
2064
2065 static const struct mrs_field_value id_isar5_sevl[] = {
2066 MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, SEVL, NOP, IMPL),
2067 MRS_FIELD_VALUE_END,
2068 };
2069
2070 static const struct mrs_field id_isar5_fields[] = {
2071 MRS_FIELD(ID_ISAR5, VCMA, false, MRS_LOWER,MRS_USERSPACE,
2072 id_isar5_vcma),
2073 MRS_FIELD(ID_ISAR5, RDM, false, MRS_LOWER, MRS_USERSPACE, id_isar5_rdm),
2074 MRS_FIELD_HWCAP(ID_ISAR5, CRC32, false, MRS_LOWER, MRS_USERSPACE,
2075 id_isar5_crc32, id_isar5_crc32_caps),
2076 MRS_FIELD_HWCAP(ID_ISAR5, SHA2, false, MRS_LOWER, MRS_USERSPACE,
2077 id_isar5_sha2, id_isar5_sha2_caps),
2078 MRS_FIELD_HWCAP(ID_ISAR5, SHA1, false, MRS_LOWER, MRS_USERSPACE,
2079 id_isar5_sha1, id_isar5_sha1_caps),
2080 MRS_FIELD_HWCAP(ID_ISAR5, AES, false, MRS_LOWER, MRS_USERSPACE,
2081 id_isar5_aes, id_isar5_aes_caps),
2082 MRS_FIELD(ID_ISAR5, SEVL, false, MRS_LOWER, MRS_USERSPACE,
2083 id_isar5_sevl),
2084 MRS_FIELD_END,
2085 };
2086
2087 /* MVFR0 */
2088 static const struct mrs_field_value mvfr0_fpround[] = {
2089 MRS_FIELD_VALUE_NONE_IMPL(MVFR0, FPRound, NONE, IMPL),
2090 MRS_FIELD_VALUE_END,
2091 };
2092
2093 static const struct mrs_field_value mvfr0_fpsqrt[] = {
2094 MRS_FIELD_VALUE_NONE_IMPL(MVFR0, FPSqrt, NONE, IMPL),
2095 MRS_FIELD_VALUE_END,
2096 };
2097
2098 static const struct mrs_field_value mvfr0_fpdivide[] = {
2099 MRS_FIELD_VALUE_NONE_IMPL(MVFR0, FPDivide, NONE, IMPL),
2100 MRS_FIELD_VALUE_END,
2101 };
2102
2103 static const struct mrs_field_value mvfr0_fptrap[] = {
2104 MRS_FIELD_VALUE_NONE_IMPL(MVFR0, FPTrap, NONE, IMPL),
2105 MRS_FIELD_VALUE_END,
2106 };
2107
2108 static const struct mrs_field_value mvfr0_fpdp[] = {
2109 MRS_FIELD_VALUE(MVFR0_FPDP_NONE, ""),
2110 MRS_FIELD_VALUE(MVFR0_FPDP_VFP_v2, "DP VFPv2"),
2111 MRS_FIELD_VALUE(MVFR0_FPDP_VFP_v3_v4, "DP VFPv3+v4"),
2112 MRS_FIELD_VALUE_END,
2113 };
2114
2115 static const struct mrs_field_hwcap mvfr0_fpdp_caps[] = {
2116 MRS_HWCAP(1, HWCAP32_VFP, MVFR0_FPDP_VFP_v2),
2117 MRS_HWCAP(1, HWCAP32_VFPv3, MVFR0_FPDP_VFP_v3_v4),
2118 MRS_HWCAP_END
2119 };
2120
2121 static const struct mrs_field_value mvfr0_fpsp[] = {
2122 MRS_FIELD_VALUE(MVFR0_FPSP_NONE, ""),
2123 MRS_FIELD_VALUE(MVFR0_FPSP_VFP_v2, "SP VFPv2"),
2124 MRS_FIELD_VALUE(MVFR0_FPSP_VFP_v3_v4, "SP VFPv3+v4"),
2125 MRS_FIELD_VALUE_END,
2126 };
2127
2128 static const struct mrs_field_value mvfr0_simdreg[] = {
2129 MRS_FIELD_VALUE(MVFR0_SIMDReg_NONE, ""),
2130 MRS_FIELD_VALUE(MVFR0_SIMDReg_FP, "FP 16x64"),
2131 MRS_FIELD_VALUE(MVFR0_SIMDReg_AdvSIMD, "AdvSIMD"),
2132 MRS_FIELD_VALUE_END,
2133 };
2134
2135 static const struct mrs_field mvfr0_fields[] = {
2136 MRS_FIELD(MVFR0, FPRound, false, MRS_LOWER, MRS_USERSPACE,
2137 mvfr0_fpround),
2138 MRS_FIELD(MVFR0, FPSqrt, false, MRS_LOWER, MRS_USERSPACE,
2139 mvfr0_fpsqrt),
2140 MRS_FIELD(MVFR0, FPDivide, false, MRS_LOWER, MRS_USERSPACE,
2141 mvfr0_fpdivide),
2142 MRS_FIELD(MVFR0, FPTrap, false, MRS_LOWER, MRS_USERSPACE,
2143 mvfr0_fptrap),
2144 MRS_FIELD_HWCAP(MVFR0, FPDP, false, MRS_LOWER, MRS_USERSPACE,
2145 mvfr0_fpdp, mvfr0_fpdp_caps),
2146 MRS_FIELD(MVFR0, FPSP, false, MRS_LOWER, MRS_USERSPACE, mvfr0_fpsp),
2147 MRS_FIELD(MVFR0, SIMDReg, false, MRS_LOWER, MRS_USERSPACE,
2148 mvfr0_simdreg),
2149 MRS_FIELD_END,
2150 };
2151
2152 /* MVFR1 */
2153 static const struct mrs_field_value mvfr1_simdfmac[] = {
2154 MRS_FIELD_VALUE_NONE_IMPL(MVFR1, SIMDFMAC, NONE, IMPL),
2155 MRS_FIELD_VALUE_END,
2156 };
2157
2158 static const struct mrs_field_hwcap mvfr1_simdfmac_caps[] = {
2159 MRS_HWCAP(1, HWCAP32_VFPv4, MVFR1_SIMDFMAC_IMPL),
2160 MRS_HWCAP_END
2161 };
2162
2163 static const struct mrs_field_value mvfr1_fphp[] = {
2164 MRS_FIELD_VALUE(MVFR1_FPHP_NONE, ""),
2165 MRS_FIELD_VALUE(MVFR1_FPHP_CONV_SP, "FPHP SP Conv"),
2166 MRS_FIELD_VALUE(MVFR1_FPHP_CONV_DP, "FPHP DP Conv"),
2167 MRS_FIELD_VALUE(MVFR1_FPHP_ARITH, "FPHP Arith"),
2168 MRS_FIELD_VALUE_END,
2169 };
2170
2171 static const struct mrs_field_value mvfr1_simdhp[] = {
2172 MRS_FIELD_VALUE(MVFR1_SIMDHP_NONE, ""),
2173 MRS_FIELD_VALUE(MVFR1_SIMDHP_CONV_SP, "SIMDHP SP Conv"),
2174 MRS_FIELD_VALUE(MVFR1_SIMDHP_ARITH, "SIMDHP Arith"),
2175 MRS_FIELD_VALUE_END,
2176 };
2177
2178 static const struct mrs_field_value mvfr1_simdsp[] = {
2179 MRS_FIELD_VALUE_NONE_IMPL(MVFR1, SIMDSP, NONE, IMPL),
2180 MRS_FIELD_VALUE_END,
2181 };
2182
2183 static const struct mrs_field_value mvfr1_simdint[] = {
2184 MRS_FIELD_VALUE_NONE_IMPL(MVFR1, SIMDInt, NONE, IMPL),
2185 MRS_FIELD_VALUE_END,
2186 };
2187
2188 static const struct mrs_field_value mvfr1_simdls[] = {
2189 MRS_FIELD_VALUE_NONE_IMPL(MVFR1, SIMDLS, NONE, IMPL),
2190 MRS_FIELD_VALUE_END,
2191 };
2192
2193 static const struct mrs_field_hwcap mvfr1_simdls_caps[] = {
2194 MRS_HWCAP(1, HWCAP32_VFPv4, MVFR1_SIMDFMAC_IMPL),
2195 MRS_HWCAP_END
2196 };
2197
2198 static const struct mrs_field_value mvfr1_fpdnan[] = {
2199 MRS_FIELD_VALUE_NONE_IMPL(MVFR1, FPDNaN, NONE, IMPL),
2200 MRS_FIELD_VALUE_END,
2201 };
2202
2203 static const struct mrs_field_value mvfr1_fpftz[] = {
2204 MRS_FIELD_VALUE_NONE_IMPL(MVFR1, FPFtZ, NONE, IMPL),
2205 MRS_FIELD_VALUE_END,
2206 };
2207
2208 static const struct mrs_field mvfr1_fields[] = {
2209 MRS_FIELD_HWCAP(MVFR1, SIMDFMAC, false, MRS_LOWER, MRS_USERSPACE,
2210 mvfr1_simdfmac, mvfr1_simdfmac_caps),
2211 MRS_FIELD(MVFR1, FPHP, false, MRS_LOWER, MRS_USERSPACE, mvfr1_fphp),
2212 MRS_FIELD(MVFR1, SIMDHP, false, MRS_LOWER, MRS_USERSPACE, mvfr1_simdhp),
2213 MRS_FIELD(MVFR1, SIMDSP, false, MRS_LOWER, MRS_USERSPACE, mvfr1_simdsp),
2214 MRS_FIELD(MVFR1, SIMDInt, false, MRS_LOWER, MRS_USERSPACE,
2215 mvfr1_simdint),
2216 MRS_FIELD_HWCAP(MVFR1, SIMDLS, false, MRS_LOWER, MRS_USERSPACE,
2217 mvfr1_simdls, mvfr1_simdls_caps),
2218 MRS_FIELD(MVFR1, FPDNaN, false, MRS_LOWER, MRS_USERSPACE,
2219 mvfr1_fpdnan),
2220 MRS_FIELD(MVFR1, FPFtZ, false, MRS_LOWER, MRS_USERSPACE,
2221 mvfr1_fpftz),
2222 MRS_FIELD_END,
2223 };
2224 #endif /* COMPAT_FREEBSD32 */
2225
2226 struct mrs_user_reg {
2227 u_int iss;
2228 bool is64bit;
2229 size_t offset;
2230 const struct mrs_field *fields;
2231 };
2232
2233 #define USER_REG(name, field_name, _is64bit) \
2234 { \
2235 .iss = name##_ISS, \
2236 .offset = __offsetof(struct cpu_desc, field_name), \
2237 .fields = field_name##_fields, \
2238 .is64bit = _is64bit, \
2239 }
2240 static const struct mrs_user_reg user_regs[] = {
2241 USER_REG(ID_AA64AFR0_EL1, id_aa64afr0, true),
2242 USER_REG(ID_AA64AFR1_EL1, id_aa64afr1, true),
2243
2244 USER_REG(ID_AA64DFR0_EL1, id_aa64dfr0, true),
2245 USER_REG(ID_AA64DFR1_EL1, id_aa64dfr1, true),
2246
2247 USER_REG(ID_AA64ISAR0_EL1, id_aa64isar0, true),
2248 USER_REG(ID_AA64ISAR1_EL1, id_aa64isar1, true),
2249 USER_REG(ID_AA64ISAR2_EL1, id_aa64isar2, true),
2250
2251 USER_REG(ID_AA64MMFR0_EL1, id_aa64mmfr0, true),
2252 USER_REG(ID_AA64MMFR1_EL1, id_aa64mmfr1, true),
2253 USER_REG(ID_AA64MMFR2_EL1, id_aa64mmfr2, true),
2254 USER_REG(ID_AA64MMFR3_EL1, id_aa64mmfr3, true),
2255 USER_REG(ID_AA64MMFR4_EL1, id_aa64mmfr4, true),
2256
2257 USER_REG(ID_AA64PFR0_EL1, id_aa64pfr0, true),
2258 USER_REG(ID_AA64PFR1_EL1, id_aa64pfr1, true),
2259 USER_REG(ID_AA64PFR2_EL1, id_aa64pfr2, true),
2260
2261 USER_REG(ID_AA64ZFR0_EL1, id_aa64zfr0, true),
2262
2263 USER_REG(CTR_EL0, ctr, true),
2264
2265 #ifdef COMPAT_FREEBSD32
2266 USER_REG(ID_ISAR5_EL1, id_isar5, false),
2267
2268 USER_REG(MVFR0_EL1, mvfr0, false),
2269 USER_REG(MVFR1_EL1, mvfr1, false),
2270 #endif /* COMPAT_FREEBSD32 */
2271 };
2272
2273 #define CPU_DESC_FIELD(desc, idx) \
2274 *(uint64_t *)((char *)&(desc) + user_regs[(idx)].offset)
2275
2276 static bool
user_ctr_has_neoverse_n1_1542419(uint32_t midr,uint64_t ctr)2277 user_ctr_has_neoverse_n1_1542419(uint32_t midr, uint64_t ctr)
2278 {
2279 /*
2280 * Neoverse-N1 erratum 1542419
2281 * Present in r3p0 - r4p0
2282 * Fixed in r4p1
2283 */
2284 return (midr_check_var_part_range(midr, CPU_IMPL_ARM,
2285 CPU_PART_NEOVERSE_N1, 3, 0, 4, 0) && CTR_DIC_VAL(ctr) != 0);
2286 }
2287
2288 static cpu_feat_en
user_ctr_check(const struct cpu_feat * feat __unused,u_int midr)2289 user_ctr_check(const struct cpu_feat *feat __unused, u_int midr)
2290 {
2291 if (emulate_ctr)
2292 return (FEAT_DEFAULT_ENABLE);
2293
2294 if (user_ctr_has_neoverse_n1_1542419(midr, READ_SPECIALREG(ctr_el0)))
2295 return (FEAT_DEFAULT_ENABLE);
2296
2297 return (FEAT_ALWAYS_DISABLE);
2298 }
2299
2300 static bool
user_ctr_has_errata(const struct cpu_feat * feat __unused,u_int midr,u_int ** errata_list,u_int * errata_count)2301 user_ctr_has_errata(const struct cpu_feat *feat __unused, u_int midr,
2302 u_int **errata_list, u_int *errata_count)
2303 {
2304 if (user_ctr_has_neoverse_n1_1542419(midr, READ_SPECIALREG(ctr_el0))) {
2305 static u_int errata_id = 1542419;
2306
2307 *errata_list = &errata_id;
2308 *errata_count = 1;
2309 return (true);
2310 }
2311
2312 return (false);
2313 }
2314
2315 static bool
user_ctr_enable(const struct cpu_feat * feat __unused,cpu_feat_errata errata_status,u_int * errata_list,u_int errata_count)2316 user_ctr_enable(const struct cpu_feat *feat __unused,
2317 cpu_feat_errata errata_status, u_int *errata_list, u_int errata_count)
2318 {
2319 MPASS(emulate_ctr || errata_status != ERRATA_NONE);
2320
2321 /*
2322 * The Errata Management Firmware Interface may incorrectly mark
2323 * this as firmware mitigated. We should ignore that as there is
2324 * a kernel component to the mitigation.
2325 */
2326 if (errata_status != ERRATA_NONE && PCPU_GET(cpuid) == 0 &&
2327 cpu_feat_has_erratum(errata_list, errata_count, 1542419)) {
2328 /* Clear fields we will change */
2329 user_cpu_desc.ctr &= ~(CTR_DIC_MASK | CTR_ILINE_WIDTH);
2330
2331 /*
2332 * Set DIC to none so userspace will execute an 'ic ivau'
2333 * instruction that can be trapped by EL3.
2334 */
2335 user_cpu_desc.ctr |= CTR_DIC_NONE;
2336 /*
2337 * Set the i-cache line size to be page size to reduce the
2338 * number of times userspace needs to execute the 'ic ivau'
2339 * instruction. The ctr_el0.IminLine is log2 the number of
2340 * 4-byte words the instruction covers. As PAGE_SHIFT is log2
2341 * of the number of bytes in a page we need to subtract 2.
2342 */
2343 user_cpu_desc.ctr |= (PAGE_SHIFT - 2) << CTR_ILINE_SHIFT;
2344
2345 l_user_cpu_desc.ctr = user_cpu_desc.ctr;
2346 }
2347
2348 WRITE_SPECIALREG(sctlr_el1,
2349 READ_SPECIALREG(sctlr_el1) & ~SCTLR_UCT);
2350 isb();
2351
2352 return (true);
2353 }
2354
2355 CPU_FEAT(trap_ctr, "Trap CTR_EL0",
2356 user_ctr_check, user_ctr_has_errata, user_ctr_enable,
2357 CPU_FEAT_AFTER_DEV | CPU_FEAT_PER_CPU);
2358
2359 static bool
user_ctr_handler(uint64_t esr,struct trapframe * frame)2360 user_ctr_handler(uint64_t esr, struct trapframe *frame)
2361 {
2362 uint64_t value;
2363 int reg;
2364
2365 if (ESR_ELx_EXCEPTION(esr) != EXCP_MSR)
2366 return (false);
2367
2368 /* Only support reading from ctr_el0 */
2369 if ((esr & ISS_MSR_DIR) == 0)
2370 return (false);
2371
2372 /* Check if this is the ctr_el0 register */
2373 if ((esr & ISS_MSR_REG_MASK) != CTR_EL0_ISS)
2374 return (false);
2375
2376 if (SV_CURPROC_ABI() == SV_ABI_FREEBSD)
2377 value = user_cpu_desc.ctr;
2378 else
2379 value = l_user_cpu_desc.ctr;
2380 /*
2381 * We will handle this instruction, move to the next so we
2382 * don't trap here again.
2383 */
2384 frame->tf_elr += INSN_SIZE;
2385
2386 reg = ISS_MSR_Rt(esr);
2387 /* If reg is 31 then write to xzr, i.e. do nothing */
2388 if (reg == 31)
2389 return (true);
2390
2391 if (reg < nitems(frame->tf_x))
2392 frame->tf_x[reg] = value;
2393 else if (reg == 30)
2394 frame->tf_lr = value;
2395
2396 return (true);
2397 }
2398
2399 static bool
user_idreg_handler(uint64_t esr,struct trapframe * frame)2400 user_idreg_handler(uint64_t esr, struct trapframe *frame)
2401 {
2402 uint64_t value;
2403 int reg;
2404
2405 if (ESR_ELx_EXCEPTION(esr) != EXCP_MSR)
2406 return (false);
2407
2408 /* Only support reading from ID registers */
2409 if ((esr & ISS_MSR_DIR) == 0)
2410 return (false);
2411
2412 /*
2413 * This only handles the ID register space and a few registers that
2414 * are safe to pass through to userspace.
2415 *
2416 * These registers are all in the space op0 == 3, op1 == 0,
2417 * CRn == 0. We support the following CRm:
2418 * - CRm == 0: midr_el1, mpidr_el1, and revidr_el1.
2419 * - CRm in {4-7}: sanitized ID registers.
2420 *
2421 * Registers in the ID register space (CRm in {4-7}) are all
2422 * read-only and have either defined fields, or are read as
2423 * zero (RAZ). For these we return 0 for any unknown register.
2424 */
2425 if (ISS_MSR_OP0(esr) != 3 || ISS_MSR_OP1(esr) != 0 ||
2426 ISS_MSR_CRn(esr) != 0)
2427 return (false);
2428
2429 value = 0;
2430 if (ISS_MSR_CRm(esr) >= 4 && ISS_MSR_CRm(esr) <= 7) {
2431 for (int i = 0; i < nitems(user_regs); i++) {
2432 if (user_regs[i].iss == (esr & ISS_MSR_REG_MASK)) {
2433 if (SV_CURPROC_ABI() == SV_ABI_FREEBSD)
2434 value = CPU_DESC_FIELD(user_cpu_desc, i);
2435 else
2436 value = CPU_DESC_FIELD(l_user_cpu_desc, i);
2437 break;
2438 }
2439 }
2440 } else if (ISS_MSR_CRm(esr) == 0) {
2441 switch (ISS_MSR_OP2(esr)) {
2442 case 0:
2443 value = READ_SPECIALREG(midr_el1);
2444 break;
2445 case 5:
2446 value = READ_SPECIALREG(mpidr_el1);
2447 break;
2448 case 6:
2449 value = READ_SPECIALREG(revidr_el1);
2450 break;
2451 default:
2452 return (false);
2453 }
2454 } else {
2455 return (false);
2456 }
2457
2458 /*
2459 * We will handle this instruction, move to the next so we
2460 * don't trap here again.
2461 */
2462 frame->tf_elr += INSN_SIZE;
2463
2464 reg = ISS_MSR_Rt(esr);
2465 /* If reg is 31 then write to xzr, i.e. do nothing */
2466 if (reg == 31)
2467 return (1);
2468
2469 if (reg < nitems(frame->tf_x))
2470 frame->tf_x[reg] = value;
2471 else if (reg == 30)
2472 frame->tf_lr = value;
2473
2474 return (true);
2475 }
2476
2477 /*
2478 * Compares two field values that may be signed or unsigned.
2479 * Returns:
2480 * < 0 when a is less than b
2481 * = 0 when a equals b
2482 * > 0 when a is greater than b
2483 */
2484 static int
mrs_field_cmp(uint64_t a,uint64_t b,u_int shift,int width,bool sign)2485 mrs_field_cmp(uint64_t a, uint64_t b, u_int shift, int width, bool sign)
2486 {
2487 uint64_t mask;
2488
2489 KASSERT(width > 0 && width < 64, ("%s: Invalid width %d", __func__,
2490 width));
2491
2492 mask = (1ul << width) - 1;
2493 /* Move the field to the lower bits */
2494 a = (a >> shift) & mask;
2495 b = (b >> shift) & mask;
2496
2497 if (sign) {
2498 /*
2499 * The field is signed. Toggle the upper bit so the comparison
2500 * works on unsigned values as this makes positive numbers,
2501 * i.e. those with a 0 bit, larger than negative numbers,
2502 * i.e. those with a 1 bit, in an unsigned comparison.
2503 */
2504 a ^= 1ul << (width - 1);
2505 b ^= 1ul << (width - 1);
2506 }
2507
2508 return (a - b);
2509 }
2510
2511 bool
get_kernel_reg_iss(u_int iss,uint64_t * val)2512 get_kernel_reg_iss(u_int iss, uint64_t *val)
2513 {
2514 int i;
2515
2516 for (i = 0; i < nitems(user_regs); i++) {
2517 if (user_regs[i].iss == iss) {
2518 *val = CPU_DESC_FIELD(kern_cpu_desc, i);
2519 return (true);
2520 }
2521 }
2522
2523 return (false);
2524 }
2525
2526 /*
2527 * Fetch the specified register's value, ensuring that individual field values
2528 * do not exceed those in the mask.
2529 */
2530 bool
get_kernel_reg_iss_masked(u_int iss,uint64_t * valp,uint64_t mask)2531 get_kernel_reg_iss_masked(u_int iss, uint64_t *valp, uint64_t mask)
2532 {
2533 const struct mrs_field *fields;
2534 uint64_t val;
2535
2536 for (int i = 0; i < nitems(user_regs); i++) {
2537 if (user_regs[i].iss == iss) {
2538 val = CPU_DESC_FIELD(kern_cpu_desc, i);
2539 fields = user_regs[i].fields;
2540 for (int j = 0; fields[j].type != 0; j++) {
2541 mask = update_special_reg_field(mask,
2542 fields[j].type, val, fields[j].width,
2543 fields[j].shift, fields[j].sign);
2544 }
2545 *valp = mask;
2546 return (true);
2547 }
2548 }
2549
2550 return (false);
2551 }
2552
2553 bool
get_user_reg_iss(u_int iss,uint64_t * val,bool fbsd)2554 get_user_reg_iss(u_int iss, uint64_t *val, bool fbsd)
2555 {
2556 int i;
2557
2558 for (i = 0; i < nitems(user_regs); i++) {
2559 if (user_regs[i].iss == iss) {
2560 if (fbsd)
2561 *val = CPU_DESC_FIELD(user_cpu_desc, i);
2562 else
2563 *val = CPU_DESC_FIELD(l_user_cpu_desc, i);
2564 return (true);
2565 }
2566 }
2567
2568 return (false);
2569 }
2570
2571 static uint64_t
update_special_reg_field(uint64_t user_reg,u_int type,uint64_t value,u_int width,u_int shift,bool sign)2572 update_special_reg_field(uint64_t user_reg, u_int type, uint64_t value,
2573 u_int width, u_int shift, bool sign)
2574 {
2575 uint64_t cur, mask, new_val;
2576
2577 mask = ((1ul << width) - 1) << shift;
2578 cur = user_reg & mask;
2579 new_val = value & mask;
2580
2581 switch (type & MRS_TYPE_MASK) {
2582 case MRS_EXACT_IF_DIFFERENT:
2583 if (mrs_field_cmp(new_val, cur, shift, width, sign) == 0)
2584 break;
2585 /* FALLTHROUGH */
2586 case MRS_EXACT:
2587 cur = (uint64_t)MRS_SAFE_VAL(type) << shift;
2588 break;
2589 case MRS_LOWER:
2590 if (mrs_field_cmp(new_val, cur, shift, width, sign) < 0)
2591 cur = new_val;
2592 break;
2593 case MRS_HIGHER_OR_ZERO:
2594 if (cur == 0 || new_val == 0) {
2595 cur = 0;
2596 break;
2597 }
2598 /* FALLTHROUGH */
2599 case MRS_HIGHER:
2600 if (mrs_field_cmp(new_val, cur, shift, width, sign) > 0)
2601 cur = new_val;
2602 break;
2603 default:
2604 panic("Invalid field type: %d", type);
2605 }
2606
2607 user_reg &= ~mask;
2608 user_reg |= cur;
2609
2610 return (user_reg);
2611 }
2612
2613 static void
clear_set_special_reg_idx(int idx,uint64_t clear,uint64_t set)2614 clear_set_special_reg_idx(int idx, uint64_t clear, uint64_t set)
2615 {
2616 const struct mrs_field *fields;
2617 uint64_t k_old, k_new;
2618 uint64_t f_old, f_new;
2619 uint64_t l_old, l_new;
2620
2621 MPASS(idx < nitems(user_regs));
2622
2623 k_old = CPU_DESC_FIELD(kern_cpu_desc, idx);
2624 k_new = (k_old & ~clear) | set;
2625
2626 f_old = CPU_DESC_FIELD(user_cpu_desc, idx);
2627 f_new = (f_old & ~clear) | set;
2628
2629 l_old = CPU_DESC_FIELD(l_user_cpu_desc, idx);
2630 l_new = (l_old & ~clear) | set;
2631
2632 fields = user_regs[idx].fields;
2633 for (int j = 0; fields[j].type != 0; j++) {
2634 u_int type;
2635
2636 /* Update the FreeBSD userspace ID register view */
2637 type = ((fields[j].type & MRS_FREEBSD) != 0) ?
2638 fields[j].type :
2639 (MRS_EXACT | (fields[j].type & MRS_SAFE_MASK));
2640 f_new = update_special_reg_field(f_new,
2641 type, f_old, fields[j].width, fields[j].shift,
2642 fields[j].sign);
2643
2644 /* Update the Linux userspace ID register view */
2645 type = ((fields[j].type & MRS_LINUX) != 0) ?
2646 fields[j].type :
2647 (MRS_EXACT | (fields[j].type & MRS_SAFE_MASK));
2648 l_new = update_special_reg_field(l_new,
2649 type, l_old, fields[j].width, fields[j].shift,
2650 fields[j].sign);
2651
2652 /* Update the kernel ID register view */
2653 k_new = update_special_reg_field(k_new,
2654 fields[j].type, k_old, fields[j].width,
2655 fields[j].shift, fields[j].sign);
2656 }
2657
2658 CPU_DESC_FIELD(kern_cpu_desc, idx) = k_new;
2659 CPU_DESC_FIELD(user_cpu_desc, idx) = f_new;
2660 CPU_DESC_FIELD(l_user_cpu_desc, idx) = l_new;
2661 }
2662
2663 void
update_special_regs(u_int cpu)2664 update_special_regs(u_int cpu)
2665 {
2666 struct cpu_desc *desc;
2667 uint64_t value;
2668 int i;
2669
2670 if (cpu == 0) {
2671 /* Create a user visible cpu description with safe values */
2672 memset(&user_cpu_desc, 0, sizeof(user_cpu_desc));
2673 /* Safe values for these registers */
2674 user_cpu_desc.id_aa64pfr0 = ID_AA64PFR0_AdvSIMD_NONE |
2675 ID_AA64PFR0_FP_NONE | ID_AA64PFR0_EL1_64 |
2676 ID_AA64PFR0_EL0_64;
2677 user_cpu_desc.id_aa64dfr0 = ID_AA64DFR0_DebugVer_8;
2678 /* Create the Linux user visible cpu description */
2679 memcpy(&l_user_cpu_desc, &user_cpu_desc, sizeof(user_cpu_desc));
2680 }
2681
2682 desc = get_cpu_desc(cpu);
2683 for (i = 0; i < nitems(user_regs); i++) {
2684 value = CPU_DESC_FIELD(*desc, i);
2685 if (cpu == 0) {
2686 CPU_DESC_FIELD(kern_cpu_desc, i) = value;
2687 CPU_DESC_FIELD(user_cpu_desc, i) = value;
2688 CPU_DESC_FIELD(l_user_cpu_desc, i) = value;
2689 }
2690
2691 clear_set_special_reg_idx(i, UINT64_MAX, value);
2692 }
2693 }
2694
2695 /*
2696 * Updates a special register in all views. This creates a copy of the
2697 * register then clears it and sets new bits. It will then compare this
2698 * with the old version as if it was the ID register for a new CPU.
2699 *
2700 * It is intended to let code that disables features, e.g. due to errata,
2701 * to clear the user visible field.
2702 *
2703 * This needs to be called before the HWCAPs are set. If called from a CPU
2704 * feature handler this safe to call from CPU_FEAT_EARLY_BOOT. It also needs
2705 * to be before link_elf_late_ireloc is called. As this is called after the
2706 * HWCAPs are set the check for these is enough.
2707 */
2708 void
update_special_reg_iss(u_int iss,uint64_t clear,uint64_t set)2709 update_special_reg_iss(u_int iss, uint64_t clear, uint64_t set)
2710 {
2711 MPASS(hwcaps_set == false);
2712 /* There is no locking here, so we only support changing this on CPU0 */
2713 /* TODO: Add said locking */
2714 MPASS(PCPU_GET(cpuid) == 0);
2715
2716 for (int i = 0; i < nitems(user_regs); i++) {
2717 if (user_regs[i].iss != iss)
2718 continue;
2719
2720 clear_set_special_reg_idx(i, clear, set);
2721 return;
2722 }
2723 }
2724
2725 void
cpu_desc_init(void)2726 cpu_desc_init(void)
2727 {
2728 if (mp_ncpus == 1)
2729 return;
2730
2731 /*
2732 * Allocate memory for the non-boot CPUs to store their registers.
2733 * As this is indexed by CPU ID we need to allocate space for CPUs
2734 * 1 to mp_maxid. Because of this mp_maxid is already the correct
2735 * number of elements.
2736 */
2737 cpu_desc = mallocarray(mp_maxid, sizeof(*cpu_desc), M_IDENTCPU,
2738 M_ZERO | M_WAITOK);
2739 }
2740
2741 /* HWCAP */
2742 bool __read_frequently lse_supported = false;
2743
2744 bool __read_frequently icache_aliasing = false;
2745 bool __read_frequently icache_vmid = false;
2746
2747 int64_t dcache_line_size; /* The minimum D cache line size */
2748 int64_t icache_line_size; /* The minimum I cache line size */
2749 int64_t idcache_line_size; /* The minimum cache line size */
2750
2751 /*
2752 * Find the values to export to userspace as AT_HWCAP and AT_HWCAP2.
2753 */
2754 static void
parse_cpu_features(bool is64bit,struct cpu_desc * cpu_desc,u_long * hwcap,u_long * hwcap2)2755 parse_cpu_features(bool is64bit, struct cpu_desc *cpu_desc, u_long *hwcap,
2756 u_long *hwcap2)
2757 {
2758 const struct mrs_field_hwcap *hwcaps;
2759 const struct mrs_field *fields;
2760 uint64_t min, reg;
2761 u_long *cur_hwcap;
2762 int i, j, k;
2763
2764 for (i = 0; i < nitems(user_regs); i++) {
2765 if (user_regs[i].is64bit != is64bit)
2766 continue;
2767
2768 reg = CPU_DESC_FIELD(*cpu_desc, i);
2769 fields = user_regs[i].fields;
2770 for (j = 0; fields[j].type != 0; j++) {
2771 hwcaps = fields[j].hwcaps;
2772 if (hwcaps == NULL)
2773 continue;
2774
2775 for (k = 0; hwcaps[k].hwcap_id != 0; k++) {
2776 KASSERT(hwcaps[k].hwcap_id == 1 ||
2777 hwcaps[k].hwcap_id == 2,
2778 ("%s: Invalid HWCAP ID %d", __func__,
2779 hwcaps[k].hwcap_id));
2780
2781 cur_hwcap = hwcaps[k].hwcap_id == 1 ?
2782 hwcap : hwcap2;
2783 min = hwcaps[k].min;
2784
2785 /*
2786 * If the field is greater than the minimum
2787 * value we can set the hwcap;
2788 */
2789 if (mrs_field_cmp(reg, min, fields[j].shift,
2790 4, fields[j].sign) >= 0) {
2791 *cur_hwcap |= hwcaps[k].hwcap_val;
2792 }
2793 }
2794 }
2795 }
2796 }
2797
2798 static void
identify_cpu_sysinit(void * dummy __unused)2799 identify_cpu_sysinit(void *dummy __unused)
2800 {
2801 struct cpu_desc *desc, *prev_desc;
2802 int cpu;
2803 bool dic, idc;
2804
2805 dic = (allow_dic != 0);
2806 idc = (allow_idc != 0);
2807
2808 prev_desc = NULL;
2809 CPU_FOREACH(cpu) {
2810 desc = get_cpu_desc(cpu);
2811 if (cpu != 0) {
2812 check_cpu_regs(cpu, desc, prev_desc);
2813 update_special_regs(cpu);
2814 }
2815
2816 if (CTR_DIC_VAL(desc->ctr) == 0)
2817 dic = false;
2818 if (CTR_IDC_VAL(desc->ctr) == 0)
2819 idc = false;
2820 prev_desc = desc;
2821 }
2822
2823 #ifdef INVARIANTS
2824 /* Check we dont update the special registers after this point */
2825 hwcaps_set = true;
2826 #endif
2827
2828 /* Find the values to export to userspace as AT_HWCAP and AT_HWCAP2 */
2829 parse_cpu_features(true, &user_cpu_desc, &elf_hwcap, &elf_hwcap2);
2830 parse_cpu_features(true, &l_user_cpu_desc, &linux_elf_hwcap,
2831 &linux_elf_hwcap2);
2832 #ifdef COMPAT_FREEBSD32
2833 parse_cpu_features(false, &user_cpu_desc, &elf32_hwcap, &elf32_hwcap2);
2834 #endif
2835
2836 /* We export the CPUID registers */
2837 elf_hwcap |= HWCAP_CPUID;
2838 linux_elf_hwcap |= HWCAP_CPUID;
2839
2840 #ifdef COMPAT_FREEBSD32
2841 /* Set the default caps and any that need to check multiple fields */
2842 elf32_hwcap |= parse_cpu_features_hwcap32();
2843 #endif
2844
2845 if (dic && idc) {
2846 arm64_icache_sync_range = &arm64_dic_idc_icache_sync_range;
2847 if (bootverbose)
2848 printf("Enabling DIC & IDC ICache sync\n");
2849 } else if (idc) {
2850 arm64_icache_sync_range = &arm64_idc_aliasing_icache_sync_range;
2851 if (bootverbose)
2852 printf("Enabling IDC ICache sync\n");
2853 }
2854
2855 if ((elf_hwcap & HWCAP_ATOMICS) != 0) {
2856 lse_supported = true;
2857 if (bootverbose)
2858 printf("Enabling LSE atomics in the kernel\n");
2859 }
2860 #ifdef LSE_ATOMICS
2861 if (!lse_supported)
2862 panic("CPU does not support LSE atomic instructions");
2863 #endif
2864
2865 install_sys_handler(user_ctr_handler);
2866 install_sys_handler(user_idreg_handler);
2867 }
2868 /*
2869 * This needs to be after the APs have stareted as they may have errata that
2870 * means we need to mask out ID registers & that could affect hwcaps, etc.
2871 */
2872 SYSINIT(identify_cpu, SI_SUB_CONFIGURE, SI_ORDER_ANY, identify_cpu_sysinit,
2873 NULL);
2874
2875 static void
cpu_features_sysinit(void * dummy __unused)2876 cpu_features_sysinit(void *dummy __unused)
2877 {
2878 struct sbuf sb;
2879 struct cpu_desc *desc, *prev_desc;
2880 u_int cpu;
2881
2882 prev_desc = NULL;
2883 CPU_FOREACH(cpu) {
2884 desc = get_cpu_desc(cpu);
2885 print_cpu_features(cpu, desc, prev_desc);
2886 prev_desc = desc;
2887 }
2888
2889 /* Fill in cpu_model for the hw.model sysctl */
2890 sbuf_new(&sb, cpu_model, sizeof(cpu_model), SBUF_FIXEDLEN);
2891 print_cpu_midr(&sb, 0);
2892
2893 sbuf_finish(&sb);
2894 sbuf_delete(&sb);
2895
2896 free(cpu_desc, M_IDENTCPU);
2897 }
2898 /* Log features before APs are released and start printing to the dmesg. */
2899 SYSINIT(cpu_features, SI_SUB_SMP - 1, SI_ORDER_ANY, cpu_features_sysinit, NULL);
2900
2901 static void
tcr_set_e0pd1(void * arg __unused)2902 tcr_set_e0pd1(void *arg __unused)
2903 {
2904 uint64_t tcr;
2905
2906 tcr = READ_SPECIALREG(tcr_el1);
2907 tcr |= TCR_E0PD1;
2908 WRITE_SPECIALREG(tcr_el1, tcr);
2909 isb();
2910 }
2911
2912 /* Enable support for more recent architecture features */
2913 static void
cpu_feat_support(void * arg __unused)2914 cpu_feat_support(void *arg __unused)
2915 {
2916 /*
2917 * If FEAT_E0PD is supported use it to cause faults without a page
2918 * table walk if userspace tries to access kernel memory.
2919 */
2920 if (ID_AA64MMFR2_E0PD_VAL(kern_cpu_desc.id_aa64mmfr2) !=
2921 ID_AA64MMFR2_E0PD_NONE)
2922 smp_rendezvous(NULL, tcr_set_e0pd1, NULL, NULL);
2923 }
2924 SYSINIT(cpu_feat_support, SI_SUB_SMP, SI_ORDER_ANY, cpu_feat_support, NULL);
2925
2926 #ifdef COMPAT_FREEBSD32
2927 static u_long
parse_cpu_features_hwcap32(void)2928 parse_cpu_features_hwcap32(void)
2929 {
2930 u_long hwcap = HWCAP32_DEFAULT;
2931
2932 if ((MVFR1_SIMDLS_VAL(user_cpu_desc.mvfr1) >=
2933 MVFR1_SIMDLS_IMPL) &&
2934 (MVFR1_SIMDInt_VAL(user_cpu_desc.mvfr1) >=
2935 MVFR1_SIMDInt_IMPL) &&
2936 (MVFR1_SIMDSP_VAL(user_cpu_desc.mvfr1) >=
2937 MVFR1_SIMDSP_IMPL))
2938 hwcap |= HWCAP32_NEON;
2939
2940 return (hwcap);
2941 }
2942 #endif /* COMPAT_FREEBSD32 */
2943
2944 static void
print_register(struct sbuf * sb,const char * reg_name,uint64_t reg,void (* print_fields)(struct sbuf *,uint64_t,const void *),const void * arg)2945 print_register(struct sbuf *sb, const char *reg_name, uint64_t reg,
2946 void (*print_fields)(struct sbuf *, uint64_t, const void *),
2947 const void *arg)
2948 {
2949
2950 sbuf_printf(sb, "%29s = <", reg_name);
2951
2952 print_fields(sb, reg, arg);
2953
2954 sbuf_finish(sb);
2955 printf("%s>\n", sbuf_data(sb));
2956 sbuf_clear(sb);
2957 }
2958
2959 static void
print_id_fields(struct sbuf * sb,uint64_t reg,const void * arg)2960 print_id_fields(struct sbuf *sb, uint64_t reg, const void *arg)
2961 {
2962 const struct mrs_field *fields = arg;
2963 const struct mrs_field_value *fv;
2964 int field, i, j, printed;
2965
2966 #define SEP_STR ((printed++) == 0) ? "" : ","
2967 printed = 0;
2968 for (i = 0; fields[i].type != 0; i++) {
2969 fv = fields[i].values;
2970
2971 if (fv == NULL)
2972 goto next;
2973
2974 field = (reg & fields[i].mask) >> fields[i].shift;
2975 for (j = 0; fv[j].desc != NULL; j++) {
2976 if ((fv[j].value >> fields[i].shift) != field)
2977 continue;
2978
2979 if (fv[j].desc[0] != '\0')
2980 sbuf_printf(sb, "%s%s", SEP_STR, fv[j].desc);
2981 break;
2982 }
2983 if (fv[j].desc == NULL)
2984 sbuf_printf(sb, "%sUnknown %s(%x)", SEP_STR,
2985 fields[i].name, field);
2986
2987 next:
2988 reg &= ~(((1ul << fields[i].width) - 1) << fields[i].shift);
2989 }
2990
2991 if (reg != 0)
2992 sbuf_printf(sb, "%s%#lx", SEP_STR, reg);
2993 #undef SEP_STR
2994 }
2995
2996 static void
print_id_register(struct sbuf * sb,const char * reg_name,uint64_t reg,const struct mrs_field * fields)2997 print_id_register(struct sbuf *sb, const char *reg_name, uint64_t reg,
2998 const struct mrs_field *fields)
2999 {
3000
3001 print_register(sb, reg_name, reg, print_id_fields, fields);
3002 }
3003
3004 static void
print_cpu_midr(struct sbuf * sb,u_int cpu)3005 print_cpu_midr(struct sbuf *sb, u_int cpu)
3006 {
3007 const struct cpu_parts *cpu_partsp;
3008 const char *cpu_impl_name;
3009 const char *cpu_part_name;
3010 u_int midr;
3011 u_int impl_id;
3012 u_int part_id;
3013
3014 midr = pcpu_find(cpu)->pc_midr;
3015
3016 cpu_impl_name = NULL;
3017 cpu_partsp = NULL;
3018 impl_id = CPU_IMPL(midr);
3019 for (int i = 0; cpu_implementers[i].impl_name != NULL; i++) {
3020 if (impl_id == cpu_implementers[i].impl_id) {
3021 cpu_impl_name = cpu_implementers[i].impl_name;
3022 cpu_partsp = cpu_implementers[i].cpu_parts;
3023 break;
3024 }
3025 }
3026 /* Unknown implementer, so unknown part */
3027 if (cpu_impl_name == NULL) {
3028 sbuf_printf(sb, "Unknown Implementer (midr: %08x)", midr);
3029 return;
3030 }
3031
3032 KASSERT(cpu_partsp != NULL, ("%s: No parts table for implementer %s",
3033 __func__, cpu_impl_name));
3034
3035 cpu_part_name = NULL;
3036 part_id = CPU_PART(midr);
3037 for (int i = 0; cpu_partsp[i].part_name != NULL; i++) {
3038 if (part_id == cpu_partsp[i].part_id) {
3039 cpu_part_name = cpu_partsp[i].part_name;
3040 break;
3041 }
3042 }
3043 /* Known Implementer, Unknown part */
3044 if (cpu_part_name == NULL) {
3045 sbuf_printf(sb, "%s Unknown CPU r%dp%d (midr: %08x)",
3046 cpu_impl_name, CPU_VAR(midr), CPU_REV(midr), midr);
3047 return;
3048 }
3049
3050 sbuf_printf(sb, "%s %s r%dp%d", cpu_impl_name,
3051 cpu_part_name, CPU_VAR(midr), CPU_REV(midr));
3052 }
3053
3054 static void
print_cpu_cache(struct cpu_desc * desc,struct sbuf * sb,uint64_t ccs,bool icache,bool unified)3055 print_cpu_cache(struct cpu_desc *desc, struct sbuf *sb, uint64_t ccs,
3056 bool icache, bool unified)
3057 {
3058 size_t cache_size;
3059 size_t line_size;
3060
3061 /* LineSize is Log2(S) - 4. */
3062 line_size = 1 << ((ccs & CCSIDR_LineSize_MASK) + 4);
3063 /*
3064 * Calculate cache size (sets * ways * line size). There are different
3065 * formats depending on the FEAT_CCIDX bit in ID_AA64MMFR2 feature
3066 * register.
3067 */
3068 if ((desc->id_aa64mmfr2 & ID_AA64MMFR2_CCIDX_64))
3069 cache_size = (CCSIDR_NSETS_64(ccs) + 1) *
3070 (CCSIDR_ASSOC_64(ccs) + 1);
3071 else
3072 cache_size = (CCSIDR_NSETS(ccs) + 1) * (CCSIDR_ASSOC(ccs) + 1);
3073
3074 cache_size *= line_size;
3075 sbuf_printf(sb, "%zuKB (%s)", cache_size / 1024,
3076 icache ? "instruction" : unified ? "unified" : "data");
3077 }
3078
3079 static void
print_cpu_caches(struct sbuf * sb,struct cpu_desc * desc)3080 print_cpu_caches(struct sbuf *sb, struct cpu_desc *desc)
3081 {
3082 /* Print out each cache combination */
3083 uint64_t clidr;
3084 int i = 1;
3085 clidr = desc->clidr;
3086
3087 for (i = 0; (clidr & CLIDR_CTYPE_MASK) != 0; i++, clidr >>= 3) {
3088 int j = 0;
3089 int ctype_m = (clidr & CLIDR_CTYPE_MASK);
3090
3091 sbuf_printf(sb, " L%d cache: ", i + 1);
3092 if ((clidr & CLIDR_CTYPE_IO)) {
3093 print_cpu_cache(desc, sb, desc->ccsidr[i][j++], true,
3094 false);
3095 /* If there's more, add to the line. */
3096 if ((ctype_m & ~CLIDR_CTYPE_IO) != 0)
3097 sbuf_printf(sb, ", ");
3098 }
3099 if ((ctype_m & ~CLIDR_CTYPE_IO) != 0) {
3100 print_cpu_cache(desc, sb, desc->ccsidr[i][j], false,
3101 (clidr & CLIDR_CTYPE_UNIFIED));
3102 }
3103 sbuf_printf(sb, "\n");
3104
3105 }
3106 sbuf_finish(sb);
3107 printf("%s", sbuf_data(sb));
3108 }
3109
3110 static void
print_cpu_features(u_int cpu,struct cpu_desc * desc,struct cpu_desc * prev_desc)3111 print_cpu_features(u_int cpu, struct cpu_desc *desc,
3112 struct cpu_desc *prev_desc)
3113 {
3114 struct sbuf *sb;
3115
3116 sb = sbuf_new_auto();
3117 sbuf_printf(sb, "CPU%3u: ", cpu);
3118 print_cpu_midr(sb, cpu);
3119
3120 sbuf_cat(sb, " affinity:");
3121 switch(cpu_aff_levels) {
3122 default:
3123 case 4:
3124 sbuf_printf(sb, " %2d", CPU_AFF3(desc->mpidr));
3125 /* FALLTHROUGH */
3126 case 3:
3127 sbuf_printf(sb, " %2d", CPU_AFF2(desc->mpidr));
3128 /* FALLTHROUGH */
3129 case 2:
3130 sbuf_printf(sb, " %2d", CPU_AFF1(desc->mpidr));
3131 /* FALLTHROUGH */
3132 case 1:
3133 case 0: /* On UP this will be zero */
3134 sbuf_printf(sb, " %2d", CPU_AFF0(desc->mpidr));
3135 break;
3136 }
3137 sbuf_finish(sb);
3138 printf("%s\n", sbuf_data(sb));
3139 sbuf_clear(sb);
3140
3141 /*
3142 * There is a hardware errata where, if one CPU is performing a TLB
3143 * invalidation while another is performing a store-exclusive the
3144 * store-exclusive may return the wrong status. A workaround seems
3145 * to be to use an IPI to invalidate on each CPU, however given the
3146 * limited number of affected units (pass 1.1 is the evaluation
3147 * hardware revision), and the lack of information from Cavium
3148 * this has not been implemented.
3149 *
3150 * At the time of writing this the only information is from:
3151 * https://lkml.org/lkml/2016/8/4/722
3152 */
3153 /*
3154 * XXX: CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1 on its own also
3155 * triggers on pass 2.0+.
3156 */
3157 if (cpu == 0 && CPU_VAR(PCPU_GET(midr)) == 0 &&
3158 CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1)
3159 printf("WARNING: ThunderX Pass 1.1 detected.\nThis has known "
3160 "hardware bugs that may cause the incorrect operation of "
3161 "atomic operations.\n");
3162
3163 #define SHOULD_PRINT_REG(_reg) \
3164 (prev_desc == NULL || desc->_reg != prev_desc->_reg)
3165
3166 /* Cache Type Register */
3167 if (SHOULD_PRINT_REG(ctr))
3168 print_id_register(sb, "Cache Type", desc->ctr, ctr_fields);
3169
3170 /* AArch64 Instruction Set Attribute Register 0 */
3171 if (SHOULD_PRINT_REG(id_aa64isar0))
3172 print_id_register(sb, "Instruction Set Attributes 0",
3173 desc->id_aa64isar0, id_aa64isar0_fields);
3174
3175 /* AArch64 Instruction Set Attribute Register 1 */
3176 if (SHOULD_PRINT_REG(id_aa64isar1))
3177 print_id_register(sb, "Instruction Set Attributes 1",
3178 desc->id_aa64isar1, id_aa64isar1_fields);
3179
3180 /* AArch64 Instruction Set Attribute Register 2 */
3181 if (SHOULD_PRINT_REG(id_aa64isar2))
3182 print_id_register(sb, "Instruction Set Attributes 2",
3183 desc->id_aa64isar2, id_aa64isar2_fields);
3184
3185 /* AArch64 Processor Feature Register 0 */
3186 if (SHOULD_PRINT_REG(id_aa64pfr0))
3187 print_id_register(sb, "Processor Features 0",
3188 desc->id_aa64pfr0, id_aa64pfr0_fields);
3189
3190 /* AArch64 Processor Feature Register 1 */
3191 if (SHOULD_PRINT_REG(id_aa64pfr1))
3192 print_id_register(sb, "Processor Features 1",
3193 desc->id_aa64pfr1, id_aa64pfr1_fields);
3194
3195 /* AArch64 Processor Feature Register 2 */
3196 if (SHOULD_PRINT_REG(id_aa64pfr2))
3197 print_id_register(sb, "Processor Features 2",
3198 desc->id_aa64pfr2, id_aa64pfr2_fields);
3199
3200 /* AArch64 Memory Model Feature Register 0 */
3201 if (SHOULD_PRINT_REG(id_aa64mmfr0))
3202 print_id_register(sb, "Memory Model Features 0",
3203 desc->id_aa64mmfr0, id_aa64mmfr0_fields);
3204
3205 /* AArch64 Memory Model Feature Register 1 */
3206 if (SHOULD_PRINT_REG(id_aa64mmfr1))
3207 print_id_register(sb, "Memory Model Features 1",
3208 desc->id_aa64mmfr1, id_aa64mmfr1_fields);
3209
3210 /* AArch64 Memory Model Feature Register 2 */
3211 if (SHOULD_PRINT_REG(id_aa64mmfr2))
3212 print_id_register(sb, "Memory Model Features 2",
3213 desc->id_aa64mmfr2, id_aa64mmfr2_fields);
3214
3215 /* AArch64 Memory Model Feature Register 3 */
3216 if (SHOULD_PRINT_REG(id_aa64mmfr3))
3217 print_id_register(sb, "Memory Model Features 3",
3218 desc->id_aa64mmfr3, id_aa64mmfr3_fields);
3219
3220 /* AArch64 Memory Model Feature Register 4 */
3221 if (SHOULD_PRINT_REG(id_aa64mmfr4))
3222 print_id_register(sb, "Memory Model Features 4",
3223 desc->id_aa64mmfr4, id_aa64mmfr4_fields);
3224
3225 /* AArch64 Debug Feature Register 0 */
3226 if (SHOULD_PRINT_REG(id_aa64dfr0))
3227 print_id_register(sb, "Debug Features 0",
3228 desc->id_aa64dfr0, id_aa64dfr0_fields);
3229
3230 /* AArch64 Memory Model Feature Register 1 */
3231 if (SHOULD_PRINT_REG(id_aa64dfr1))
3232 print_id_register(sb, "Debug Features 1",
3233 desc->id_aa64dfr1, id_aa64dfr1_fields);
3234
3235 /* AArch64 Auxiliary Feature Register 0 */
3236 if (SHOULD_PRINT_REG(id_aa64afr0))
3237 print_id_register(sb, "Auxiliary Features 0",
3238 desc->id_aa64afr0, id_aa64afr0_fields);
3239
3240 /* AArch64 Auxiliary Feature Register 1 */
3241 if (SHOULD_PRINT_REG(id_aa64afr1))
3242 print_id_register(sb, "Auxiliary Features 1",
3243 desc->id_aa64afr1, id_aa64afr1_fields);
3244
3245 /* AArch64 SVE Feature Register 0 */
3246 if (desc->have_sve) {
3247 if (SHOULD_PRINT_REG(id_aa64zfr0) ||
3248 !prev_desc->have_sve) {
3249 print_id_register(sb, "SVE Features 0",
3250 desc->id_aa64zfr0, id_aa64zfr0_fields);
3251 }
3252 }
3253
3254 #ifdef COMPAT_FREEBSD32
3255 /* AArch32 Instruction Set Attribute Register 5 */
3256 if (SHOULD_PRINT_REG(id_isar5))
3257 print_id_register(sb, "AArch32 Instruction Set Attributes 5",
3258 desc->id_isar5, id_isar5_fields);
3259
3260 /* AArch32 Media and VFP Feature Register 0 */
3261 if (SHOULD_PRINT_REG(mvfr0))
3262 print_id_register(sb, "AArch32 Media and VFP Features 0",
3263 desc->mvfr0, mvfr0_fields);
3264
3265 /* AArch32 Media and VFP Feature Register 1 */
3266 if (SHOULD_PRINT_REG(mvfr1))
3267 print_id_register(sb, "AArch32 Media and VFP Features 1",
3268 desc->mvfr1, mvfr1_fields);
3269 #endif
3270 if (bootverbose)
3271 print_cpu_caches(sb, desc);
3272
3273 sbuf_delete(sb);
3274 sb = NULL;
3275 #undef SHOULD_PRINT_REG
3276 #undef SEP_STR
3277 }
3278
3279 void
identify_cache(uint64_t ctr)3280 identify_cache(uint64_t ctr)
3281 {
3282
3283 /* Identify the L1 cache type */
3284 switch (CTR_L1IP_VAL(ctr)) {
3285 case CTR_L1IP_PIPT:
3286 break;
3287 default:
3288 case CTR_L1IP_VIPT:
3289 icache_aliasing = true;
3290 break;
3291 }
3292
3293 if (dcache_line_size == 0) {
3294 KASSERT(icache_line_size == 0, ("%s: i-cacheline size set: %ld",
3295 __func__, icache_line_size));
3296
3297 /* Get the D cache line size */
3298 dcache_line_size = CTR_DLINE_SIZE(ctr);
3299 /* And the same for the I cache */
3300 icache_line_size = CTR_ILINE_SIZE(ctr);
3301
3302 idcache_line_size = MIN(dcache_line_size, icache_line_size);
3303 }
3304
3305 if (dcache_line_size != CTR_DLINE_SIZE(ctr)) {
3306 printf("WARNING: D-cacheline size mismatch %ld != %d\n",
3307 dcache_line_size, CTR_DLINE_SIZE(ctr));
3308 }
3309
3310 if (icache_line_size != CTR_ILINE_SIZE(ctr)) {
3311 printf("WARNING: I-cacheline size mismatch %ld != %d\n",
3312 icache_line_size, CTR_ILINE_SIZE(ctr));
3313 }
3314 }
3315
3316 void
identify_cpu(u_int cpu)3317 identify_cpu(u_int cpu)
3318 {
3319 struct cpu_desc *desc;
3320 uint64_t clidr;
3321
3322 desc = get_cpu_desc(cpu);
3323 /* Save affinity for current CPU */
3324 desc->mpidr = get_mpidr();
3325 CPU_AFFINITY(cpu) = desc->mpidr & CPU_AFF_MASK;
3326
3327 desc->ctr = READ_SPECIALREG(ctr_el0);
3328 desc->id_aa64dfr0 = READ_SPECIALREG(ID_AA64DFR0_EL1_REG);
3329 desc->id_aa64dfr1 = READ_SPECIALREG(ID_AA64DFR1_EL1_REG);
3330 desc->id_aa64isar0 = READ_SPECIALREG(ID_AA64ISAR0_EL1_REG);
3331 desc->id_aa64isar1 = READ_SPECIALREG(ID_AA64ISAR1_EL1_REG);
3332 desc->id_aa64isar2 = READ_SPECIALREG(ID_AA64ISAR2_EL1_REG);
3333 desc->id_aa64mmfr0 = READ_SPECIALREG(ID_AA64MMFR0_EL1_REG);
3334 desc->id_aa64mmfr1 = READ_SPECIALREG(ID_AA64MMFR1_EL1_REG);
3335 desc->id_aa64mmfr2 = READ_SPECIALREG(ID_AA64MMFR2_EL1_REG);
3336 desc->id_aa64mmfr3 = READ_SPECIALREG(ID_AA64MMFR3_EL1_REG);
3337 desc->id_aa64mmfr4 = READ_SPECIALREG(ID_AA64MMFR4_EL1_REG);
3338 desc->id_aa64pfr0 = READ_SPECIALREG(ID_AA64PFR0_EL1_REG);
3339 desc->id_aa64pfr1 = READ_SPECIALREG(ID_AA64PFR1_EL1_REG);
3340 desc->id_aa64pfr2 = READ_SPECIALREG(ID_AA64PFR2_EL1_REG);
3341
3342 /*
3343 * ID_AA64ZFR0_EL1 is only valid when at least one of:
3344 * - ID_AA64PFR0_EL1.SVE is non-zero
3345 * - ID_AA64PFR1_EL1.SME is non-zero
3346 * In other cases it is zero, but still safe to read
3347 */
3348 desc->have_sve =
3349 (ID_AA64PFR0_SVE_VAL(desc->id_aa64pfr0) != 0);
3350 desc->id_aa64zfr0 = READ_SPECIALREG(ID_AA64ZFR0_EL1_REG);
3351
3352 desc->clidr = READ_SPECIALREG(clidr_el1);
3353
3354 clidr = desc->clidr;
3355
3356 for (int i = 0; (clidr & CLIDR_CTYPE_MASK) != 0; i++, clidr >>= 3) {
3357 int j = 0;
3358 if ((clidr & CLIDR_CTYPE_IO)) {
3359 WRITE_SPECIALREG(csselr_el1,
3360 CSSELR_Level(i) | CSSELR_InD);
3361 desc->ccsidr[i][j++] =
3362 READ_SPECIALREG(ccsidr_el1);
3363 }
3364 if ((clidr & ~CLIDR_CTYPE_IO) == 0)
3365 continue;
3366 WRITE_SPECIALREG(csselr_el1, CSSELR_Level(i));
3367 desc->ccsidr[i][j] = READ_SPECIALREG(ccsidr_el1);
3368 }
3369
3370 #ifdef COMPAT_FREEBSD32
3371 /* Only read aarch32 SRs if EL0-32 is available */
3372 if (ID_AA64PFR0_EL0_VAL(desc->id_aa64pfr0) == ID_AA64PFR0_EL0_64_32) {
3373 desc->id_isar5 = READ_SPECIALREG(id_isar5_el1);
3374 desc->mvfr0 = READ_SPECIALREG(mvfr0_el1);
3375 desc->mvfr1 = READ_SPECIALREG(mvfr1_el1);
3376 }
3377 #endif
3378 }
3379
3380 static void
check_cpu_regs(u_int cpu,struct cpu_desc * desc,struct cpu_desc * prev_desc)3381 check_cpu_regs(u_int cpu, struct cpu_desc *desc, struct cpu_desc *prev_desc)
3382 {
3383 switch (cpu_aff_levels) {
3384 case 0:
3385 if (CPU_AFF0(desc->mpidr) != CPU_AFF0(prev_desc->mpidr))
3386 cpu_aff_levels = 1;
3387 /* FALLTHROUGH */
3388 case 1:
3389 if (CPU_AFF1(desc->mpidr) != CPU_AFF1(prev_desc->mpidr))
3390 cpu_aff_levels = 2;
3391 /* FALLTHROUGH */
3392 case 2:
3393 if (CPU_AFF2(desc->mpidr) != CPU_AFF2(prev_desc->mpidr))
3394 cpu_aff_levels = 3;
3395 /* FALLTHROUGH */
3396 case 3:
3397 if (CPU_AFF3(desc->mpidr) != CPU_AFF3(prev_desc->mpidr))
3398 cpu_aff_levels = 4;
3399 break;
3400 }
3401
3402 if (desc->ctr != prev_desc->ctr) {
3403 /*
3404 * If the cache is different on different cores we should
3405 * emulate for userspace to provide a uniform value
3406 */
3407 emulate_ctr = true;
3408
3409 /*
3410 * If the cache type register is different we may
3411 * have a different l1 cache type.
3412 */
3413 identify_cache(desc->ctr);
3414 }
3415 }
3416