1
2 /*-
3 * Copyright (c) 2005, 2006
4 * Damien Bergamini <damien.bergamini@free.fr>
5 *
6 * Copyright (c) 2006, 2008
7 * Hans Petter Selasky <hselasky@FreeBSD.org>
8 *
9 * Permission to use, copy, modify, and distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 */
21
22 /*-
23 * Ralink Technology RT2500USB chipset driver
24 * http://www.ralinktech.com/
25 */
26
27 #include "opt_wlan.h"
28
29 #include <sys/param.h>
30 #include <sys/sockio.h>
31 #include <sys/sysctl.h>
32 #include <sys/lock.h>
33 #include <sys/mutex.h>
34 #include <sys/mbuf.h>
35 #include <sys/kernel.h>
36 #include <sys/socket.h>
37 #include <sys/systm.h>
38 #include <sys/malloc.h>
39 #include <sys/module.h>
40 #include <sys/bus.h>
41 #include <sys/endian.h>
42 #include <sys/kdb.h>
43
44 #include <net/bpf.h>
45 #include <net/if.h>
46 #include <net/if_var.h>
47 #include <net/if_arp.h>
48 #include <net/ethernet.h>
49 #include <net/if_dl.h>
50 #include <net/if_media.h>
51 #include <net/if_types.h>
52
53 #ifdef INET
54 #include <netinet/in.h>
55 #include <netinet/in_systm.h>
56 #include <netinet/in_var.h>
57 #include <netinet/if_ether.h>
58 #include <netinet/ip.h>
59 #endif
60
61 #include <net80211/ieee80211_var.h>
62 #include <net80211/ieee80211_regdomain.h>
63 #include <net80211/ieee80211_radiotap.h>
64 #include <net80211/ieee80211_ratectl.h>
65
66 #include <dev/usb/usb.h>
67 #include <dev/usb/usbdi.h>
68 #include "usbdevs.h"
69
70 #define USB_DEBUG_VAR ural_debug
71 #include <dev/usb/usb_debug.h>
72
73 #include <dev/usb/wlan/if_uralreg.h>
74 #include <dev/usb/wlan/if_uralvar.h>
75
76 #ifdef USB_DEBUG
77 static int ural_debug = 0;
78
79 static SYSCTL_NODE(_hw_usb, OID_AUTO, ural, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
80 "USB ural");
81 SYSCTL_INT(_hw_usb_ural, OID_AUTO, debug, CTLFLAG_RWTUN, &ural_debug, 0,
82 "Debug level");
83 #endif
84
85 #define URAL_RSSI(rssi) \
86 ((rssi) > (RAL_NOISE_FLOOR + RAL_RSSI_CORR) ? \
87 ((rssi) - (RAL_NOISE_FLOOR + RAL_RSSI_CORR)) : 0)
88
89 /* various supported device vendors/products */
90 static const STRUCT_USB_HOST_ID ural_devs[] = {
91 #define URAL_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) }
92 URAL_DEV(ASUS, WL167G),
93 URAL_DEV(ASUS, RT2570),
94 URAL_DEV(BELKIN, F5D7050),
95 URAL_DEV(BELKIN, F5D7051),
96 URAL_DEV(CISCOLINKSYS, HU200TS),
97 URAL_DEV(CISCOLINKSYS, WUSB54G),
98 URAL_DEV(CISCOLINKSYS, WUSB54GP),
99 URAL_DEV(CONCEPTRONIC2, C54RU),
100 URAL_DEV(DLINK, DWLG122),
101 URAL_DEV(GIGABYTE, GN54G),
102 URAL_DEV(GIGABYTE, GNWBKG),
103 URAL_DEV(GUILLEMOT, HWGUSB254),
104 URAL_DEV(MELCO, KG54),
105 URAL_DEV(MELCO, KG54AI),
106 URAL_DEV(MELCO, KG54YB),
107 URAL_DEV(MELCO, NINWIFI),
108 URAL_DEV(MSI, RT2570),
109 URAL_DEV(MSI, RT2570_2),
110 URAL_DEV(MSI, RT2570_3),
111 URAL_DEV(NOVATECH, NV902),
112 URAL_DEV(RALINK, RT2570),
113 URAL_DEV(RALINK, RT2570_2),
114 URAL_DEV(RALINK, RT2570_3),
115 URAL_DEV(SIEMENS2, WL54G),
116 URAL_DEV(SMC, 2862WG),
117 URAL_DEV(SPHAIRON, UB801R),
118 URAL_DEV(SURECOM, RT2570),
119 URAL_DEV(VTECH, RT2570),
120 URAL_DEV(ZINWELL, RT2570),
121 #undef URAL_DEV
122 };
123
124 static usb_callback_t ural_bulk_read_callback;
125 static usb_callback_t ural_bulk_write_callback;
126
127 static usb_error_t ural_do_request(struct ural_softc *sc,
128 struct usb_device_request *req, void *data);
129 static struct ieee80211vap *ural_vap_create(struct ieee80211com *,
130 const char [IFNAMSIZ], int, enum ieee80211_opmode,
131 int, const uint8_t [IEEE80211_ADDR_LEN],
132 const uint8_t [IEEE80211_ADDR_LEN]);
133 static void ural_vap_delete(struct ieee80211vap *);
134 static void ural_tx_free(struct ural_tx_data *, int);
135 static void ural_setup_tx_list(struct ural_softc *);
136 static void ural_unsetup_tx_list(struct ural_softc *);
137 static int ural_newstate(struct ieee80211vap *,
138 enum ieee80211_state, int);
139 static void ural_setup_tx_desc(struct ural_softc *,
140 struct ural_tx_desc *, uint32_t, int, int);
141 static int ural_tx_bcn(struct ural_softc *, struct mbuf *,
142 struct ieee80211_node *);
143 static int ural_tx_mgt(struct ural_softc *, struct mbuf *,
144 struct ieee80211_node *);
145 static int ural_tx_data(struct ural_softc *, struct mbuf *,
146 struct ieee80211_node *);
147 static int ural_transmit(struct ieee80211com *, struct mbuf *);
148 static void ural_start(struct ural_softc *);
149 static void ural_parent(struct ieee80211com *);
150 static void ural_set_testmode(struct ural_softc *);
151 static void ural_eeprom_read(struct ural_softc *, uint16_t, void *,
152 int);
153 static uint16_t ural_read(struct ural_softc *, uint16_t);
154 static void ural_read_multi(struct ural_softc *, uint16_t, void *,
155 int);
156 static void ural_write(struct ural_softc *, uint16_t, uint16_t);
157 static void ural_write_multi(struct ural_softc *, uint16_t, void *,
158 int) __unused;
159 static void ural_bbp_write(struct ural_softc *, uint8_t, uint8_t);
160 static uint8_t ural_bbp_read(struct ural_softc *, uint8_t);
161 static void ural_rf_write(struct ural_softc *, uint8_t, uint32_t);
162 static void ural_scan_start(struct ieee80211com *);
163 static void ural_scan_end(struct ieee80211com *);
164 static void ural_getradiocaps(struct ieee80211com *, int, int *,
165 struct ieee80211_channel[]);
166 static void ural_set_channel(struct ieee80211com *);
167 static void ural_set_chan(struct ural_softc *,
168 struct ieee80211_channel *);
169 static void ural_disable_rf_tune(struct ural_softc *);
170 static void ural_enable_tsf_sync(struct ural_softc *);
171 static void ural_enable_tsf(struct ural_softc *);
172 static void ural_update_slot(struct ural_softc *);
173 static void ural_set_txpreamble(struct ural_softc *);
174 static void ural_set_basicrates(struct ural_softc *,
175 const struct ieee80211_channel *);
176 static void ural_set_bssid(struct ural_softc *, const uint8_t *);
177 static void ural_set_macaddr(struct ural_softc *, const uint8_t *);
178 static void ural_update_promisc(struct ieee80211com *);
179 static void ural_setpromisc(struct ural_softc *);
180 static const char *ural_get_rf(int);
181 static void ural_read_eeprom(struct ural_softc *);
182 static int ural_bbp_init(struct ural_softc *);
183 static void ural_set_txantenna(struct ural_softc *, int);
184 static void ural_set_rxantenna(struct ural_softc *, int);
185 static void ural_init(struct ural_softc *);
186 static void ural_stop(struct ural_softc *);
187 static int ural_raw_xmit(struct ieee80211_node *, struct mbuf *,
188 const struct ieee80211_bpf_params *);
189 static void ural_ratectl_start(struct ural_softc *,
190 struct ieee80211_node *);
191 static void ural_ratectl_timeout(void *);
192 static void ural_ratectl_task(void *, int);
193 static int ural_pause(struct ural_softc *sc, int timeout);
194
195 /*
196 * Default values for MAC registers; values taken from the reference driver.
197 */
198 static const struct {
199 uint16_t reg;
200 uint16_t val;
201 } ural_def_mac[] = {
202 { RAL_TXRX_CSR5, 0x8c8d },
203 { RAL_TXRX_CSR6, 0x8b8a },
204 { RAL_TXRX_CSR7, 0x8687 },
205 { RAL_TXRX_CSR8, 0x0085 },
206 { RAL_MAC_CSR13, 0x1111 },
207 { RAL_MAC_CSR14, 0x1e11 },
208 { RAL_TXRX_CSR21, 0xe78f },
209 { RAL_MAC_CSR9, 0xff1d },
210 { RAL_MAC_CSR11, 0x0002 },
211 { RAL_MAC_CSR22, 0x0053 },
212 { RAL_MAC_CSR15, 0x0000 },
213 { RAL_MAC_CSR8, RAL_FRAME_SIZE },
214 { RAL_TXRX_CSR19, 0x0000 },
215 { RAL_TXRX_CSR18, 0x005a },
216 { RAL_PHY_CSR2, 0x0000 },
217 { RAL_TXRX_CSR0, 0x1ec0 },
218 { RAL_PHY_CSR4, 0x000f }
219 };
220
221 /*
222 * Default values for BBP registers; values taken from the reference driver.
223 */
224 static const struct {
225 uint8_t reg;
226 uint8_t val;
227 } ural_def_bbp[] = {
228 { 3, 0x02 },
229 { 4, 0x19 },
230 { 14, 0x1c },
231 { 15, 0x30 },
232 { 16, 0xac },
233 { 17, 0x48 },
234 { 18, 0x18 },
235 { 19, 0xff },
236 { 20, 0x1e },
237 { 21, 0x08 },
238 { 22, 0x08 },
239 { 23, 0x08 },
240 { 24, 0x80 },
241 { 25, 0x50 },
242 { 26, 0x08 },
243 { 27, 0x23 },
244 { 30, 0x10 },
245 { 31, 0x2b },
246 { 32, 0xb9 },
247 { 34, 0x12 },
248 { 35, 0x50 },
249 { 39, 0xc4 },
250 { 40, 0x02 },
251 { 41, 0x60 },
252 { 53, 0x10 },
253 { 54, 0x18 },
254 { 56, 0x08 },
255 { 57, 0x10 },
256 { 58, 0x08 },
257 { 61, 0x60 },
258 { 62, 0x10 },
259 { 75, 0xff }
260 };
261
262 /*
263 * Default values for RF register R2 indexed by channel numbers.
264 */
265 static const uint32_t ural_rf2522_r2[] = {
266 0x307f6, 0x307fb, 0x30800, 0x30805, 0x3080a, 0x3080f, 0x30814,
267 0x30819, 0x3081e, 0x30823, 0x30828, 0x3082d, 0x30832, 0x3083e
268 };
269
270 static const uint32_t ural_rf2523_r2[] = {
271 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d,
272 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346
273 };
274
275 static const uint32_t ural_rf2524_r2[] = {
276 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d,
277 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346
278 };
279
280 static const uint32_t ural_rf2525_r2[] = {
281 0x20327, 0x20328, 0x20329, 0x2032a, 0x2032b, 0x2032c, 0x2032d,
282 0x2032e, 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20346
283 };
284
285 static const uint32_t ural_rf2525_hi_r2[] = {
286 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20344, 0x20345,
287 0x20346, 0x20347, 0x20348, 0x20349, 0x2034a, 0x2034b, 0x2034e
288 };
289
290 static const uint32_t ural_rf2525e_r2[] = {
291 0x2044d, 0x2044e, 0x2044f, 0x20460, 0x20461, 0x20462, 0x20463,
292 0x20464, 0x20465, 0x20466, 0x20467, 0x20468, 0x20469, 0x2046b
293 };
294
295 static const uint32_t ural_rf2526_hi_r2[] = {
296 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d, 0x0022d,
297 0x0022e, 0x0022e, 0x0022f, 0x0022d, 0x00240, 0x00240, 0x00241
298 };
299
300 static const uint32_t ural_rf2526_r2[] = {
301 0x00226, 0x00227, 0x00227, 0x00228, 0x00228, 0x00229, 0x00229,
302 0x0022a, 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d
303 };
304
305 /*
306 * For dual-band RF, RF registers R1 and R4 also depend on channel number;
307 * values taken from the reference driver.
308 */
309 static const struct {
310 uint8_t chan;
311 uint32_t r1;
312 uint32_t r2;
313 uint32_t r4;
314 } ural_rf5222[] = {
315 { 1, 0x08808, 0x0044d, 0x00282 },
316 { 2, 0x08808, 0x0044e, 0x00282 },
317 { 3, 0x08808, 0x0044f, 0x00282 },
318 { 4, 0x08808, 0x00460, 0x00282 },
319 { 5, 0x08808, 0x00461, 0x00282 },
320 { 6, 0x08808, 0x00462, 0x00282 },
321 { 7, 0x08808, 0x00463, 0x00282 },
322 { 8, 0x08808, 0x00464, 0x00282 },
323 { 9, 0x08808, 0x00465, 0x00282 },
324 { 10, 0x08808, 0x00466, 0x00282 },
325 { 11, 0x08808, 0x00467, 0x00282 },
326 { 12, 0x08808, 0x00468, 0x00282 },
327 { 13, 0x08808, 0x00469, 0x00282 },
328 { 14, 0x08808, 0x0046b, 0x00286 },
329
330 { 36, 0x08804, 0x06225, 0x00287 },
331 { 40, 0x08804, 0x06226, 0x00287 },
332 { 44, 0x08804, 0x06227, 0x00287 },
333 { 48, 0x08804, 0x06228, 0x00287 },
334 { 52, 0x08804, 0x06229, 0x00287 },
335 { 56, 0x08804, 0x0622a, 0x00287 },
336 { 60, 0x08804, 0x0622b, 0x00287 },
337 { 64, 0x08804, 0x0622c, 0x00287 },
338
339 { 100, 0x08804, 0x02200, 0x00283 },
340 { 104, 0x08804, 0x02201, 0x00283 },
341 { 108, 0x08804, 0x02202, 0x00283 },
342 { 112, 0x08804, 0x02203, 0x00283 },
343 { 116, 0x08804, 0x02204, 0x00283 },
344 { 120, 0x08804, 0x02205, 0x00283 },
345 { 124, 0x08804, 0x02206, 0x00283 },
346 { 128, 0x08804, 0x02207, 0x00283 },
347 { 132, 0x08804, 0x02208, 0x00283 },
348 { 136, 0x08804, 0x02209, 0x00283 },
349 { 140, 0x08804, 0x0220a, 0x00283 },
350
351 { 149, 0x08808, 0x02429, 0x00281 },
352 { 153, 0x08808, 0x0242b, 0x00281 },
353 { 157, 0x08808, 0x0242d, 0x00281 },
354 { 161, 0x08808, 0x0242f, 0x00281 }
355 };
356
357 static const uint8_t ural_chan_5ghz[] =
358 { 36, 40, 44, 48, 52, 56, 60, 64,
359 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140,
360 149, 153, 157, 161 };
361
362 static const struct usb_config ural_config[URAL_N_TRANSFER] = {
363 [URAL_BULK_WR] = {
364 .type = UE_BULK,
365 .endpoint = UE_ADDR_ANY,
366 .direction = UE_DIR_OUT,
367 .bufsize = (RAL_FRAME_SIZE + RAL_TX_DESC_SIZE + 4),
368 .flags = {.pipe_bof = 1,.force_short_xfer = 1,},
369 .callback = ural_bulk_write_callback,
370 .timeout = 5000, /* ms */
371 },
372 [URAL_BULK_RD] = {
373 .type = UE_BULK,
374 .endpoint = UE_ADDR_ANY,
375 .direction = UE_DIR_IN,
376 .bufsize = (RAL_FRAME_SIZE + RAL_RX_DESC_SIZE),
377 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,},
378 .callback = ural_bulk_read_callback,
379 },
380 };
381
382 static device_probe_t ural_match;
383 static device_attach_t ural_attach;
384 static device_detach_t ural_detach;
385
386 static device_method_t ural_methods[] = {
387 /* Device interface */
388 DEVMETHOD(device_probe, ural_match),
389 DEVMETHOD(device_attach, ural_attach),
390 DEVMETHOD(device_detach, ural_detach),
391 DEVMETHOD_END
392 };
393
394 static driver_t ural_driver = {
395 .name = "ural",
396 .methods = ural_methods,
397 .size = sizeof(struct ural_softc),
398 };
399
400 DRIVER_MODULE(ural, uhub, ural_driver, NULL, NULL);
401 MODULE_DEPEND(ural, usb, 1, 1, 1);
402 MODULE_DEPEND(ural, wlan, 1, 1, 1);
403 MODULE_VERSION(ural, 1);
404 USB_PNP_HOST_INFO(ural_devs);
405
406 static int
ural_match(device_t self)407 ural_match(device_t self)
408 {
409 struct usb_attach_arg *uaa = device_get_ivars(self);
410
411 if (uaa->usb_mode != USB_MODE_HOST)
412 return (ENXIO);
413 if (uaa->info.bConfigIndex != 0)
414 return (ENXIO);
415 if (uaa->info.bIfaceIndex != RAL_IFACE_INDEX)
416 return (ENXIO);
417
418 return (usbd_lookup_id_by_uaa(ural_devs, sizeof(ural_devs), uaa));
419 }
420
421 static int
ural_attach(device_t self)422 ural_attach(device_t self)
423 {
424 struct usb_attach_arg *uaa = device_get_ivars(self);
425 struct ural_softc *sc = device_get_softc(self);
426 struct ieee80211com *ic = &sc->sc_ic;
427 uint8_t iface_index;
428 int error;
429
430 device_set_usb_desc(self);
431 sc->sc_udev = uaa->device;
432 sc->sc_dev = self;
433
434 mtx_init(&sc->sc_mtx, device_get_nameunit(self),
435 MTX_NETWORK_LOCK, MTX_DEF);
436 mbufq_init(&sc->sc_snd, ifqmaxlen);
437
438 iface_index = RAL_IFACE_INDEX;
439 error = usbd_transfer_setup(uaa->device,
440 &iface_index, sc->sc_xfer, ural_config,
441 URAL_N_TRANSFER, sc, &sc->sc_mtx);
442 if (error) {
443 device_printf(self, "could not allocate USB transfers, "
444 "err=%s\n", usbd_errstr(error));
445 goto detach;
446 }
447
448 RAL_LOCK(sc);
449 /* retrieve RT2570 rev. no */
450 sc->asic_rev = ural_read(sc, RAL_MAC_CSR0);
451
452 /* retrieve MAC address and various other things from EEPROM */
453 ural_read_eeprom(sc);
454 RAL_UNLOCK(sc);
455
456 device_printf(self, "MAC/BBP RT2570 (rev 0x%02x), RF %s\n",
457 sc->asic_rev, ural_get_rf(sc->rf_rev));
458
459 ic->ic_softc = sc;
460 ic->ic_name = device_get_nameunit(self);
461 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
462
463 /* set device capabilities */
464 ic->ic_caps =
465 IEEE80211_C_STA /* station mode supported */
466 | IEEE80211_C_IBSS /* IBSS mode supported */
467 | IEEE80211_C_MONITOR /* monitor mode supported */
468 | IEEE80211_C_HOSTAP /* HostAp mode supported */
469 | IEEE80211_C_TXPMGT /* tx power management */
470 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
471 | IEEE80211_C_SHSLOT /* short slot time supported */
472 | IEEE80211_C_BGSCAN /* bg scanning supported */
473 | IEEE80211_C_WPA /* 802.11i */
474 ;
475
476 ic->ic_flags_ext |= IEEE80211_FEXT_SEQNO_OFFLOAD;
477
478 ural_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans,
479 ic->ic_channels);
480
481 ieee80211_ifattach(ic);
482 ic->ic_update_promisc = ural_update_promisc;
483 ic->ic_raw_xmit = ural_raw_xmit;
484 ic->ic_scan_start = ural_scan_start;
485 ic->ic_scan_end = ural_scan_end;
486 ic->ic_getradiocaps = ural_getradiocaps;
487 ic->ic_set_channel = ural_set_channel;
488 ic->ic_parent = ural_parent;
489 ic->ic_transmit = ural_transmit;
490 ic->ic_vap_create = ural_vap_create;
491 ic->ic_vap_delete = ural_vap_delete;
492
493 ieee80211_radiotap_attach(ic,
494 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap),
495 RAL_TX_RADIOTAP_PRESENT,
496 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap),
497 RAL_RX_RADIOTAP_PRESENT);
498
499 if (bootverbose)
500 ieee80211_announce(ic);
501
502 return (0);
503
504 detach:
505 ural_detach(self);
506 return (ENXIO); /* failure */
507 }
508
509 static int
ural_detach(device_t self)510 ural_detach(device_t self)
511 {
512 struct ural_softc *sc = device_get_softc(self);
513 struct ieee80211com *ic = &sc->sc_ic;
514
515 /* prevent further ioctls */
516 RAL_LOCK(sc);
517 sc->sc_detached = 1;
518 RAL_UNLOCK(sc);
519
520 /* stop all USB transfers */
521 usbd_transfer_unsetup(sc->sc_xfer, URAL_N_TRANSFER);
522
523 /* free TX list, if any */
524 RAL_LOCK(sc);
525 ural_unsetup_tx_list(sc);
526 RAL_UNLOCK(sc);
527
528 if (ic->ic_softc == sc)
529 ieee80211_ifdetach(ic);
530 mbufq_drain(&sc->sc_snd);
531 mtx_destroy(&sc->sc_mtx);
532
533 return (0);
534 }
535
536 static usb_error_t
ural_do_request(struct ural_softc * sc,struct usb_device_request * req,void * data)537 ural_do_request(struct ural_softc *sc,
538 struct usb_device_request *req, void *data)
539 {
540 usb_error_t err;
541 int ntries = 10;
542
543 while (ntries--) {
544 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx,
545 req, data, 0, NULL, 250 /* ms */);
546 if (err == 0)
547 break;
548
549 DPRINTFN(1, "Control request failed, %s (retrying)\n",
550 usbd_errstr(err));
551 if (ural_pause(sc, hz / 100))
552 break;
553 }
554 return (err);
555 }
556
557 static struct ieee80211vap *
ural_vap_create(struct ieee80211com * ic,const char name[IFNAMSIZ],int unit,enum ieee80211_opmode opmode,int flags,const uint8_t bssid[IEEE80211_ADDR_LEN],const uint8_t mac[IEEE80211_ADDR_LEN])558 ural_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
559 enum ieee80211_opmode opmode, int flags,
560 const uint8_t bssid[IEEE80211_ADDR_LEN],
561 const uint8_t mac[IEEE80211_ADDR_LEN])
562 {
563 struct ural_softc *sc = ic->ic_softc;
564 struct ural_vap *uvp;
565 struct ieee80211vap *vap;
566
567 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */
568 return NULL;
569 uvp = malloc(sizeof(struct ural_vap), M_80211_VAP, M_WAITOK | M_ZERO);
570 vap = &uvp->vap;
571 /* enable s/w bmiss handling for sta mode */
572
573 if (ieee80211_vap_setup(ic, vap, name, unit, opmode,
574 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) {
575 /* out of memory */
576 free(uvp, M_80211_VAP);
577 return (NULL);
578 }
579
580 /* override state transition machine */
581 uvp->newstate = vap->iv_newstate;
582 vap->iv_newstate = ural_newstate;
583
584 usb_callout_init_mtx(&uvp->ratectl_ch, &sc->sc_mtx, 0);
585 TASK_INIT(&uvp->ratectl_task, 0, ural_ratectl_task, uvp);
586 ieee80211_ratectl_init(vap);
587 ieee80211_ratectl_setinterval(vap, 1000 /* 1 sec */);
588
589 /* complete setup */
590 ieee80211_vap_attach(vap, ieee80211_media_change,
591 ieee80211_media_status, mac);
592 ic->ic_opmode = opmode;
593 return vap;
594 }
595
596 static void
ural_vap_delete(struct ieee80211vap * vap)597 ural_vap_delete(struct ieee80211vap *vap)
598 {
599 struct ural_vap *uvp = URAL_VAP(vap);
600 struct ieee80211com *ic = vap->iv_ic;
601
602 usb_callout_drain(&uvp->ratectl_ch);
603 ieee80211_draintask(ic, &uvp->ratectl_task);
604 ieee80211_ratectl_deinit(vap);
605 ieee80211_vap_detach(vap);
606 free(uvp, M_80211_VAP);
607 }
608
609 static void
ural_tx_free(struct ural_tx_data * data,int txerr)610 ural_tx_free(struct ural_tx_data *data, int txerr)
611 {
612 struct ural_softc *sc = data->sc;
613
614 if (data->m != NULL) {
615 ieee80211_tx_complete(data->ni, data->m, txerr);
616 data->m = NULL;
617 data->ni = NULL;
618 }
619 STAILQ_INSERT_TAIL(&sc->tx_free, data, next);
620 sc->tx_nfree++;
621 }
622
623 static void
ural_setup_tx_list(struct ural_softc * sc)624 ural_setup_tx_list(struct ural_softc *sc)
625 {
626 struct ural_tx_data *data;
627 int i;
628
629 sc->tx_nfree = 0;
630 STAILQ_INIT(&sc->tx_q);
631 STAILQ_INIT(&sc->tx_free);
632
633 for (i = 0; i < RAL_TX_LIST_COUNT; i++) {
634 data = &sc->tx_data[i];
635
636 data->sc = sc;
637 STAILQ_INSERT_TAIL(&sc->tx_free, data, next);
638 sc->tx_nfree++;
639 }
640 }
641
642 static void
ural_unsetup_tx_list(struct ural_softc * sc)643 ural_unsetup_tx_list(struct ural_softc *sc)
644 {
645 struct ural_tx_data *data;
646 int i;
647
648 /* make sure any subsequent use of the queues will fail */
649 sc->tx_nfree = 0;
650 STAILQ_INIT(&sc->tx_q);
651 STAILQ_INIT(&sc->tx_free);
652
653 /* free up all node references and mbufs */
654 for (i = 0; i < RAL_TX_LIST_COUNT; i++) {
655 data = &sc->tx_data[i];
656
657 if (data->m != NULL) {
658 m_freem(data->m);
659 data->m = NULL;
660 }
661 if (data->ni != NULL) {
662 ieee80211_free_node(data->ni);
663 data->ni = NULL;
664 }
665 }
666 }
667
668 static int
ural_newstate(struct ieee80211vap * vap,enum ieee80211_state nstate,int arg)669 ural_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
670 {
671 struct ural_vap *uvp = URAL_VAP(vap);
672 struct ieee80211com *ic = vap->iv_ic;
673 struct ural_softc *sc = ic->ic_softc;
674 const struct ieee80211_txparam *tp;
675 struct ieee80211_node *ni;
676 struct mbuf *m;
677
678 DPRINTF("%s -> %s\n",
679 ieee80211_state_name[vap->iv_state],
680 ieee80211_state_name[nstate]);
681
682 IEEE80211_UNLOCK(ic);
683 RAL_LOCK(sc);
684 usb_callout_stop(&uvp->ratectl_ch);
685
686 switch (nstate) {
687 case IEEE80211_S_INIT:
688 if (vap->iv_state == IEEE80211_S_RUN) {
689 /* abort TSF synchronization */
690 ural_write(sc, RAL_TXRX_CSR19, 0);
691
692 /* force tx led to stop blinking */
693 ural_write(sc, RAL_MAC_CSR20, 0);
694 }
695 break;
696
697 case IEEE80211_S_RUN:
698 ni = ieee80211_ref_node(vap->iv_bss);
699
700 if (vap->iv_opmode != IEEE80211_M_MONITOR) {
701 if (ic->ic_bsschan == IEEE80211_CHAN_ANYC)
702 goto fail;
703
704 ural_update_slot(sc);
705 ural_set_txpreamble(sc);
706 ural_set_basicrates(sc, ic->ic_bsschan);
707 IEEE80211_ADDR_COPY(sc->sc_bssid, ni->ni_bssid);
708 ural_set_bssid(sc, sc->sc_bssid);
709 }
710
711 if (vap->iv_opmode == IEEE80211_M_HOSTAP ||
712 vap->iv_opmode == IEEE80211_M_IBSS) {
713 m = ieee80211_beacon_alloc(ni);
714 if (m == NULL) {
715 device_printf(sc->sc_dev,
716 "could not allocate beacon\n");
717 goto fail;
718 }
719 ieee80211_ref_node(ni);
720 if (ural_tx_bcn(sc, m, ni) != 0) {
721 device_printf(sc->sc_dev,
722 "could not send beacon\n");
723 goto fail;
724 }
725 }
726
727 /* make tx led blink on tx (controlled by ASIC) */
728 ural_write(sc, RAL_MAC_CSR20, 1);
729
730 if (vap->iv_opmode != IEEE80211_M_MONITOR)
731 ural_enable_tsf_sync(sc);
732 else
733 ural_enable_tsf(sc);
734
735 /* enable automatic rate adaptation */
736 /* XXX should use ic_bsschan but not valid until after newstate call below */
737 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)];
738 if (tp->ucastrate == IEEE80211_FIXED_RATE_NONE)
739 ural_ratectl_start(sc, ni);
740 ieee80211_free_node(ni);
741 break;
742
743 default:
744 break;
745 }
746 RAL_UNLOCK(sc);
747 IEEE80211_LOCK(ic);
748 return (uvp->newstate(vap, nstate, arg));
749
750 fail:
751 RAL_UNLOCK(sc);
752 IEEE80211_LOCK(ic);
753 ieee80211_free_node(ni);
754 return (-1);
755 }
756
757 static void
ural_bulk_write_callback(struct usb_xfer * xfer,usb_error_t error)758 ural_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error)
759 {
760 struct ural_softc *sc = usbd_xfer_softc(xfer);
761 struct ieee80211vap *vap;
762 struct ural_tx_data *data;
763 struct mbuf *m;
764 struct usb_page_cache *pc;
765 int len;
766
767 usbd_xfer_status(xfer, &len, NULL, NULL, NULL);
768
769 switch (USB_GET_STATE(xfer)) {
770 case USB_ST_TRANSFERRED:
771 DPRINTFN(11, "transfer complete, %d bytes\n", len);
772
773 /* free resources */
774 data = usbd_xfer_get_priv(xfer);
775 ural_tx_free(data, 0);
776 usbd_xfer_set_priv(xfer, NULL);
777
778 /* FALLTHROUGH */
779 case USB_ST_SETUP:
780 tr_setup:
781 data = STAILQ_FIRST(&sc->tx_q);
782 if (data) {
783 STAILQ_REMOVE_HEAD(&sc->tx_q, next);
784 m = data->m;
785
786 if (m->m_pkthdr.len > (int)(RAL_FRAME_SIZE + RAL_TX_DESC_SIZE)) {
787 DPRINTFN(0, "data overflow, %u bytes\n",
788 m->m_pkthdr.len);
789 m->m_pkthdr.len = (RAL_FRAME_SIZE + RAL_TX_DESC_SIZE);
790 }
791 pc = usbd_xfer_get_frame(xfer, 0);
792 usbd_copy_in(pc, 0, &data->desc, RAL_TX_DESC_SIZE);
793 usbd_m_copy_in(pc, RAL_TX_DESC_SIZE, m, 0,
794 m->m_pkthdr.len);
795
796 vap = data->ni->ni_vap;
797 if (ieee80211_radiotap_active_vap(vap)) {
798 struct ural_tx_radiotap_header *tap = &sc->sc_txtap;
799
800 tap->wt_flags = 0;
801 tap->wt_rate = data->rate;
802 tap->wt_antenna = sc->tx_ant;
803
804 ieee80211_radiotap_tx(vap, m);
805 }
806
807 /* xfer length needs to be a multiple of two! */
808 len = (RAL_TX_DESC_SIZE + m->m_pkthdr.len + 1) & ~1;
809 if ((len % 64) == 0)
810 len += 2;
811
812 DPRINTFN(11, "sending frame len=%u xferlen=%u\n",
813 m->m_pkthdr.len, len);
814
815 usbd_xfer_set_frame_len(xfer, 0, len);
816 usbd_xfer_set_priv(xfer, data);
817
818 usbd_transfer_submit(xfer);
819 }
820 ural_start(sc);
821 break;
822
823 default: /* Error */
824 DPRINTFN(11, "transfer error, %s\n",
825 usbd_errstr(error));
826
827 data = usbd_xfer_get_priv(xfer);
828 if (data != NULL) {
829 ural_tx_free(data, error);
830 usbd_xfer_set_priv(xfer, NULL);
831 }
832
833 if (error == USB_ERR_STALLED) {
834 /* try to clear stall first */
835 usbd_xfer_set_stall(xfer);
836 goto tr_setup;
837 }
838 if (error == USB_ERR_TIMEOUT)
839 device_printf(sc->sc_dev, "device timeout\n");
840 break;
841 }
842 }
843
844 static void
ural_bulk_read_callback(struct usb_xfer * xfer,usb_error_t error)845 ural_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error)
846 {
847 struct ural_softc *sc = usbd_xfer_softc(xfer);
848 struct ieee80211com *ic = &sc->sc_ic;
849 struct ieee80211_node *ni;
850 struct mbuf *m = NULL;
851 struct usb_page_cache *pc;
852 uint32_t flags;
853 int8_t rssi = 0, nf = 0;
854 int len;
855
856 usbd_xfer_status(xfer, &len, NULL, NULL, NULL);
857
858 switch (USB_GET_STATE(xfer)) {
859 case USB_ST_TRANSFERRED:
860
861 DPRINTFN(15, "rx done, actlen=%d\n", len);
862
863 if (len < (int)(RAL_RX_DESC_SIZE + IEEE80211_MIN_LEN)) {
864 DPRINTF("%s: xfer too short %d\n",
865 device_get_nameunit(sc->sc_dev), len);
866 counter_u64_add(ic->ic_ierrors, 1);
867 goto tr_setup;
868 }
869
870 len -= RAL_RX_DESC_SIZE;
871 /* rx descriptor is located at the end */
872 pc = usbd_xfer_get_frame(xfer, 0);
873 usbd_copy_out(pc, len, &sc->sc_rx_desc, RAL_RX_DESC_SIZE);
874
875 rssi = URAL_RSSI(sc->sc_rx_desc.rssi);
876 nf = RAL_NOISE_FLOOR;
877 flags = le32toh(sc->sc_rx_desc.flags);
878 if (flags & (RAL_RX_PHY_ERROR | RAL_RX_CRC_ERROR)) {
879 /*
880 * This should not happen since we did not
881 * request to receive those frames when we
882 * filled RAL_TXRX_CSR2:
883 */
884 DPRINTFN(5, "PHY or CRC error\n");
885 counter_u64_add(ic->ic_ierrors, 1);
886 goto tr_setup;
887 }
888
889 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
890 if (m == NULL) {
891 DPRINTF("could not allocate mbuf\n");
892 counter_u64_add(ic->ic_ierrors, 1);
893 goto tr_setup;
894 }
895 usbd_copy_out(pc, 0, mtod(m, uint8_t *), len);
896
897 /* finalize mbuf */
898 m->m_pkthdr.len = m->m_len = (flags >> 16) & 0xfff;
899
900 if (ieee80211_radiotap_active(ic)) {
901 struct ural_rx_radiotap_header *tap = &sc->sc_rxtap;
902
903 /* XXX set once */
904 tap->wr_flags = 0;
905 tap->wr_rate = ieee80211_plcp2rate(sc->sc_rx_desc.rate,
906 (flags & RAL_RX_OFDM) ?
907 IEEE80211_T_OFDM : IEEE80211_T_CCK);
908 tap->wr_antenna = sc->rx_ant;
909 tap->wr_antsignal = nf + rssi;
910 tap->wr_antnoise = nf;
911 }
912 /* Strip trailing 802.11 MAC FCS. */
913 m_adj(m, -IEEE80211_CRC_LEN);
914
915 /* FALLTHROUGH */
916 case USB_ST_SETUP:
917 tr_setup:
918 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));
919 usbd_transfer_submit(xfer);
920
921 /*
922 * At the end of a USB callback it is always safe to unlock
923 * the private mutex of a device! That is why we do the
924 * "ieee80211_input" here, and not some lines up!
925 */
926 RAL_UNLOCK(sc);
927 if (m) {
928 ni = ieee80211_find_rxnode(ic,
929 mtod(m, struct ieee80211_frame_min *));
930 if (ni != NULL) {
931 (void) ieee80211_input(ni, m, rssi, nf);
932 ieee80211_free_node(ni);
933 } else
934 (void) ieee80211_input_all(ic, m, rssi, nf);
935 }
936 RAL_LOCK(sc);
937 ural_start(sc);
938 return;
939
940 default: /* Error */
941 if (error != USB_ERR_CANCELLED) {
942 /* try to clear stall first */
943 usbd_xfer_set_stall(xfer);
944 goto tr_setup;
945 }
946 return;
947 }
948 }
949
950 static uint8_t
ural_plcp_signal(int rate)951 ural_plcp_signal(int rate)
952 {
953 switch (rate) {
954 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */
955 case 12: return 0xb;
956 case 18: return 0xf;
957 case 24: return 0xa;
958 case 36: return 0xe;
959 case 48: return 0x9;
960 case 72: return 0xd;
961 case 96: return 0x8;
962 case 108: return 0xc;
963
964 /* CCK rates (NB: not IEEE std, device-specific) */
965 case 2: return 0x0;
966 case 4: return 0x1;
967 case 11: return 0x2;
968 case 22: return 0x3;
969 }
970 return 0xff; /* XXX unsupported/unknown rate */
971 }
972
973 static void
ural_setup_tx_desc(struct ural_softc * sc,struct ural_tx_desc * desc,uint32_t flags,int len,int rate)974 ural_setup_tx_desc(struct ural_softc *sc, struct ural_tx_desc *desc,
975 uint32_t flags, int len, int rate)
976 {
977 struct ieee80211com *ic = &sc->sc_ic;
978 uint16_t plcp_length;
979 int remainder;
980
981 desc->flags = htole32(flags);
982 desc->flags |= htole32(RAL_TX_NEWSEQ);
983 desc->flags |= htole32(len << 16);
984
985 desc->wme = htole16(RAL_AIFSN(2) | RAL_LOGCWMIN(3) | RAL_LOGCWMAX(5));
986 desc->wme |= htole16(RAL_IVOFFSET(sizeof (struct ieee80211_frame)));
987
988 /* setup PLCP fields */
989 desc->plcp_signal = ural_plcp_signal(rate);
990 desc->plcp_service = 4;
991
992 len += IEEE80211_CRC_LEN;
993 if (ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) {
994 desc->flags |= htole32(RAL_TX_OFDM);
995
996 plcp_length = len & 0xfff;
997 desc->plcp_length_hi = plcp_length >> 6;
998 desc->plcp_length_lo = plcp_length & 0x3f;
999 } else {
1000 if (rate == 0)
1001 rate = 2; /* avoid division by zero */
1002 plcp_length = howmany(16 * len, rate);
1003 if (rate == 22) {
1004 remainder = (16 * len) % 22;
1005 if (remainder != 0 && remainder < 7)
1006 desc->plcp_service |= RAL_PLCP_LENGEXT;
1007 }
1008 desc->plcp_length_hi = plcp_length >> 8;
1009 desc->plcp_length_lo = plcp_length & 0xff;
1010
1011 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
1012 desc->plcp_signal |= 0x08;
1013 }
1014
1015 desc->iv = 0;
1016 desc->eiv = 0;
1017 }
1018
1019 #define RAL_TX_TIMEOUT 5000
1020
1021 static int
ural_tx_bcn(struct ural_softc * sc,struct mbuf * m0,struct ieee80211_node * ni)1022 ural_tx_bcn(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni)
1023 {
1024 struct ieee80211vap *vap = ni->ni_vap;
1025 struct ieee80211com *ic = ni->ni_ic;
1026 const struct ieee80211_txparam *tp;
1027 struct ural_tx_data *data;
1028
1029 if (sc->tx_nfree == 0) {
1030 m_freem(m0);
1031 ieee80211_free_node(ni);
1032 return (EIO);
1033 }
1034 if (ic->ic_bsschan == IEEE80211_CHAN_ANYC) {
1035 m_freem(m0);
1036 ieee80211_free_node(ni);
1037 return (ENXIO);
1038 }
1039 data = STAILQ_FIRST(&sc->tx_free);
1040 STAILQ_REMOVE_HEAD(&sc->tx_free, next);
1041 sc->tx_nfree--;
1042 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_bsschan)];
1043
1044 data->m = m0;
1045 data->ni = ni;
1046 data->rate = tp->mgmtrate;
1047
1048 ural_setup_tx_desc(sc, &data->desc,
1049 RAL_TX_IFS_NEWBACKOFF | RAL_TX_TIMESTAMP, m0->m_pkthdr.len,
1050 tp->mgmtrate);
1051
1052 DPRINTFN(10, "sending beacon frame len=%u rate=%u\n",
1053 m0->m_pkthdr.len, tp->mgmtrate);
1054
1055 STAILQ_INSERT_TAIL(&sc->tx_q, data, next);
1056 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]);
1057
1058 return (0);
1059 }
1060
1061 static int
ural_tx_mgt(struct ural_softc * sc,struct mbuf * m0,struct ieee80211_node * ni)1062 ural_tx_mgt(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni)
1063 {
1064 const struct ieee80211_txparam *tp = ni->ni_txparms;
1065 struct ieee80211com *ic = ni->ni_ic;
1066 struct ural_tx_data *data;
1067 struct ieee80211_frame *wh;
1068 struct ieee80211_key *k;
1069 uint32_t flags;
1070 uint16_t dur;
1071
1072 RAL_LOCK_ASSERT(sc, MA_OWNED);
1073
1074 data = STAILQ_FIRST(&sc->tx_free);
1075 STAILQ_REMOVE_HEAD(&sc->tx_free, next);
1076 sc->tx_nfree--;
1077
1078 ieee80211_output_seqno_assign(ni, -1, m0);
1079
1080 wh = mtod(m0, struct ieee80211_frame *);
1081 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
1082 k = ieee80211_crypto_encap(ni, m0);
1083 if (k == NULL) {
1084 m_freem(m0);
1085 return ENOBUFS;
1086 }
1087 wh = mtod(m0, struct ieee80211_frame *);
1088 }
1089
1090 data->m = m0;
1091 data->ni = ni;
1092 data->rate = tp->mgmtrate;
1093
1094 flags = 0;
1095 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1096 flags |= RAL_TX_ACK;
1097
1098 dur = ieee80211_ack_duration(ic->ic_rt, tp->mgmtrate,
1099 ic->ic_flags & IEEE80211_F_SHPREAMBLE);
1100 USETW(wh->i_dur, dur);
1101
1102 /* tell hardware to add timestamp for probe responses */
1103 if (IEEE80211_IS_MGMT_PROBE_RESP(wh))
1104 flags |= RAL_TX_TIMESTAMP;
1105 }
1106
1107 ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, tp->mgmtrate);
1108
1109 DPRINTFN(10, "sending mgt frame len=%u rate=%u\n",
1110 m0->m_pkthdr.len, tp->mgmtrate);
1111
1112 STAILQ_INSERT_TAIL(&sc->tx_q, data, next);
1113 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]);
1114
1115 return 0;
1116 }
1117
1118 static int
ural_sendprot(struct ural_softc * sc,const struct mbuf * m,struct ieee80211_node * ni,int prot,int rate)1119 ural_sendprot(struct ural_softc *sc,
1120 const struct mbuf *m, struct ieee80211_node *ni, int prot, int rate)
1121 {
1122 struct ieee80211com *ic = ni->ni_ic;
1123 struct ural_tx_data *data;
1124 struct mbuf *mprot;
1125 int protrate, flags;
1126
1127 mprot = ieee80211_alloc_prot(ni, m, rate, prot);
1128 if (mprot == NULL) {
1129 if_inc_counter(ni->ni_vap->iv_ifp, IFCOUNTER_OERRORS, 1);
1130 device_printf(sc->sc_dev,
1131 "could not allocate mbuf for protection mode %d\n", prot);
1132 return ENOBUFS;
1133 }
1134
1135 protrate = ieee80211_ctl_rate(ic->ic_rt, rate);
1136 flags = RAL_TX_RETRY(7);
1137 if (prot == IEEE80211_PROT_RTSCTS)
1138 flags |= RAL_TX_ACK;
1139
1140 data = STAILQ_FIRST(&sc->tx_free);
1141 STAILQ_REMOVE_HEAD(&sc->tx_free, next);
1142 sc->tx_nfree--;
1143
1144 data->m = mprot;
1145 data->ni = ieee80211_ref_node(ni);
1146 data->rate = protrate;
1147 ural_setup_tx_desc(sc, &data->desc, flags, mprot->m_pkthdr.len, protrate);
1148
1149 STAILQ_INSERT_TAIL(&sc->tx_q, data, next);
1150 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]);
1151
1152 return 0;
1153 }
1154
1155 static int
ural_tx_raw(struct ural_softc * sc,struct mbuf * m0,struct ieee80211_node * ni,const struct ieee80211_bpf_params * params)1156 ural_tx_raw(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni,
1157 const struct ieee80211_bpf_params *params)
1158 {
1159 struct ieee80211com *ic = ni->ni_ic;
1160 struct ural_tx_data *data;
1161 uint32_t flags;
1162 int error;
1163 int rate;
1164
1165 RAL_LOCK_ASSERT(sc, MA_OWNED);
1166 KASSERT(params != NULL, ("no raw xmit params"));
1167
1168 rate = params->ibp_rate0;
1169 if (!ieee80211_isratevalid(ic->ic_rt, rate)) {
1170 m_freem(m0);
1171 return EINVAL;
1172 }
1173 flags = 0;
1174 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0)
1175 flags |= RAL_TX_ACK;
1176 if (params->ibp_flags & (IEEE80211_BPF_RTS|IEEE80211_BPF_CTS)) {
1177 error = ural_sendprot(sc, m0, ni,
1178 params->ibp_flags & IEEE80211_BPF_RTS ?
1179 IEEE80211_PROT_RTSCTS : IEEE80211_PROT_CTSONLY,
1180 rate);
1181 if (error || sc->tx_nfree == 0) {
1182 m_freem(m0);
1183 return ENOBUFS;
1184 }
1185 flags |= RAL_TX_IFS_SIFS;
1186 }
1187
1188 data = STAILQ_FIRST(&sc->tx_free);
1189 STAILQ_REMOVE_HEAD(&sc->tx_free, next);
1190 sc->tx_nfree--;
1191
1192 data->m = m0;
1193 data->ni = ni;
1194 data->rate = rate;
1195
1196 /* XXX need to setup descriptor ourself */
1197 ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, rate);
1198
1199 DPRINTFN(10, "sending raw frame len=%u rate=%u\n",
1200 m0->m_pkthdr.len, rate);
1201
1202 STAILQ_INSERT_TAIL(&sc->tx_q, data, next);
1203 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]);
1204
1205 return 0;
1206 }
1207
1208 static int
ural_tx_data(struct ural_softc * sc,struct mbuf * m0,struct ieee80211_node * ni)1209 ural_tx_data(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni)
1210 {
1211 struct ieee80211vap *vap = ni->ni_vap;
1212 struct ieee80211com *ic = ni->ni_ic;
1213 struct ural_tx_data *data;
1214 struct ieee80211_frame *wh;
1215 const struct ieee80211_txparam *tp = ni->ni_txparms;
1216 struct ieee80211_key *k;
1217 uint32_t flags = 0;
1218 uint16_t dur;
1219 int error, rate;
1220
1221 RAL_LOCK_ASSERT(sc, MA_OWNED);
1222
1223 wh = mtod(m0, struct ieee80211_frame *);
1224
1225 if (m0->m_flags & M_EAPOL)
1226 rate = tp->mgmtrate;
1227 else if (IEEE80211_IS_MULTICAST(wh->i_addr1))
1228 rate = tp->mcastrate;
1229 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE)
1230 rate = tp->ucastrate;
1231 else {
1232 (void) ieee80211_ratectl_rate(ni, NULL, 0);
1233 rate = ieee80211_node_get_txrate_dot11rate(ni);
1234 }
1235
1236 ieee80211_output_seqno_assign(ni, -1, m0);
1237
1238 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
1239 k = ieee80211_crypto_encap(ni, m0);
1240 if (k == NULL) {
1241 m_freem(m0);
1242 return ENOBUFS;
1243 }
1244 /* packet header may have moved, reset our local pointer */
1245 wh = mtod(m0, struct ieee80211_frame *);
1246 }
1247
1248 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1249 int prot = IEEE80211_PROT_NONE;
1250 if (m0->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold)
1251 prot = IEEE80211_PROT_RTSCTS;
1252 else if ((ic->ic_flags & IEEE80211_F_USEPROT) &&
1253 ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM)
1254 prot = ic->ic_protmode;
1255 if (prot != IEEE80211_PROT_NONE) {
1256 error = ural_sendprot(sc, m0, ni, prot, rate);
1257 if (error || sc->tx_nfree == 0) {
1258 m_freem(m0);
1259 return ENOBUFS;
1260 }
1261 flags |= RAL_TX_IFS_SIFS;
1262 }
1263 }
1264
1265 data = STAILQ_FIRST(&sc->tx_free);
1266 STAILQ_REMOVE_HEAD(&sc->tx_free, next);
1267 sc->tx_nfree--;
1268
1269 data->m = m0;
1270 data->ni = ni;
1271 data->rate = rate;
1272
1273 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1274 flags |= RAL_TX_ACK;
1275 flags |= RAL_TX_RETRY(7);
1276
1277 dur = ieee80211_ack_duration(ic->ic_rt, rate,
1278 ic->ic_flags & IEEE80211_F_SHPREAMBLE);
1279 USETW(wh->i_dur, dur);
1280 }
1281
1282 ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, rate);
1283
1284 DPRINTFN(10, "sending data frame len=%u rate=%u\n",
1285 m0->m_pkthdr.len, rate);
1286
1287 STAILQ_INSERT_TAIL(&sc->tx_q, data, next);
1288 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]);
1289
1290 return 0;
1291 }
1292
1293 static int
ural_transmit(struct ieee80211com * ic,struct mbuf * m)1294 ural_transmit(struct ieee80211com *ic, struct mbuf *m)
1295 {
1296 struct ural_softc *sc = ic->ic_softc;
1297 int error;
1298
1299 RAL_LOCK(sc);
1300 if (!sc->sc_running) {
1301 RAL_UNLOCK(sc);
1302 return (ENXIO);
1303 }
1304 error = mbufq_enqueue(&sc->sc_snd, m);
1305 if (error) {
1306 RAL_UNLOCK(sc);
1307 return (error);
1308 }
1309 ural_start(sc);
1310 RAL_UNLOCK(sc);
1311
1312 return (0);
1313 }
1314
1315 static void
ural_start(struct ural_softc * sc)1316 ural_start(struct ural_softc *sc)
1317 {
1318 struct ieee80211_node *ni;
1319 struct mbuf *m;
1320
1321 RAL_LOCK_ASSERT(sc, MA_OWNED);
1322
1323 if (sc->sc_running == 0)
1324 return;
1325
1326 while (sc->tx_nfree >= RAL_TX_MINFREE &&
1327 (m = mbufq_dequeue(&sc->sc_snd)) != NULL) {
1328 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif;
1329 if (ural_tx_data(sc, m, ni) != 0) {
1330 if_inc_counter(ni->ni_vap->iv_ifp,
1331 IFCOUNTER_OERRORS, 1);
1332 ieee80211_free_node(ni);
1333 break;
1334 }
1335 }
1336 }
1337
1338 static void
ural_parent(struct ieee80211com * ic)1339 ural_parent(struct ieee80211com *ic)
1340 {
1341 struct ural_softc *sc = ic->ic_softc;
1342 int startall = 0;
1343
1344 RAL_LOCK(sc);
1345 if (sc->sc_detached) {
1346 RAL_UNLOCK(sc);
1347 return;
1348 }
1349 if (ic->ic_nrunning > 0) {
1350 if (sc->sc_running == 0) {
1351 ural_init(sc);
1352 startall = 1;
1353 } else
1354 ural_setpromisc(sc);
1355 } else if (sc->sc_running)
1356 ural_stop(sc);
1357 RAL_UNLOCK(sc);
1358 if (startall)
1359 ieee80211_start_all(ic);
1360 }
1361
1362 static void
ural_set_testmode(struct ural_softc * sc)1363 ural_set_testmode(struct ural_softc *sc)
1364 {
1365 struct usb_device_request req;
1366 usb_error_t error;
1367
1368 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
1369 req.bRequest = RAL_VENDOR_REQUEST;
1370 USETW(req.wValue, 4);
1371 USETW(req.wIndex, 1);
1372 USETW(req.wLength, 0);
1373
1374 error = ural_do_request(sc, &req, NULL);
1375 if (error != 0) {
1376 device_printf(sc->sc_dev, "could not set test mode: %s\n",
1377 usbd_errstr(error));
1378 }
1379 }
1380
1381 static void
ural_eeprom_read(struct ural_softc * sc,uint16_t addr,void * buf,int len)1382 ural_eeprom_read(struct ural_softc *sc, uint16_t addr, void *buf, int len)
1383 {
1384 struct usb_device_request req;
1385 usb_error_t error;
1386
1387 req.bmRequestType = UT_READ_VENDOR_DEVICE;
1388 req.bRequest = RAL_READ_EEPROM;
1389 USETW(req.wValue, 0);
1390 USETW(req.wIndex, addr);
1391 USETW(req.wLength, len);
1392
1393 error = ural_do_request(sc, &req, buf);
1394 if (error != 0) {
1395 device_printf(sc->sc_dev, "could not read EEPROM: %s\n",
1396 usbd_errstr(error));
1397 }
1398 }
1399
1400 static uint16_t
ural_read(struct ural_softc * sc,uint16_t reg)1401 ural_read(struct ural_softc *sc, uint16_t reg)
1402 {
1403 struct usb_device_request req;
1404 usb_error_t error;
1405 uint16_t val;
1406
1407 req.bmRequestType = UT_READ_VENDOR_DEVICE;
1408 req.bRequest = RAL_READ_MAC;
1409 USETW(req.wValue, 0);
1410 USETW(req.wIndex, reg);
1411 USETW(req.wLength, sizeof (uint16_t));
1412
1413 error = ural_do_request(sc, &req, &val);
1414 if (error != 0) {
1415 device_printf(sc->sc_dev, "could not read MAC register: %s\n",
1416 usbd_errstr(error));
1417 return 0;
1418 }
1419
1420 return le16toh(val);
1421 }
1422
1423 static void
ural_read_multi(struct ural_softc * sc,uint16_t reg,void * buf,int len)1424 ural_read_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len)
1425 {
1426 struct usb_device_request req;
1427 usb_error_t error;
1428
1429 req.bmRequestType = UT_READ_VENDOR_DEVICE;
1430 req.bRequest = RAL_READ_MULTI_MAC;
1431 USETW(req.wValue, 0);
1432 USETW(req.wIndex, reg);
1433 USETW(req.wLength, len);
1434
1435 error = ural_do_request(sc, &req, buf);
1436 if (error != 0) {
1437 device_printf(sc->sc_dev, "could not read MAC register: %s\n",
1438 usbd_errstr(error));
1439 }
1440 }
1441
1442 static void
ural_write(struct ural_softc * sc,uint16_t reg,uint16_t val)1443 ural_write(struct ural_softc *sc, uint16_t reg, uint16_t val)
1444 {
1445 struct usb_device_request req;
1446 usb_error_t error;
1447
1448 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
1449 req.bRequest = RAL_WRITE_MAC;
1450 USETW(req.wValue, val);
1451 USETW(req.wIndex, reg);
1452 USETW(req.wLength, 0);
1453
1454 error = ural_do_request(sc, &req, NULL);
1455 if (error != 0) {
1456 device_printf(sc->sc_dev, "could not write MAC register: %s\n",
1457 usbd_errstr(error));
1458 }
1459 }
1460
1461 static void
ural_write_multi(struct ural_softc * sc,uint16_t reg,void * buf,int len)1462 ural_write_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len)
1463 {
1464 struct usb_device_request req;
1465 usb_error_t error;
1466
1467 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
1468 req.bRequest = RAL_WRITE_MULTI_MAC;
1469 USETW(req.wValue, 0);
1470 USETW(req.wIndex, reg);
1471 USETW(req.wLength, len);
1472
1473 error = ural_do_request(sc, &req, buf);
1474 if (error != 0) {
1475 device_printf(sc->sc_dev, "could not write MAC register: %s\n",
1476 usbd_errstr(error));
1477 }
1478 }
1479
1480 static void
ural_bbp_write(struct ural_softc * sc,uint8_t reg,uint8_t val)1481 ural_bbp_write(struct ural_softc *sc, uint8_t reg, uint8_t val)
1482 {
1483 uint16_t tmp;
1484 int ntries;
1485
1486 for (ntries = 0; ntries < 100; ntries++) {
1487 if (!(ural_read(sc, RAL_PHY_CSR8) & RAL_BBP_BUSY))
1488 break;
1489 if (ural_pause(sc, hz / 100))
1490 break;
1491 }
1492 if (ntries == 100) {
1493 device_printf(sc->sc_dev, "could not write to BBP\n");
1494 return;
1495 }
1496
1497 tmp = reg << 8 | val;
1498 ural_write(sc, RAL_PHY_CSR7, tmp);
1499 }
1500
1501 static uint8_t
ural_bbp_read(struct ural_softc * sc,uint8_t reg)1502 ural_bbp_read(struct ural_softc *sc, uint8_t reg)
1503 {
1504 uint16_t val;
1505 int ntries;
1506
1507 val = RAL_BBP_WRITE | reg << 8;
1508 ural_write(sc, RAL_PHY_CSR7, val);
1509
1510 for (ntries = 0; ntries < 100; ntries++) {
1511 if (!(ural_read(sc, RAL_PHY_CSR8) & RAL_BBP_BUSY))
1512 break;
1513 if (ural_pause(sc, hz / 100))
1514 break;
1515 }
1516 if (ntries == 100) {
1517 device_printf(sc->sc_dev, "could not read BBP\n");
1518 return 0;
1519 }
1520
1521 return ural_read(sc, RAL_PHY_CSR7) & 0xff;
1522 }
1523
1524 static void
ural_rf_write(struct ural_softc * sc,uint8_t reg,uint32_t val)1525 ural_rf_write(struct ural_softc *sc, uint8_t reg, uint32_t val)
1526 {
1527 uint32_t tmp;
1528 int ntries;
1529
1530 for (ntries = 0; ntries < 100; ntries++) {
1531 if (!(ural_read(sc, RAL_PHY_CSR10) & RAL_RF_LOBUSY))
1532 break;
1533 if (ural_pause(sc, hz / 100))
1534 break;
1535 }
1536 if (ntries == 100) {
1537 device_printf(sc->sc_dev, "could not write to RF\n");
1538 return;
1539 }
1540
1541 tmp = RAL_RF_BUSY | RAL_RF_20BIT | (val & 0xfffff) << 2 | (reg & 0x3);
1542 ural_write(sc, RAL_PHY_CSR9, tmp & 0xffff);
1543 ural_write(sc, RAL_PHY_CSR10, tmp >> 16);
1544
1545 /* remember last written value in sc */
1546 sc->rf_regs[reg] = val;
1547
1548 DPRINTFN(15, "RF R[%u] <- 0x%05x\n", reg & 0x3, val & 0xfffff);
1549 }
1550
1551 static void
ural_scan_start(struct ieee80211com * ic)1552 ural_scan_start(struct ieee80211com *ic)
1553 {
1554 struct ural_softc *sc = ic->ic_softc;
1555
1556 RAL_LOCK(sc);
1557 ural_write(sc, RAL_TXRX_CSR19, 0);
1558 ural_set_bssid(sc, ieee80211broadcastaddr);
1559 RAL_UNLOCK(sc);
1560 }
1561
1562 static void
ural_scan_end(struct ieee80211com * ic)1563 ural_scan_end(struct ieee80211com *ic)
1564 {
1565 struct ural_softc *sc = ic->ic_softc;
1566
1567 RAL_LOCK(sc);
1568 ural_enable_tsf_sync(sc);
1569 ural_set_bssid(sc, sc->sc_bssid);
1570 RAL_UNLOCK(sc);
1571
1572 }
1573
1574 static void
ural_getradiocaps(struct ieee80211com * ic,int maxchans,int * nchans,struct ieee80211_channel chans[])1575 ural_getradiocaps(struct ieee80211com *ic,
1576 int maxchans, int *nchans, struct ieee80211_channel chans[])
1577 {
1578 struct ural_softc *sc = ic->ic_softc;
1579 uint8_t bands[IEEE80211_MODE_BYTES];
1580
1581 memset(bands, 0, sizeof(bands));
1582 setbit(bands, IEEE80211_MODE_11B);
1583 setbit(bands, IEEE80211_MODE_11G);
1584 ieee80211_add_channels_default_2ghz(chans, maxchans, nchans, bands, 0);
1585
1586 if (sc->rf_rev == RAL_RF_5222) {
1587 setbit(bands, IEEE80211_MODE_11A);
1588 ieee80211_add_channel_list_5ghz(chans, maxchans, nchans,
1589 ural_chan_5ghz, nitems(ural_chan_5ghz), bands, 0);
1590 }
1591 }
1592
1593 static void
ural_set_channel(struct ieee80211com * ic)1594 ural_set_channel(struct ieee80211com *ic)
1595 {
1596 struct ural_softc *sc = ic->ic_softc;
1597
1598 RAL_LOCK(sc);
1599 ural_set_chan(sc, ic->ic_curchan);
1600 RAL_UNLOCK(sc);
1601 }
1602
1603 static void
ural_set_chan(struct ural_softc * sc,struct ieee80211_channel * c)1604 ural_set_chan(struct ural_softc *sc, struct ieee80211_channel *c)
1605 {
1606 struct ieee80211com *ic = &sc->sc_ic;
1607 uint8_t power, tmp;
1608 int i, chan;
1609
1610 chan = ieee80211_chan2ieee(ic, c);
1611 if (chan == 0 || chan == IEEE80211_CHAN_ANY)
1612 return;
1613
1614 if (IEEE80211_IS_CHAN_2GHZ(c))
1615 power = min(sc->txpow[chan - 1], 31);
1616 else
1617 power = 31;
1618
1619 /* adjust txpower using ifconfig settings */
1620 power -= (100 - ic->ic_txpowlimit) / 8;
1621
1622 DPRINTFN(2, "setting channel to %u, txpower to %u\n", chan, power);
1623
1624 switch (sc->rf_rev) {
1625 case RAL_RF_2522:
1626 ural_rf_write(sc, RAL_RF1, 0x00814);
1627 ural_rf_write(sc, RAL_RF2, ural_rf2522_r2[chan - 1]);
1628 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040);
1629 break;
1630
1631 case RAL_RF_2523:
1632 ural_rf_write(sc, RAL_RF1, 0x08804);
1633 ural_rf_write(sc, RAL_RF2, ural_rf2523_r2[chan - 1]);
1634 ural_rf_write(sc, RAL_RF3, power << 7 | 0x38044);
1635 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286);
1636 break;
1637
1638 case RAL_RF_2524:
1639 ural_rf_write(sc, RAL_RF1, 0x0c808);
1640 ural_rf_write(sc, RAL_RF2, ural_rf2524_r2[chan - 1]);
1641 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040);
1642 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286);
1643 break;
1644
1645 case RAL_RF_2525:
1646 ural_rf_write(sc, RAL_RF1, 0x08808);
1647 ural_rf_write(sc, RAL_RF2, ural_rf2525_hi_r2[chan - 1]);
1648 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044);
1649 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286);
1650
1651 ural_rf_write(sc, RAL_RF1, 0x08808);
1652 ural_rf_write(sc, RAL_RF2, ural_rf2525_r2[chan - 1]);
1653 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044);
1654 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286);
1655 break;
1656
1657 case RAL_RF_2525E:
1658 ural_rf_write(sc, RAL_RF1, 0x08808);
1659 ural_rf_write(sc, RAL_RF2, ural_rf2525e_r2[chan - 1]);
1660 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044);
1661 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00286 : 0x00282);
1662 break;
1663
1664 case RAL_RF_2526:
1665 ural_rf_write(sc, RAL_RF2, ural_rf2526_hi_r2[chan - 1]);
1666 ural_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381);
1667 ural_rf_write(sc, RAL_RF1, 0x08804);
1668
1669 ural_rf_write(sc, RAL_RF2, ural_rf2526_r2[chan - 1]);
1670 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044);
1671 ural_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381);
1672 break;
1673
1674 /* dual-band RF */
1675 case RAL_RF_5222:
1676 for (i = 0; ural_rf5222[i].chan != chan; i++);
1677
1678 ural_rf_write(sc, RAL_RF1, ural_rf5222[i].r1);
1679 ural_rf_write(sc, RAL_RF2, ural_rf5222[i].r2);
1680 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040);
1681 ural_rf_write(sc, RAL_RF4, ural_rf5222[i].r4);
1682 break;
1683 }
1684
1685 if (ic->ic_opmode != IEEE80211_M_MONITOR &&
1686 (ic->ic_flags & IEEE80211_F_SCAN) == 0) {
1687 /* set Japan filter bit for channel 14 */
1688 tmp = ural_bbp_read(sc, 70);
1689
1690 tmp &= ~RAL_JAPAN_FILTER;
1691 if (chan == 14)
1692 tmp |= RAL_JAPAN_FILTER;
1693
1694 ural_bbp_write(sc, 70, tmp);
1695
1696 /* clear CRC errors */
1697 ural_read(sc, RAL_STA_CSR0);
1698
1699 ural_pause(sc, hz / 100);
1700 ural_disable_rf_tune(sc);
1701 }
1702
1703 /* XXX doesn't belong here */
1704 /* update basic rate set */
1705 ural_set_basicrates(sc, c);
1706
1707 /* give the hardware some time to do the switchover */
1708 ural_pause(sc, hz / 100);
1709 }
1710
1711 /*
1712 * Disable RF auto-tuning.
1713 */
1714 static void
ural_disable_rf_tune(struct ural_softc * sc)1715 ural_disable_rf_tune(struct ural_softc *sc)
1716 {
1717 uint32_t tmp;
1718
1719 if (sc->rf_rev != RAL_RF_2523) {
1720 tmp = sc->rf_regs[RAL_RF1] & ~RAL_RF1_AUTOTUNE;
1721 ural_rf_write(sc, RAL_RF1, tmp);
1722 }
1723
1724 tmp = sc->rf_regs[RAL_RF3] & ~RAL_RF3_AUTOTUNE;
1725 ural_rf_write(sc, RAL_RF3, tmp);
1726
1727 DPRINTFN(2, "disabling RF autotune\n");
1728 }
1729
1730 /*
1731 * Refer to IEEE Std 802.11-1999 pp. 123 for more information on TSF
1732 * synchronization.
1733 */
1734 static void
ural_enable_tsf_sync(struct ural_softc * sc)1735 ural_enable_tsf_sync(struct ural_softc *sc)
1736 {
1737 struct ieee80211com *ic = &sc->sc_ic;
1738 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
1739 uint16_t logcwmin, preload, tmp;
1740
1741 /* first, disable TSF synchronization */
1742 ural_write(sc, RAL_TXRX_CSR19, 0);
1743
1744 tmp = (16 * vap->iv_bss->ni_intval) << 4;
1745 ural_write(sc, RAL_TXRX_CSR18, tmp);
1746
1747 logcwmin = (ic->ic_opmode == IEEE80211_M_IBSS) ? 2 : 0;
1748 preload = (ic->ic_opmode == IEEE80211_M_IBSS) ? 320 : 6;
1749 tmp = logcwmin << 12 | preload;
1750 ural_write(sc, RAL_TXRX_CSR20, tmp);
1751
1752 /* finally, enable TSF synchronization */
1753 tmp = RAL_ENABLE_TSF | RAL_ENABLE_TBCN;
1754 if (ic->ic_opmode == IEEE80211_M_STA)
1755 tmp |= RAL_ENABLE_TSF_SYNC(1);
1756 else
1757 tmp |= RAL_ENABLE_TSF_SYNC(2) | RAL_ENABLE_BEACON_GENERATOR;
1758 ural_write(sc, RAL_TXRX_CSR19, tmp);
1759
1760 DPRINTF("enabling TSF synchronization\n");
1761 }
1762
1763 static void
ural_enable_tsf(struct ural_softc * sc)1764 ural_enable_tsf(struct ural_softc *sc)
1765 {
1766 /* first, disable TSF synchronization */
1767 ural_write(sc, RAL_TXRX_CSR19, 0);
1768 ural_write(sc, RAL_TXRX_CSR19, RAL_ENABLE_TSF | RAL_ENABLE_TSF_SYNC(2));
1769 }
1770
1771 #define RAL_RXTX_TURNAROUND 5 /* us */
1772 static void
ural_update_slot(struct ural_softc * sc)1773 ural_update_slot(struct ural_softc *sc)
1774 {
1775 struct ieee80211com *ic = &sc->sc_ic;
1776 uint16_t slottime, sifs, eifs;
1777
1778 slottime = IEEE80211_GET_SLOTTIME(ic);
1779
1780 /*
1781 * These settings may sound a bit inconsistent but this is what the
1782 * reference driver does.
1783 */
1784 if (ic->ic_curmode == IEEE80211_MODE_11B) {
1785 sifs = 16 - RAL_RXTX_TURNAROUND;
1786 eifs = 364;
1787 } else {
1788 sifs = 10 - RAL_RXTX_TURNAROUND;
1789 eifs = 64;
1790 }
1791
1792 ural_write(sc, RAL_MAC_CSR10, slottime);
1793 ural_write(sc, RAL_MAC_CSR11, sifs);
1794 ural_write(sc, RAL_MAC_CSR12, eifs);
1795 }
1796
1797 static void
ural_set_txpreamble(struct ural_softc * sc)1798 ural_set_txpreamble(struct ural_softc *sc)
1799 {
1800 struct ieee80211com *ic = &sc->sc_ic;
1801 uint16_t tmp;
1802
1803 tmp = ural_read(sc, RAL_TXRX_CSR10);
1804
1805 tmp &= ~RAL_SHORT_PREAMBLE;
1806 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
1807 tmp |= RAL_SHORT_PREAMBLE;
1808
1809 ural_write(sc, RAL_TXRX_CSR10, tmp);
1810 }
1811
1812 static void
ural_set_basicrates(struct ural_softc * sc,const struct ieee80211_channel * c)1813 ural_set_basicrates(struct ural_softc *sc, const struct ieee80211_channel *c)
1814 {
1815 /* XXX wrong, take from rate set */
1816 /* update basic rate set */
1817 if (IEEE80211_IS_CHAN_5GHZ(c)) {
1818 /* 11a basic rates: 6, 12, 24Mbps */
1819 ural_write(sc, RAL_TXRX_CSR11, 0x150);
1820 } else if (IEEE80211_IS_CHAN_ANYG(c)) {
1821 /* 11g basic rates: 1, 2, 5.5, 11, 6, 12, 24Mbps */
1822 ural_write(sc, RAL_TXRX_CSR11, 0x15f);
1823 } else {
1824 /* 11b basic rates: 1, 2Mbps */
1825 ural_write(sc, RAL_TXRX_CSR11, 0x3);
1826 }
1827 }
1828
1829 static void
ural_set_bssid(struct ural_softc * sc,const uint8_t * bssid)1830 ural_set_bssid(struct ural_softc *sc, const uint8_t *bssid)
1831 {
1832 uint16_t tmp;
1833
1834 tmp = bssid[0] | bssid[1] << 8;
1835 ural_write(sc, RAL_MAC_CSR5, tmp);
1836
1837 tmp = bssid[2] | bssid[3] << 8;
1838 ural_write(sc, RAL_MAC_CSR6, tmp);
1839
1840 tmp = bssid[4] | bssid[5] << 8;
1841 ural_write(sc, RAL_MAC_CSR7, tmp);
1842
1843 DPRINTF("setting BSSID to %6D\n", bssid, ":");
1844 }
1845
1846 static void
ural_set_macaddr(struct ural_softc * sc,const uint8_t * addr)1847 ural_set_macaddr(struct ural_softc *sc, const uint8_t *addr)
1848 {
1849 uint16_t tmp;
1850
1851 tmp = addr[0] | addr[1] << 8;
1852 ural_write(sc, RAL_MAC_CSR2, tmp);
1853
1854 tmp = addr[2] | addr[3] << 8;
1855 ural_write(sc, RAL_MAC_CSR3, tmp);
1856
1857 tmp = addr[4] | addr[5] << 8;
1858 ural_write(sc, RAL_MAC_CSR4, tmp);
1859
1860 DPRINTF("setting MAC address to %6D\n", addr, ":");
1861 }
1862
1863 static void
ural_setpromisc(struct ural_softc * sc)1864 ural_setpromisc(struct ural_softc *sc)
1865 {
1866 uint32_t tmp;
1867
1868 tmp = ural_read(sc, RAL_TXRX_CSR2);
1869
1870 tmp &= ~RAL_DROP_NOT_TO_ME;
1871 if (sc->sc_ic.ic_promisc == 0)
1872 tmp |= RAL_DROP_NOT_TO_ME;
1873
1874 ural_write(sc, RAL_TXRX_CSR2, tmp);
1875
1876 DPRINTF("%s promiscuous mode\n", sc->sc_ic.ic_promisc ?
1877 "entering" : "leaving");
1878 }
1879
1880 static void
ural_update_promisc(struct ieee80211com * ic)1881 ural_update_promisc(struct ieee80211com *ic)
1882 {
1883 struct ural_softc *sc = ic->ic_softc;
1884
1885 RAL_LOCK(sc);
1886 if (sc->sc_running)
1887 ural_setpromisc(sc);
1888 RAL_UNLOCK(sc);
1889 }
1890
1891 static const char *
ural_get_rf(int rev)1892 ural_get_rf(int rev)
1893 {
1894 switch (rev) {
1895 case RAL_RF_2522: return "RT2522";
1896 case RAL_RF_2523: return "RT2523";
1897 case RAL_RF_2524: return "RT2524";
1898 case RAL_RF_2525: return "RT2525";
1899 case RAL_RF_2525E: return "RT2525e";
1900 case RAL_RF_2526: return "RT2526";
1901 case RAL_RF_5222: return "RT5222";
1902 default: return "unknown";
1903 }
1904 }
1905
1906 static void
ural_read_eeprom(struct ural_softc * sc)1907 ural_read_eeprom(struct ural_softc *sc)
1908 {
1909 struct ieee80211com *ic = &sc->sc_ic;
1910 uint16_t val;
1911
1912 ural_eeprom_read(sc, RAL_EEPROM_CONFIG0, &val, 2);
1913 val = le16toh(val);
1914 sc->rf_rev = (val >> 11) & 0x7;
1915 sc->hw_radio = (val >> 10) & 0x1;
1916 sc->led_mode = (val >> 6) & 0x7;
1917 sc->rx_ant = (val >> 4) & 0x3;
1918 sc->tx_ant = (val >> 2) & 0x3;
1919 sc->nb_ant = val & 0x3;
1920
1921 /* read MAC address */
1922 ural_eeprom_read(sc, RAL_EEPROM_ADDRESS, ic->ic_macaddr, 6);
1923
1924 /* read default values for BBP registers */
1925 ural_eeprom_read(sc, RAL_EEPROM_BBP_BASE, sc->bbp_prom, 2 * 16);
1926
1927 /* read Tx power for all b/g channels */
1928 ural_eeprom_read(sc, RAL_EEPROM_TXPOWER, sc->txpow, 14);
1929 }
1930
1931 static int
ural_bbp_init(struct ural_softc * sc)1932 ural_bbp_init(struct ural_softc *sc)
1933 {
1934 int i, ntries;
1935
1936 /* wait for BBP to be ready */
1937 for (ntries = 0; ntries < 100; ntries++) {
1938 if (ural_bbp_read(sc, RAL_BBP_VERSION) != 0)
1939 break;
1940 if (ural_pause(sc, hz / 100))
1941 break;
1942 }
1943 if (ntries == 100) {
1944 device_printf(sc->sc_dev, "timeout waiting for BBP\n");
1945 return EIO;
1946 }
1947
1948 /* initialize BBP registers to default values */
1949 for (i = 0; i < nitems(ural_def_bbp); i++)
1950 ural_bbp_write(sc, ural_def_bbp[i].reg, ural_def_bbp[i].val);
1951
1952 #if 0
1953 /* initialize BBP registers to values stored in EEPROM */
1954 for (i = 0; i < 16; i++) {
1955 if (sc->bbp_prom[i].reg == 0xff)
1956 continue;
1957 ural_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val);
1958 }
1959 #endif
1960
1961 return 0;
1962 }
1963
1964 static void
ural_set_txantenna(struct ural_softc * sc,int antenna)1965 ural_set_txantenna(struct ural_softc *sc, int antenna)
1966 {
1967 uint16_t tmp;
1968 uint8_t tx;
1969
1970 tx = ural_bbp_read(sc, RAL_BBP_TX) & ~RAL_BBP_ANTMASK;
1971 if (antenna == 1)
1972 tx |= RAL_BBP_ANTA;
1973 else if (antenna == 2)
1974 tx |= RAL_BBP_ANTB;
1975 else
1976 tx |= RAL_BBP_DIVERSITY;
1977
1978 /* need to force I/Q flip for RF 2525e, 2526 and 5222 */
1979 if (sc->rf_rev == RAL_RF_2525E || sc->rf_rev == RAL_RF_2526 ||
1980 sc->rf_rev == RAL_RF_5222)
1981 tx |= RAL_BBP_FLIPIQ;
1982
1983 ural_bbp_write(sc, RAL_BBP_TX, tx);
1984
1985 /* update values in PHY_CSR5 and PHY_CSR6 */
1986 tmp = ural_read(sc, RAL_PHY_CSR5) & ~0x7;
1987 ural_write(sc, RAL_PHY_CSR5, tmp | (tx & 0x7));
1988
1989 tmp = ural_read(sc, RAL_PHY_CSR6) & ~0x7;
1990 ural_write(sc, RAL_PHY_CSR6, tmp | (tx & 0x7));
1991 }
1992
1993 static void
ural_set_rxantenna(struct ural_softc * sc,int antenna)1994 ural_set_rxantenna(struct ural_softc *sc, int antenna)
1995 {
1996 uint8_t rx;
1997
1998 rx = ural_bbp_read(sc, RAL_BBP_RX) & ~RAL_BBP_ANTMASK;
1999 if (antenna == 1)
2000 rx |= RAL_BBP_ANTA;
2001 else if (antenna == 2)
2002 rx |= RAL_BBP_ANTB;
2003 else
2004 rx |= RAL_BBP_DIVERSITY;
2005
2006 /* need to force no I/Q flip for RF 2525e and 2526 */
2007 if (sc->rf_rev == RAL_RF_2525E || sc->rf_rev == RAL_RF_2526)
2008 rx &= ~RAL_BBP_FLIPIQ;
2009
2010 ural_bbp_write(sc, RAL_BBP_RX, rx);
2011 }
2012
2013 static void
ural_init(struct ural_softc * sc)2014 ural_init(struct ural_softc *sc)
2015 {
2016 struct ieee80211com *ic = &sc->sc_ic;
2017 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
2018 uint16_t tmp;
2019 int i, ntries;
2020
2021 RAL_LOCK_ASSERT(sc, MA_OWNED);
2022
2023 ural_set_testmode(sc);
2024 ural_write(sc, 0x308, 0x00f0); /* XXX magic */
2025
2026 ural_stop(sc);
2027
2028 /* initialize MAC registers to default values */
2029 for (i = 0; i < nitems(ural_def_mac); i++)
2030 ural_write(sc, ural_def_mac[i].reg, ural_def_mac[i].val);
2031
2032 /* wait for BBP and RF to wake up (this can take a long time!) */
2033 for (ntries = 0; ntries < 100; ntries++) {
2034 tmp = ural_read(sc, RAL_MAC_CSR17);
2035 if ((tmp & (RAL_BBP_AWAKE | RAL_RF_AWAKE)) ==
2036 (RAL_BBP_AWAKE | RAL_RF_AWAKE))
2037 break;
2038 if (ural_pause(sc, hz / 100))
2039 break;
2040 }
2041 if (ntries == 100) {
2042 device_printf(sc->sc_dev,
2043 "timeout waiting for BBP/RF to wakeup\n");
2044 goto fail;
2045 }
2046
2047 /* we're ready! */
2048 ural_write(sc, RAL_MAC_CSR1, RAL_HOST_READY);
2049
2050 /* set basic rate set (will be updated later) */
2051 ural_write(sc, RAL_TXRX_CSR11, 0x15f);
2052
2053 if (ural_bbp_init(sc) != 0)
2054 goto fail;
2055
2056 ural_set_chan(sc, ic->ic_curchan);
2057
2058 /* clear statistic registers (STA_CSR0 to STA_CSR10) */
2059 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof sc->sta);
2060
2061 ural_set_txantenna(sc, sc->tx_ant);
2062 ural_set_rxantenna(sc, sc->rx_ant);
2063
2064 ural_set_macaddr(sc, vap ? vap->iv_myaddr : ic->ic_macaddr);
2065
2066 /*
2067 * Allocate Tx and Rx xfer queues.
2068 */
2069 ural_setup_tx_list(sc);
2070
2071 /* kick Rx */
2072 tmp = RAL_DROP_PHY | RAL_DROP_CRC;
2073 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
2074 tmp |= RAL_DROP_CTL | RAL_DROP_BAD_VERSION;
2075 if (ic->ic_opmode != IEEE80211_M_HOSTAP)
2076 tmp |= RAL_DROP_TODS;
2077 if (ic->ic_promisc == 0)
2078 tmp |= RAL_DROP_NOT_TO_ME;
2079 }
2080 ural_write(sc, RAL_TXRX_CSR2, tmp);
2081
2082 sc->sc_running = 1;
2083 usbd_xfer_set_stall(sc->sc_xfer[URAL_BULK_WR]);
2084 usbd_transfer_start(sc->sc_xfer[URAL_BULK_RD]);
2085 return;
2086
2087 fail: ural_stop(sc);
2088 }
2089
2090 static void
ural_stop(struct ural_softc * sc)2091 ural_stop(struct ural_softc *sc)
2092 {
2093
2094 RAL_LOCK_ASSERT(sc, MA_OWNED);
2095
2096 sc->sc_running = 0;
2097
2098 /*
2099 * Drain all the transfers, if not already drained:
2100 */
2101 RAL_UNLOCK(sc);
2102 usbd_transfer_drain(sc->sc_xfer[URAL_BULK_WR]);
2103 usbd_transfer_drain(sc->sc_xfer[URAL_BULK_RD]);
2104 RAL_LOCK(sc);
2105
2106 ural_unsetup_tx_list(sc);
2107
2108 /* disable Rx */
2109 ural_write(sc, RAL_TXRX_CSR2, RAL_DISABLE_RX);
2110 /* reset ASIC and BBP (but won't reset MAC registers!) */
2111 ural_write(sc, RAL_MAC_CSR1, RAL_RESET_ASIC | RAL_RESET_BBP);
2112 /* wait a little */
2113 ural_pause(sc, hz / 10);
2114 ural_write(sc, RAL_MAC_CSR1, 0);
2115 /* wait a little */
2116 ural_pause(sc, hz / 10);
2117 }
2118
2119 static int
ural_raw_xmit(struct ieee80211_node * ni,struct mbuf * m,const struct ieee80211_bpf_params * params)2120 ural_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
2121 const struct ieee80211_bpf_params *params)
2122 {
2123 struct ieee80211com *ic = ni->ni_ic;
2124 struct ural_softc *sc = ic->ic_softc;
2125
2126 RAL_LOCK(sc);
2127 /* prevent management frames from being sent if we're not ready */
2128 if (!sc->sc_running) {
2129 RAL_UNLOCK(sc);
2130 m_freem(m);
2131 return ENETDOWN;
2132 }
2133 if (sc->tx_nfree < RAL_TX_MINFREE) {
2134 RAL_UNLOCK(sc);
2135 m_freem(m);
2136 return EIO;
2137 }
2138
2139 if (params == NULL) {
2140 /*
2141 * Legacy path; interpret frame contents to decide
2142 * precisely how to send the frame.
2143 */
2144 if (ural_tx_mgt(sc, m, ni) != 0)
2145 goto bad;
2146 } else {
2147 /*
2148 * Caller supplied explicit parameters to use in
2149 * sending the frame.
2150 */
2151 if (ural_tx_raw(sc, m, ni, params) != 0)
2152 goto bad;
2153 }
2154 RAL_UNLOCK(sc);
2155 return 0;
2156 bad:
2157 RAL_UNLOCK(sc);
2158 return EIO; /* XXX */
2159 }
2160
2161 static void
ural_ratectl_start(struct ural_softc * sc,struct ieee80211_node * ni)2162 ural_ratectl_start(struct ural_softc *sc, struct ieee80211_node *ni)
2163 {
2164 struct ieee80211vap *vap = ni->ni_vap;
2165 struct ural_vap *uvp = URAL_VAP(vap);
2166
2167 /* clear statistic registers (STA_CSR0 to STA_CSR10) */
2168 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof sc->sta);
2169
2170 usb_callout_reset(&uvp->ratectl_ch, hz, ural_ratectl_timeout, uvp);
2171 }
2172
2173 static void
ural_ratectl_timeout(void * arg)2174 ural_ratectl_timeout(void *arg)
2175 {
2176 struct ural_vap *uvp = arg;
2177 struct ieee80211vap *vap = &uvp->vap;
2178 struct ieee80211com *ic = vap->iv_ic;
2179
2180 ieee80211_runtask(ic, &uvp->ratectl_task);
2181 }
2182
2183 static void
ural_ratectl_task(void * arg,int pending)2184 ural_ratectl_task(void *arg, int pending)
2185 {
2186 struct ural_vap *uvp = arg;
2187 struct ieee80211vap *vap = &uvp->vap;
2188 struct ural_softc *sc = vap->iv_ic->ic_softc;
2189 struct ieee80211_ratectl_tx_stats *txs = &sc->sc_txs;
2190 int fail;
2191
2192 RAL_LOCK(sc);
2193 /* read and clear statistic registers (STA_CSR0 to STA_CSR10) */
2194 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof(sc->sta));
2195
2196 txs->flags = IEEE80211_RATECTL_TX_STATS_RETRIES;
2197 txs->nsuccess = sc->sta[7] + /* TX ok w/o retry */
2198 sc->sta[8]; /* TX ok w/ retry */
2199 fail = sc->sta[9]; /* TX retry-fail count */
2200 txs->nframes = txs->nsuccess + fail;
2201 /* XXX fail * maxretry */
2202 txs->nretries = sc->sta[8] + fail;
2203
2204 ieee80211_ratectl_tx_update(vap, txs);
2205
2206 /* count TX retry-fail as Tx errors */
2207 if_inc_counter(vap->iv_ifp, IFCOUNTER_OERRORS, fail);
2208
2209 usb_callout_reset(&uvp->ratectl_ch, hz, ural_ratectl_timeout, uvp);
2210 RAL_UNLOCK(sc);
2211 }
2212
2213 static int
ural_pause(struct ural_softc * sc,int timeout)2214 ural_pause(struct ural_softc *sc, int timeout)
2215 {
2216
2217 usb_pause_mtx(&sc->sc_mtx, timeout);
2218 return (0);
2219 }
2220